37ced72a9d
lab2实验报告&lab3还有最后一个错误
2025-10-13 16:03:58 +08:00
2f8cb461d5
lab2已跑完
2025-10-12 01:44:12 +08:00
d6b780df0f
lab2离成功又近了一步
2025-10-12 00:26:44 +08:00
f8cce5b4ae
lab2还有一个报错防止改错
2025-10-12 00:14:14 +08:00
PurplePower
b9865cd612
Lab3 pipelined CPU renewed
...
- added tutorial
- fix ID reg addr invalid in certain types of instructions
- renamed some variables for better understanding
2025-08-14 16:55:53 +08:00
PurplePower
3890e3a314
Added auto answer filler and updated anchors for lab2
2025-07-20 15:55:04 +08:00
PurplePower
2caaf3d9f5
[not tested] lab2 codes updated:
...
- added environment instruction tests
- removed useless classes in CLINT.scala
- rename and comments
2025-07-19 21:21:21 +08:00
PurplePower
283eb09fd3
temp fix for lab2 on z710v1.3 board
2024-11-19 02:56:45 +08:00
PurplePower
b4141db235
updates
2024-11-19 02:09:45 +08:00
PurplePower
2b8e3eb45f
updates
2024-11-19 02:00:32 +08:00
PurplePower
ea09ee5925
updated readmes and better printing
2024-11-19 01:47:50 +08:00
PurplePower
a64186bddb
update z7-10 project scripts for other labs
2024-11-19 00:44:37 +08:00
PurplePower
8a3fae13fd
updates
2024-11-19 00:25:58 +08:00
PurplePower
0f905afe36
fixes
2024-11-18 23:17:58 +08:00
PurplePower
ddb70fa967
Fixing Z710 frequency TNS too large
...
- now Z7-10 vivado project no longer copy files to local folder, so vivado can auto update it in generate_bitstream.tcl
- Z7-10 clock freq is divided by 5 from 125MHz to 25MHz in clock_control.v
- adds Zynq7000 v1.3 for lab2
2024-11-18 22:30:07 +08:00
PurplePower
67896ab727
update csrc for correct UART printing with lower clock frequency
2024-11-18 17:06:23 +08:00
PurplePower
3e3c8ba6c0
board updates and fixes
...
- now VCD is written in all tests by default, turn it on/off in TestAnnotations.scala
- updated cmakelists.txt
- added board program scripts and sources for Zynq 7000 v1.3 2024/02 board, lab1 only currently
2024-11-18 10:50:45 +08:00
PurplePower
b9294c0bd1
added c source files back
2024-01-23 21:35:09 +08:00
PurplePower
b3738b8f63
Updated z710 README and vitis script
...
- skipped a redundant `paltform generate` in vitis_prj_run.tcl
- updated z710 README.md to be more detailed
2024-01-19 15:40:51 +08:00
PurplePower
0a8f2ecffc
updated readme for z710 board burning
2024-01-13 11:54:24 +08:00
PurplePower
ef4a567f22
Updated readme in z710 board burning
2024-01-13 11:34:17 +08:00
PurplePower
d79780a480
Fixed vivado script import path error
2023-12-27 14:01:29 +08:00
PurplePower
844cb062c2
Deleted useless verilog files
2023-12-26 01:18:54 +08:00
PurplePower
ffcc688d94
vivado-vitis uart workflow added for lab2
2023-12-25 20:50:54 +08:00
PurplePower
bcd11625a6
Fixed generate bitstream bug
...
copy not rename so vivado GUI still finds the .bit file
2023-12-25 11:53:20 +08:00
PurplePower
2a6899729b
Fixed Z7-10 generator duplicate file directory
2023-12-23 00:52:34 +08:00
TOKISAKIX\21168
d7c8c1b030
finished lab1
2023-12-12 22:14:02 +08:00
TOKISAKIX\21168
cba231d592
finished lab2
2023-12-12 00:34:29 +08:00
TOKISAKIX\21168
2bce97ff4e
add file
2023-12-11 22:20:48 +08:00
TOKISAKIX\21168
e720a0dfc2
add csrc
2023-12-11 21:54:53 +08:00
TOKISAKIX\21168
910ee11168
init repo
2023-12-11 21:50:22 +08:00
