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finished lab1

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TOKISAKIX\21168
2023-12-12 22:14:02 +08:00
parent 0b16bb935b
commit d7c8c1b030
23 changed files with 1845 additions and 128 deletions
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27
lab1/src/main/scala/board/z710/z710/Top.scala
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@@ -32,16 +32,17 @@ class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module {
// val hdmi_display = Module(new HDMIDisplay)
// val display = Module(new CharacterDisplay)
// val timer = Module(new Timer)
val uart = Module(new Uart(frequency = 32_000000, baudRate = 115200)) // 31M or 32M is good, 33M more error
// val uart = Module(new Uart(frequency = 32_000000, baudRate = 115200)) // 31M or 32M is good, 33M more error
val dummy = Module(new Dummy)
// display.io.bundle <> dummy.io.bundle
mem.io.bundle <> dummy.io.bundle
mem.io.debug_read_address := 0.U
// timer.io.bundle <> dummy.io.bundle
uart.io.bundle <> dummy.io.bundle
io.tx := uart.io.txd
uart.io.rxd := io.rx
// uart.io.bundle <> dummy.io.bundle
// io.tx := uart.io.txd
// uart.io.rxd := io.rx
io.tx := 0.U
val instruction_rom = Module(new InstructionROM(binaryFilename))
val rom_loader = Module(new ROMLoader(instruction_rom.capacity))
@@ -68,16 +69,24 @@ class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module {
mem.io.instruction_address := cpu.io.instruction_address
cpu.io.instruction := mem.io.instruction
// when(!rom_loader.io.load_finished) {
// rom_loader.io.bundle <> mem.io.bundle
// cpu.io.memory_bundle.read_data := 0.U
// }.otherwise {
// rom_loader.io.bundle.read_data := 0.U
// when(cpu.io.deviceSelect === 2.U) {
// cpu.io.memory_bundle <> uart.io.bundle
// }.otherwise {
// cpu.io.memory_bundle <> mem.io.bundle
// }
// }
when(!rom_loader.io.load_finished) {
rom_loader.io.bundle <> mem.io.bundle
cpu.io.memory_bundle.read_data := 0.U
}.otherwise {
rom_loader.io.bundle.read_data := 0.U
when(cpu.io.deviceSelect === 2.U) { // deviceSelect = highest 3 bits of address, thus 0x4000_0000 is mapped to UART
cpu.io.memory_bundle <> uart.io.bundle
}.otherwise {
cpu.io.memory_bundle <> mem.io.bundle
}
cpu.io.memory_bundle <> mem.io.bundle
}
}

32
lab1/verilog/z710/Top_reset.v Normal file
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@@ -0,0 +1,32 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/12/01 16:32:40
// Design Name:
// Module Name: Top_reset
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Top_reset(
input reset
);
initial begin
reset = 1;
#25 reset = 0;
end
endmodule

46
lab1/verilog/z710/clock_control.v Normal file
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@@ -0,0 +1,46 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/11/29 15:52:55
// Design Name:
// Module Name: clock_control
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clock_control(
input clk_in,
input enable_clk,
output clk_out
);
// if clock is divided
localparam clk_div = 2; // clock is diveded by half of divisor
reg [3:0] cnt = 4'd0;
reg out = 1'b0;
always @(posedge clk_in) begin
cnt <= cnt + 4'd1;
if (cnt >= (clk_div - 1)) begin
out <= ~out;
cnt <= 0;
end
end
assign clk_out = out & enable_clk;
// original clock
// assign clk_out = clk_in & enable_clk;
endmodule

28
lab1/verilog/z710/pass_through.v Normal file
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@@ -0,0 +1,28 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/11/29 16:38:00
// Design Name:
// Module Name: pass_through
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pass_through(
input in,
output out
);
assign out = in;
endmodule

47
lab1/verilog/z710/top_test.v Normal file
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@@ -0,0 +1,47 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/12/01 15:46:54
// Design Name:
// Module Name: top_test
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top_test(
);
reg clock;
reg reset;
reg constant_zero = 1'b0;
wire io_led, io_tx;
localparam CLK_PERIOD = 10;
initial begin
clock = 1'b0;
forever #( CLK_PERIOD / 2 ) clock = ~clock;
end
initial begin
reset = 1; // need a down edge to init all components
#(CLK_PERIOD) reset = 0; // NOTE!!: must happen together with clock down edge!
end
Top mytop(clock, reset, io_tx, constant_zero, io_led );
endmodule

30
lab1/verilog/z710/uart_control.v Normal file
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@@ -0,0 +1,30 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/11/30 00:51:08
// Design Name:
// Module Name: uart_control
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module uart_control(
input enable_uart,
input tx_in,
output tx_out
);
assign tx_out = (enable_uart) ? tx_in : 1'h1;
endmodule

17
lab1/vivado/z710/generate_and_program.tcl Normal file
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@@ -0,0 +1,17 @@
# Copyright 2021 Howard Lau
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# Only tested on Vivado 2020.1 on Windows 10
source generate_bitstream.tcl
source program_device.tcl

57
lab1/vivado/z710/generate_bitstream.tcl Normal file
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@@ -0,0 +1,57 @@
# Copyright 2021 Howard Lau
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
source open_project.tcl
while 1 {
if { [catch {launch_runs synth_1 -jobs 4 } ] } {
regexp {ERROR: \[Common (\d+-\d+)]} $errorInfo -> code
if { [string equal $code "12-978"] } {
puts "Already generated and up-to-date"
break
} elseif { [string equal $code "17-69"] } {
puts "Out of date, reset runs"
reset_runs synth_1
continue
} else {
puts "UNKNOWN ERROR!!! $errorInfo"
exit
}
}
break
}
wait_on_run synth_1
while 1 {
if { [catch {launch_runs impl_1 -jobs 4 -to_step write_bitstream } ] } {
regexp {ERROR: \[Vivado (\d+-\d+)]} $errorInfo -> code
if { [string equal $code "12-978"] } {
puts "Already generated and up-to-date"
break
} elseif { [string equal $code "12-1088"] } {
puts "Out of date, reset runs"
reset_runs impl_1
continue
} else {
puts "UNKNOWN ERROR!!! $errorInfo"
exit
}
}
break
}
wait_on_run impl_1
file rename riscv-z710/riscv-z710.runs/impl_1/design_1_wrapper.bit riscv-z710/riscv-z710.runs/impl_1/Top.bit

139
lab1/vivado/z710/helloworld.c Normal file
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@@ -0,0 +1,139 @@
/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*
* helloworld.c: simple test application
*
* This application configures UART 16550 to baud rate 9600.
* PS7 UART (Zynq) is not initialized by this application, since
* bootrom/bsp configures it to baud rate 115200
*
* ------------------------------------------------
* | UART TYPE BAUD RATE |
* ------------------------------------------------
* uartns550 9600
* uartlite Configurable only in HW design
* ps7_uart 115200 (configured by bootrom/bsp)
*/
#include <stdio.h>
#include "platform.h"
#include "xil_printf.h"
//#include "xuartps_hw.h" // already include in xuartps.h
#include "xuartps.h"
#include "xparameters.h"
XUartPs uart_ps; // instance of the UART device
int main()
{
init_platform();
xil_printf("\nHello World\n\r");
// test on UART ps
int BUFFER_SIZE = 16; // do not set too much to overflow FIFO
char send_buffer[BUFFER_SIZE + 1];
char recv_buffer[BUFFER_SIZE + 1];
int status = 0;
XUartPs_Config *config;
for (int i = 0; i < BUFFER_SIZE; i++) send_buffer[i] = i % 256;
config = XUartPs_LookupConfig(XPAR_XUARTPS_0_BASEADDR); // CHANGE UART PORT HERE!!!
if (config == NULL) {
printf("Error in config lookup!\n");
return XST_FAILURE;
}
status = XUartPs_CfgInitialize(&uart_ps, config, config->BaseAddress);
if (status != XST_SUCCESS) {
printf("Error in cfg initialize!\n");
return XST_FAILURE;
}
XUartPs_SetBaudRate(&uart_ps, 115200);
/* Check hardware build. */
status = XUartPs_SelfTest(&uart_ps);
if (status != XST_SUCCESS) {
printf("Error in self test!\n");
return XST_FAILURE;
}
/* Configure UART mode */
int mode = XUartPs_ReadReg(uart_ps.Config.BaseAddress, XUARTPS_MR_OFFSET);
printf("original mode = 0x%x\n", mode);
XUartPs_WriteReg(uart_ps.Config.BaseAddress, XUARTPS_MR_OFFSET,
(XUARTPS_MR_STOPMODE_2_BIT | XUARTPS_MR_PARITY_NONE | XUARTPS_MR_CHARLEN_8_BIT));
XUartPs_SetOperMode(&uart_ps, XUARTPS_OPER_MODE_NORMAL);
int recv_cnt = 0;
while (1) {
int recved = XUartPs_Recv(&uart_ps, (u8*)(recv_buffer + 0), BUFFER_SIZE);
recv_cnt += recved;
recv_buffer[recv_cnt] = 0; // end
if (recv_cnt >= 1) {
// printf("%s", recv_buffer);
// printf("%i\n", recv_buffer[0]);
/* print string manually */
for (int j = 0; j < BUFFER_SIZE; j++) {
if (recv_buffer[j] != 0) {
printf("%c", recv_buffer[j]);
} else {
break;
}
}
recv_cnt = 0;
}
}
/* Restore to normal mode. */
XUartPs_SetOperMode(&uart_ps, XUARTPS_OPER_MODE_NORMAL);
cleanup_platform();
return 0;
}

33
lab1/vivado/z710/open_project.tcl Normal file
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@@ -0,0 +1,33 @@
# Copyright 2021 Howard Lau
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# Only tested on Vivado 2020.1 on Windows 10
# set variables
set project_dir riscv-z710
set project_name riscv-z710
set part xc7z010clg400-1
set sources {../../verilog/z710/Top.v ../../verilog/z710/clock_control.v ../../verilog/z710/pass_through.v ../../verilog/z710/Top_reset.v ../../verilog/z710/uart_control.v}
set test_sources {../../verilog/z710/test.v ../../verilog/z710/top_test.v}
# open the project. will create one if it doesn't exist
if {[file exist $project_dir]} {
# check that it's a directory
if {! [file isdirectory $project_dir]} {
puts "$project_dir exists, but it's a file"
}
open_project $project_dir/$project_name.xpr -part $part
} else {
source riscv-z710.tcl
}

24
lab1/vivado/z710/program_device.tcl Normal file
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@@ -0,0 +1,24 @@
# Copyright 2021 Howard Lau
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# Only tested on Vivado 2020.1 on Windows 10
open_hw_manager
connect_hw_server -allow_non_jtag
open_hw_target
current_hw_device [get_hw_devices xc7z010_1]
refresh_hw_server [current_hw_server]
open_hw_target [lindex [get_hw_targets] 0]
set_property PROGRAM.FILE {./riscv-z710/riscv-z710.runs/impl_1/Top.bit} [get_hw_devices xc7z010_1]
program_hw_devices [get_hw_devices xc7z010_1]
close_hw_target

BIN
lab1/vivado/z710/riscv-z710/design_1_wrapper.xsa Normal file
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Binary file not shown.

459
lab1/vivado/z710/riscv-z710/riscv-z710.srcs/sources_1/bd/design_1/design_1.bd Normal file
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@@ -0,0 +1,459 @@
{
"design": {
"design_info": {
"boundary_crc": "0xD2682A7282870375",
"device": "xc7z010clg400-1",
"name": "design_1",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "Hierarchical",
"tool_version": "2020.1",
"validated": "true"
},
"design_tree": {
"processing_system7_0": "",
"clock_control_0": "",
"xlconstant_0": "",
"Top_0": ""
},
"interface_ports": {
"DDR": {
"mode": "Master",
"vlnv": "xilinx.com:interface:ddrx_rtl:1.0",
"parameters": {
"CAN_DEBUG": {
"value": "false",
"value_src": "default"
},
"TIMEPERIOD_PS": {
"value": "1250",
"value_src": "default"
},
"MEMORY_TYPE": {
"value": "COMPONENTS",
"value_src": "default"
},
"DATA_WIDTH": {
"value": "8",
"value_src": "default"
},
"CS_ENABLED": {
"value": "true",
"value_src": "default"
},
"DATA_MASK_ENABLED": {
"value": "true",
"value_src": "default"
},
"SLOT": {
"value": "Single",
"value_src": "default"
},
"MEM_ADDR_MAP": {
"value": "ROW_COLUMN_BANK",
"value_src": "default"
},
"BURST_LENGTH": {
"value": "8",
"value_src": "default"
},
"AXI_ARBITRATION_SCHEME": {
"value": "TDM",
"value_src": "default"
},
"CAS_LATENCY": {
"value": "11",
"value_src": "default"
},
"CAS_WRITE_LATENCY": {
"value": "11",
"value_src": "default"
}
}
},
"FIXED_IO": {
"mode": "Master",
"vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0",
"parameters": {
"CAN_DEBUG": {
"value": "false",
"value_src": "default"
}
}
}
},
"ports": {
"io_clock": {
"type": "clk",
"direction": "I",
"parameters": {
"CLK_DOMAIN": {
"value": "design_1_clock",
"value_src": "default"
},
"FREQ_HZ": {
"value": "100000000"
},
"FREQ_TOLERANCE_HZ": {
"value": "0",
"value_src": "default"
},
"INSERT_VIP": {
"value": "0",
"value_src": "default"
},
"PHASE": {
"value": "0.000",
"value_src": "default"
}
}
},
"io_alive_led": {
"direction": "O"
},
"io_reset": {
"direction": "I",
"parameters": {
"POLARITY": {
"value": "",
"value_src": "weak"
}
}
},
"enable_clk": {
"type": "clk",
"direction": "I",
"parameters": {
"CLK_DOMAIN": {
"value": "design_1_enable_clk_0",
"value_src": "default"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "default"
},
"FREQ_TOLERANCE_HZ": {
"value": "0",
"value_src": "default"
},
"INSERT_VIP": {
"value": "0",
"value_src": "default"
},
"PHASE": {
"value": "0.000",
"value_src": "default"
}
}
}
},
"components": {
"processing_system7_0": {
"vlnv": "xilinx.com:ip:processing_system7:5.5",
"xci_name": "design_1_processing_system7_0_0",
"parameters": {
"PCW_ACT_APU_PERIPHERAL_FREQMHZ": {
"value": "666.666687"
},
"PCW_ACT_CAN_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_DCI_PERIPHERAL_FREQMHZ": {
"value": "10.158730"
},
"PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_ENET1_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": {
"value": "50.000000"
},
"PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": {
"value": "200.000000"
},
"PCW_ACT_QSPI_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_SDIO_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_SMC_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_SPI_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": {
"value": "200.000000"
},
"PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_ACT_UART_PERIPHERAL_FREQMHZ": {
"value": "100.000000"
},
"PCW_ACT_WDT_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_CLK0_FREQ": {
"value": "50000000"
},
"PCW_CLK1_FREQ": {
"value": "10000000"
},
"PCW_CLK2_FREQ": {
"value": "10000000"
},
"PCW_CLK3_FREQ": {
"value": "10000000"
},
"PCW_DDR_RAM_HIGHADDR": {
"value": "0x1FFFFFFF"
},
"PCW_EN_EMIO_UART0": {
"value": "1"
},
"PCW_EN_UART0": {
"value": "1"
},
"PCW_EN_UART1": {
"value": "1"
},
"PCW_FPGA_FCLK0_ENABLE": {
"value": "1"
},
"PCW_MIO_48_IOTYPE": {
"value": "LVCMOS 3.3V"
},
"PCW_MIO_48_PULLUP": {
"value": "enabled"
},
"PCW_MIO_48_SLEW": {
"value": "slow"
},
"PCW_MIO_49_IOTYPE": {
"value": "LVCMOS 3.3V"
},
"PCW_MIO_49_PULLUP": {
"value": "enabled"
},
"PCW_MIO_49_SLEW": {
"value": "slow"
},
"PCW_MIO_TREE_PERIPHERALS": {
"value": "unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 1#UART 1#unassigned#unassigned#unassigned#unassigned"
},
"PCW_MIO_TREE_SIGNALS": {
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},
"PCW_UART0_GRP_FULL_ENABLE": {
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},
"PCW_UART0_PERIPHERAL_ENABLE": {
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},
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"value": "EMIO"
},
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},
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"value": "1"
},
"PCW_UART1_UART1_IO": {
"value": "MIO 48 .. 49"
},
"PCW_UART_PERIPHERAL_FREQMHZ": {
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},
"PCW_UART_PERIPHERAL_VALID": {
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},
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"value": "533.333374"
},
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}
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"ref_type": "hdl",
"ref_name": "clock_control",
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},
"ports": {
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"direction": "I",
"parameters": {
"CLK_DOMAIN": {
"value": "design_1_clock",
"value_src": "default_prop"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "user_prop"
},
"PHASE": {
"value": "0.000",
"value_src": "default_prop"
}
}
},
"enable_clk": {
"type": "clk",
"direction": "I",
"parameters": {
"CLK_DOMAIN": {
"value": "design_1_enable_clk_0",
"value_src": "default_prop"
}
}
},
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"parameters": {
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"value": "",
"value_src": "weak"
},
"FREQ_HZ": {
"value": "",
"value_src": "weak"
},
"PHASE": {
"value": "",
"value_src": "weak"
}
}
}
}
},
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"vlnv": "xilinx.com:ip:xlconstant:1.1",
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},
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"vlnv": "xilinx.com:module_ref:Top:1.0",
"xci_name": "design_1_Top_0_0",
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"ref_type": "hdl",
"ref_name": "Top",
"boundary_crc": "0x0"
},
"ports": {
"clock": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_RESET": {
"value": "reset",
"value_src": "constant"
}
}
},
"reset": {
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"direction": "I"
},
"io_tx": {
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},
"io_rx": {
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},
"io_led": {
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}
}
}
},
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"interface_ports": [
"FIXED_IO",
"processing_system7_0/FIXED_IO"
]
},
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"DDR",
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]
}
},
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"ports": [
"Top_0/io_tx",
"processing_system7_0/UART0_RX"
]
},
"Top_0_io_led": {
"ports": [
"Top_0/io_led",
"io_alive_led"
]
},
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"ports": [
"io_reset",
"Top_0/reset"
]
},
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"ports": [
"io_clock",
"clock_control_0/clk_in"
]
},
"enable_clk_0_1": {
"ports": [
"enable_clk",
"clock_control_0/enable_clk"
]
},
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"ports": [
"clock_control_0/clk_out",
"Top_0/clock"
]
},
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"ports": [
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"Top_0/io_rx"
]
}
}
}
}

116
lab1/vivado/z710/riscv-z710/riscv-z710.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v Normal file
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//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
//Date : Tue Dec 12 00:14:50 2023
//Host : Tokisakix running 64-bit major release (build 9200)
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
enable_clk,
io_alive_led,
io_clock,
io_reset);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
input enable_clk;
output io_alive_led;
input io_clock;
input io_reset;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire enable_clk;
wire io_alive_led;
wire io_clock;
wire io_reset;
design_1 design_1_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.enable_clk(enable_clk),
.io_alive_led(io_alive_led),
.io_clock(io_clock),
.io_reset(io_reset));
endmodule

376
lab1/vivado/z710/riscv-z710/riscv-z710.xpr Normal file
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@@ -0,0 +1,376 @@
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<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="design_1_clock_control_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_clock_control_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_clock_control_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="design_1_Top_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_Top_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_Top_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>

24
lab1/vivado/z710/run_simulation.tcl Normal file
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# Copyright 2021 Howard Lau
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
source open_project.tcl
launch_simulation
restart
open_vcd
log_wave -recursive [get_object /test/top/cpu/*]
log_vcd [get_object /test/top/cpu/*]
run 1000ns
close_vcd
close_sim

216
lab1/vivado/z710/z710.xdc Normal file
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## This file is a general .xdc for the Zybo Z7 Rev. B
## It is compatible with the Zybo Z7-20 and Zybo Z7-10
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
#set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
#set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
##Clock signal
set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS33} [get_ports io_clock]
create_clock -period 20.000 -name sys_clk_pin -waveform {0.000 10.000} -add [get_ports io_clock]
# UART 1
#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS18 } [get_ports { io_tx }];
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { io_tx }];
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { reset }]; # bind to BTN1
#set_property IOSTANDARD LVCMOS18 [get_ports { io_tx }];
#set_property IOSTANDARD LVCMOS33 [get_ports { reset }];
##Switches
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports enable_clk]
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports enable_uart]
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=sw[2]
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=sw[3]
##Buttons
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports io_reset]; #IO_L12N_T1_MRCC_35 Sch=btn[0]
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { reset }]; #IO_L24N_T3_34 Sch=btn[1]
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { btn_tri_io[2] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2]
#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { btn_tri_io[3] }]; #IO_L7P_T1_34 Sch=btn[3]
##LEDs
set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports io_alive_led]
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=led[1]
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35 Sch=led[2]
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3]
##RGB LED 5 (Zybo Z7-20 only)
#set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS33 } [get_ports { led5_r }]; #IO_L18N_T2_13 Sch=led5_r
#set_property -dict { PACKAGE_PIN T5 IOSTANDARD LVCMOS33 } [get_ports { led5_g }]; #IO_L19P_T3_13 Sch=led5_g
#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { led5_b }]; #IO_L20P_T3_13 Sch=led5_b
##RGB LED 6
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led6_r }]; #IO_L18P_T2_34 Sch=led6_r
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { led6_g }]; #IO_L6N_T0_VREF_35 Sch=led6_g
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { led6_b }]; #IO_L8P_T1_AD10P_35 Sch=led6_b
##Audio Codec
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { ac_bclk }]; #IO_0_34 Sch=ac_bclk
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ac_mclk }]; #IO_L19N_T3_VREF_34 Sch=ac_mclk
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ac_muten }]; #IO_L23N_T3_34 Sch=ac_muten
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ac_pbdat }]; #IO_L20N_T3_34 Sch=ac_pbdat
#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { ac_pblrc }]; #IO_25_34 Sch=ac_pblrc
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ac_recdat }]; #IO_L19P_T3_34 Sch=ac_recdat
#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { ac_reclrc }]; #IO_L17P_T2_34 Sch=ac_reclrc
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { ac_scl }]; #IO_L13P_T2_MRCC_34 Sch=ac_scl
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ac_sda }]; #IO_L23P_T3_34 Sch=ac_sda
##Additional Ethernet signals
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { eth_int_pu_b }]; #IO_L6P_T0_35 Sch=eth_int_pu_b
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { eth_rst_b }]; #IO_L3P_T0_DQS_AD1P_35 Sch=eth_rst_b
##USB-OTG over-current detect pin
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { otg_oc }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=otg_oc
##Fan (Zybo Z7-20 only)
#set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { fan_fb_pu }]; #IO_L20N_T3_13 Sch=fan_fb_pu
##HDMI RX
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpd }]; #IO_L22N_T3_34 Sch=hdmi_rx_hpd
#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L22P_T3_34 Sch=hdmi_rx_scl
#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L17N_T2_34 Sch=hdmi_rx_sda
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p
#set_property -dict { PACKAGE_PIN W20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[0] }]; #IO_L16N_T2_34 Sch=hdmi_rx_n[0]
#set_property -dict { PACKAGE_PIN V20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[0] }]; #IO_L16P_T2_34 Sch=hdmi_rx_p[0]
#set_property -dict { PACKAGE_PIN U20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[1] }]; #IO_L15N_T2_DQS_34 Sch=hdmi_rx_n[1]
#set_property -dict { PACKAGE_PIN T20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[1] }]; #IO_L15P_T2_DQS_34 Sch=hdmi_rx_p[1]
#set_property -dict { PACKAGE_PIN P20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=hdmi_rx_n[2]
#set_property -dict { PACKAGE_PIN N20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=hdmi_rx_p[2]
##HDMI RX CEC (Zybo Z7-20 only)
#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L14N_T2_SRCC_13 Sch=hdmi_rx_cec
##HDMI TX
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpd }]; #IO_L5P_T0_AD9P_35 Sch=hdmi_tx_hpd
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L16P_T2_35 Sch=hdmi_tx_scl
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L16N_T2_35 Sch=hdmi_tx_sda
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_n }]; #IO_L13N_T2_MRCC_35 Sch=hdmi_tx_clk_n
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_p }]; #IO_L13P_T2_MRCC_35 Sch=hdmi_tx_clk_p
#set_property -dict { PACKAGE_PIN D20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[0] }]; #IO_L4N_T0_35 Sch=hdmi_tx_n[0]
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[0] }]; #IO_L4P_T0_35 Sch=hdmi_tx_p[0]
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=hdmi_tx_n[1]
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=hdmi_tx_p[1]
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=hdmi_tx_n[2]
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=hdmi_tx_p[2]
##HDMI TX CEC
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L5N_T0_AD9N_35 Sch=hdmi_tx_cec
##Pmod Header JA (XADC)
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N
#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N
##Pmod Header JB (Zybo Z7-20 only)
#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L15P_T2_DQS_13 Sch=jb_p[1]
#set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L15N_T2_DQS_13 Sch=jb_n[1]
#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L11P_T1_SRCC_13 Sch=jb_p[2]
#set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L11N_T1_SRCC_13 Sch=jb_n[2]
#set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L13P_T2_MRCC_13 Sch=jb_p[3]
#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L13N_T2_MRCC_13 Sch=jb_n[3]
#set_property -dict { PACKAGE_PIN V6 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L22P_T3_13 Sch=jb_p[4]
#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L22N_T3_13 Sch=jb_n[4]
##Pmod Header JC
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L10P_T1_34 Sch=jc_p[1]
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L10N_T1_34 Sch=jc_n[1]
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L1P_T0_34 Sch=jc_p[2]
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L1N_T0_34 Sch=jc_n[2]
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L8P_T1_34 Sch=jc_p[3]
#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L8N_T1_34 Sch=jc_n[3]
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L2P_T0_34 Sch=jc_p[4]
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L2N_T0_34 Sch=jc_n[4]
##Pmod Header JD
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L5P_T0_34 Sch=jd_p[1]
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L5N_T0_34 Sch=jd_n[1]
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L6P_T0_34 Sch=jd_p[2]
#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L6N_T0_VREF_34 Sch=jd_n[2]
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L11P_T1_SRCC_34 Sch=jd_p[3]
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3]
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4]
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4]
##Pmod Header JE
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=je[1]
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=je[2]
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=je[3]
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=je[4]
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=je[7]
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=je[8]
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=je[9]
#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=je[10]
##Pcam MIPI CSI-2 Connector
## This configuration expects the sensor to use 672Mbps/lane = 336 MHz HS_Clk
#create_clock -period 2.976 -name dphy_hs_clock_clk_p -waveform {0.000 1.488} [get_ports dphy_hs_clock_clk_p]
#set_property INTERNAL_VREF 0.6 [get_iobanks 35]
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD HSUL_12 } [get_ports { dphy_clk_lp_n }]; #IO_L10N_T1_AD11N_35 Sch=lp_clk_n
#set_property -dict { PACKAGE_PIN H20 IOSTANDARD HSUL_12 } [get_ports { dphy_clk_lp_p }]; #IO_L17N_T2_AD5N_35 Sch=lp_clk_p
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_n[0] }]; #IO_L8N_T1_AD10N_35 Sch=lp_lane_n[0]
#set_property -dict { PACKAGE_PIN L19 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_p[0] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=lp_lane_p[0]
#set_property -dict { PACKAGE_PIN L20 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_n[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=lp_lane_n[1]
#set_property -dict { PACKAGE_PIN J20 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_p[1] }]; #IO_L17P_T2_AD5P_35 Sch=lp_lane_p[1]
#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVDS_25 } [get_ports { dphy_hs_clock_clk_n }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=mipi_clk_n
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVDS_25 } [get_ports { dphy_hs_clock_clk_p }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=mipi_clk_p
#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_n[0] }]; #IO_L7N_T1_AD2N_35 Sch=mipi_lane_n[0]
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_p[0] }]; #IO_L7P_T1_AD2P_35 Sch=mipi_lane_p[0]
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_n[1] }]; #IO_L11N_T1_SRCC_35 Sch=mipi_lane_n[1]
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_p[1] }]; #IO_L11P_T1_SRCC_35 Sch=mipi_lane_p[1]
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { cam_clk }]; #IO_L18P_T2_AD13P_35 Sch=cam_clk
#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 PULLUP true} [get_ports { cam_gpio }]; #IO_L18N_T2_AD13N_35 Sch=cam_gpio
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { cam_scl }]; #IO_L15N_T2_DQS_AD12N_35 Sch=cam_scl
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { cam_sda }]; #IO_L15P_T2_DQS_AD12P_35 Sch=cam_sda
##Unloaded Crypto Chip SWI (for future use)
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L13N_T2_MRCC_34 Sch=crypto_sda
##Unconnected Pins (Zybo Z7-20 only)
#set_property PACKAGE_PIN T9 [get_ports {netic19_t9}]; #IO_L12P_T1_MRCC_13
#set_property PACKAGE_PIN U10 [get_ports {netic19_u10}]; #IO_L12N_T1_MRCC_13
#set_property PACKAGE_PIN U5 [get_ports {netic19_u5}]; #IO_L19N_T3_VREF_13
#set_property PACKAGE_PIN U8 [get_ports {netic19_u8}]; #IO_L17N_T2_13
#set_property PACKAGE_PIN U9 [get_ports {netic19_u9}]; #IO_L17P_T2_13
#set_property PACKAGE_PIN V10 [get_ports {netic19_v10}]; #IO_L21N_T3_DQS_13
#set_property PACKAGE_PIN V11 [get_ports {netic19_v11}]; #IO_L21P_T3_DQS_13
#set_property PACKAGE_PIN V5 [get_ports {netic19_v5}]; #IO_L6N_T0_VREF_13
#set_property PACKAGE_PIN W10 [get_ports {netic19_w10}]; #IO_L16P_T2_13
#set_property PACKAGE_PIN W11 [get_ports {netic19_w11}]; #IO_L18P_T2_13
#set_property PACKAGE_PIN W9 [get_ports {netic19_w9}]; #IO_L16N_T2_13
#set_property PACKAGE_PIN Y9 [get_ports {netic19_y9}]; #IO_L14P_T2_SRCC_13

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lab2/verilog/z710/Top_reset.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/12/01 16:32:40
// Design Name:
// Module Name: Top_reset
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Top_reset(
input reset
);
initial begin
reset = 1;
#25 reset = 0;
end
endmodule

46
lab2/verilog/z710/clock_control.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/11/29 15:52:55
// Design Name:
// Module Name: clock_control
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clock_control(
input clk_in,
input enable_clk,
output clk_out
);
// if clock is divided
localparam clk_div = 2; // clock is diveded by half of divisor
reg [3:0] cnt = 4'd0;
reg out = 1'b0;
always @(posedge clk_in) begin
cnt <= cnt + 4'd1;
if (cnt >= (clk_div - 1)) begin
out <= ~out;
cnt <= 0;
end
end
assign clk_out = out & enable_clk;
// original clock
// assign clk_out = clk_in & enable_clk;
endmodule

28
lab2/verilog/z710/pass_through.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/11/29 16:38:00
// Design Name:
// Module Name: pass_through
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pass_through(
input in,
output out
);
assign out = in;
endmodule

47
lab2/verilog/z710/top_test.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/12/01 15:46:54
// Design Name:
// Module Name: top_test
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top_test(
);
reg clock;
reg reset;
reg constant_zero = 1'b0;
wire io_led, io_tx;
localparam CLK_PERIOD = 10;
initial begin
clock = 1'b0;
forever #( CLK_PERIOD / 2 ) clock = ~clock;
end
initial begin
reset = 1; // need a down edge to init all components
#(CLK_PERIOD) reset = 0; // NOTE!!: must happen together with clock down edge!
end
Top mytop(clock, reset, io_tx, constant_zero, io_led );
endmodule

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lab2/verilog/z710/uart_control.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/11/30 00:51:08
// Design Name:
// Module Name: uart_control
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module uart_control(
input enable_uart,
input tx_in,
output tx_out
);
assign tx_out = (enable_uart) ? tx_in : 1'h1;
endmodule

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lab2/verilog/z710/z710/Top.scala
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package board.z710
import chisel3._
import chisel3.stage.ChiselStage
import chisel3.util._
import chisel3.{ChiselEnum, _}
// import circt.stage.ChiselStage
import chisel3.stage.ChiselGeneratorAnnotation
import bus._
import peripheral._
import riscv._
import riscv.Parameters
import riscv.core.CPU
import javax.print.SimpleDoc
object BootStates extends ChiselEnum {
val Init, Loading, BusWait, Finished = Value
}
class Top(binaryFilename: String ="say_goodbye.asmbin") extends Module {
// val binaryFilename = "say_goodbye.asmbin"
val io = IO(new Bundle {
// val switch = Input(UInt(16.W))
// val rgb = Output(UInt(12.W))
val led = Output(Bool())
val tx = Output(Bool())
val rx = Input(Bool())
})
val boot_state = RegInit(BootStates.Init)
val uart = Module(new Uart(125_000_000, 115200)) // this freq is consistent with Zynq 7 PS UART module
io.tx := uart.io.txd
uart.io.rxd := io.rx
val cpu = Module(new CPU)
val mem = Module(new Memory(Parameters.MemorySizeInWords))
val timer = Module(new Timer)
val dummy = Module(new DummySlave)
val bus_arbiter = Module(new BusArbiter)
val bus_switch = Module(new BusSwitch)
val instruction_rom = Module(new InstructionROM(binaryFilename))
val rom_loader = Module(new ROMLoader(instruction_rom.capacity))
bus_arbiter.io.bus_request(0) := true.B
bus_switch.io.master <> cpu.io.axi4_channels
bus_switch.io.address := cpu.io.bus_address
for (i <- 0 until Parameters.SlaveDeviceCount) {
bus_switch.io.slaves(i) <> dummy.io.channels
}
rom_loader.io.load_address := Parameters.EntryAddress
rom_loader.io.load_start := false.B
rom_loader.io.rom_data := instruction_rom.io.data
instruction_rom.io.address := rom_loader.io.rom_address
cpu.io.stall_flag_bus := true.B
cpu.io.instruction_valid := false.B
bus_switch.io.slaves(0) <> mem.io.channels
rom_loader.io.channels <> dummy.io.channels
switch(boot_state) {
is(BootStates.Init) {
rom_loader.io.load_start := true.B
boot_state := BootStates.Loading
rom_loader.io.channels <> mem.io.channels
}
is(BootStates.Loading) {
rom_loader.io.load_start := false.B
rom_loader.io.channels <> mem.io.channels
when(rom_loader.io.load_finished) {
boot_state := BootStates.Finished
}
}
is(BootStates.Finished) {
cpu.io.stall_flag_bus := false.B
cpu.io.instruction_valid := true.B
}
}
bus_switch.io.slaves(2) <> uart.io.channels
bus_switch.io.slaves(4) <> timer.io.channels
cpu.io.interrupt_flag := Cat(uart.io.signal_interrupt, timer.io.signal_interrupt)
cpu.io.debug_read_address := 0.U
mem.io.debug_read_address := 0.U
val clock_freq = 100_000_000.U
val led_count = RegInit(0.U(32.W))
when (led_count >= clock_freq) { // the led blinks every second, clock freq is 100M
led_count := 0.U
}.otherwise {
led_count := led_count + 1.U
}
io.led := (led_count >= (clock_freq >> 1))
}
object VerilogGenerator extends App {
(new ChiselStage).execute(
Array("-X", "verilog", "--target-dir", "verilog/z710"),
Seq(ChiselGeneratorAnnotation(() => new Top())) // default bin file
)
}