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31 lines
622 B
Verilog
31 lines
622 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2023/11/30 00:51:08
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// Design Name:
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// Module Name: uart_control
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module uart_control(
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input enable_uart,
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input tx_in,
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output tx_out
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);
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assign tx_out = (enable_uart) ? tx_in : 1'h1;
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endmodule
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