finished lab1

lab2/verilog/z710/Top_reset.v

@@ -0,0 +1,32 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2023/12/01 16:32:40
+// Design Name: 
+// Module Name: Top_reset
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Top_reset(
+    input reset
+    );
+    initial begin
+        reset = 1;
+        #25 reset = 0;
+    end
+    
+    
+endmodule

lab2/verilog/z710/clock_control.v

@@ -0,0 +1,46 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2023/11/29 15:52:55
+// Design Name: 
+// Module Name: clock_control
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module clock_control(
+    input clk_in,
+    input enable_clk,
+    output clk_out
+    );
+    
+    // if clock is divided
+    localparam clk_div = 2; // clock is diveded by half of divisor
+    reg [3:0] cnt = 4'd0;
+    reg out = 1'b0;
+    always @(posedge clk_in) begin 
+        cnt <= cnt + 4'd1;
+        if (cnt >= (clk_div - 1)) begin
+            out <= ~out;
+            cnt <= 0;
+        end
+    end
+    assign clk_out = out & enable_clk;
+    
+    
+    // original clock
+//    assign clk_out = clk_in & enable_clk;
+    
+endmodule

lab2/verilog/z710/pass_through.v

@@ -0,0 +1,28 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2023/11/29 16:38:00
+// Design Name: 
+// Module Name: pass_through
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module pass_through(
+    input in,
+    output out
+    );
+    assign out = in;
+endmodule

lab2/verilog/z710/top_test.v

@@ -0,0 +1,47 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2023/12/01 15:46:54
+// Design Name: 
+// Module Name: top_test
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module top_test(
+
+    );
+    
+    reg clock;
+    reg reset;
+    reg constant_zero = 1'b0;
+    
+    wire io_led, io_tx;
+    
+    localparam CLK_PERIOD = 10;
+    initial begin
+        clock = 1'b0;
+        forever #( CLK_PERIOD / 2 ) clock = ~clock;
+    end
+    
+    
+    initial begin
+        reset = 1;  // need a down edge to init all components
+        #(CLK_PERIOD)  reset = 0;  // NOTE!!: must happen together with clock down edge!
+    end
+    
+    Top mytop(clock, reset, io_tx, constant_zero, io_led );
+    
+endmodule

lab2/verilog/z710/uart_control.v

@@ -0,0 +1,30 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2023/11/30 00:51:08
+// Design Name: 
+// Module Name: uart_control
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module uart_control(
+    input enable_uart,
+    input tx_in,
+    output tx_out
+    );
+    assign tx_out = (enable_uart) ? tx_in : 1'h1;
+
+endmodule

lab2/verilog/z710/z710/Top.scala

@@ -1,119 +0,0 @@
-package board.z710
-
-
-import chisel3._
-import chisel3.stage.ChiselStage
-import chisel3.util._
-import chisel3.{ChiselEnum, _}
-
-// import circt.stage.ChiselStage
-import chisel3.stage.ChiselGeneratorAnnotation
-
-import bus._
-import peripheral._
-import riscv._
-import riscv.Parameters
-import riscv.core.CPU
-import javax.print.SimpleDoc
-
-object BootStates extends ChiselEnum {
-  val Init, Loading, BusWait, Finished = Value
-}
-
-
-class Top(binaryFilename: String ="say_goodbye.asmbin") extends Module {
-  // val binaryFilename = "say_goodbye.asmbin"
-  val io = IO(new Bundle {
-    // val switch = Input(UInt(16.W))
-
-    // val rgb = Output(UInt(12.W))
-
-    val led = Output(Bool())
-    val tx = Output(Bool())
-    val rx = Input(Bool())
-
-
-  })
-  val boot_state = RegInit(BootStates.Init)
-
-  val uart = Module(new Uart(125_000_000, 115200))  // this freq is consistent with Zynq 7 PS UART module
-  io.tx := uart.io.txd
-  uart.io.rxd := io.rx
-
-  val cpu = Module(new CPU)
-  val mem = Module(new Memory(Parameters.MemorySizeInWords))
-  val timer = Module(new Timer)
-  val dummy = Module(new DummySlave)
-  val bus_arbiter = Module(new BusArbiter)
-  val bus_switch = Module(new BusSwitch)
-
-  val instruction_rom = Module(new InstructionROM(binaryFilename))
-  val rom_loader = Module(new ROMLoader(instruction_rom.capacity))
-
-  bus_arbiter.io.bus_request(0) := true.B
-
-  bus_switch.io.master <> cpu.io.axi4_channels
-  bus_switch.io.address := cpu.io.bus_address
-  for (i <- 0 until Parameters.SlaveDeviceCount) {
-    bus_switch.io.slaves(i) <> dummy.io.channels
-  }
-  rom_loader.io.load_address := Parameters.EntryAddress
-  rom_loader.io.load_start := false.B
-  rom_loader.io.rom_data := instruction_rom.io.data
-  instruction_rom.io.address := rom_loader.io.rom_address
-  cpu.io.stall_flag_bus := true.B
-  cpu.io.instruction_valid := false.B
-  bus_switch.io.slaves(0) <> mem.io.channels
-  rom_loader.io.channels <> dummy.io.channels
-  switch(boot_state) {
-    is(BootStates.Init) {
-      rom_loader.io.load_start := true.B
-      boot_state := BootStates.Loading
-      rom_loader.io.channels <> mem.io.channels
-    }
-    is(BootStates.Loading) {
-      rom_loader.io.load_start := false.B
-      rom_loader.io.channels <> mem.io.channels
-      when(rom_loader.io.load_finished) {
-        boot_state := BootStates.Finished
-      }
-    }
-    is(BootStates.Finished) {
-      cpu.io.stall_flag_bus := false.B
-      cpu.io.instruction_valid := true.B
-    }
-  }
-
-  bus_switch.io.slaves(2) <> uart.io.channels
-  bus_switch.io.slaves(4) <> timer.io.channels
-
-  cpu.io.interrupt_flag := Cat(uart.io.signal_interrupt, timer.io.signal_interrupt)
-
-  cpu.io.debug_read_address := 0.U
-  mem.io.debug_read_address := 0.U
-
-
-  
-  val clock_freq = 100_000_000.U
-
-  val led_count = RegInit(0.U(32.W))
-  when (led_count >= clock_freq) { // the led blinks every second, clock freq is 100M
-    led_count := 0.U
-  }.otherwise {
-    led_count := led_count + 1.U
-  }
-
-  io.led := (led_count >= (clock_freq >> 1))
-
-
-}
-
-
-
-object VerilogGenerator extends App {
-    (new ChiselStage).execute(
-        Array("-X", "verilog", "--target-dir", "verilog/z710"), 
-        Seq(ChiselGeneratorAnnotation(() => new Top())) // default bin file
-    )
-    
-}