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lab1/实验报告/1.md
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lab1/实验报告/1.md
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好～我把(3)和(4)都整理成**流水线时序表**（5 级：IF/ID/EX/M/WB），空白表示该拍无操作。
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# (3) 指令：
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I1: LOAD R1,[a]
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I2: LOAD R2,[b]
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I3: ADD R1,R2 （结果写回 R2）
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I4: STORE R2,[x]
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### 时序表（到 14 拍）
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| 指令 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 |
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| -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- |
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| I1 | IF | ID | EX | M | WB | | | | | | | | | |
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| I2 | | IF | ID | EX | M | WB | | | | | | | | |
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| I3 | | | IF | ID | ID | ID | ID | EX | M | WB | | | | |
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| I4 | | | | | | | IF | ID | ID | ID | ID | EX | M | |
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> 说明：I3 在 ID 等待到 R1@5、R2@6 写回后才在第 7 拍完成读寄存器；I4 受 I3 占据 ID 反压，IF 被阻塞到第 7 拍开始；又因需等 R2@10 写回，ID 等到第 11 拍才读到新 R2，随后 EX→M 结束。
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---
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# (4) 指令（提示给定）：
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I1: LOAD R1,[x]
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I2: LOAD R2,[a]
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I3: SHL R1 （x*2）
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I4: ADD R1,R2 （写回 R2）
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I5: STORE R2,[x]
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### 时序表（到 16 拍）
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| 指令 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 |
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| -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- |
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| I1 | IF | ID | EX | M | WB | | | | | | | | | | | |
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| I2 | | IF | ID | EX | M | WB | | | | | | | | | | |
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| I3 | | | IF | ID | ID | ID | EX | M | WB | | | | | | | |
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| I4 | | | | | | | IF | ID | ID | ID | EX | M | WB | | | |
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| I5 | | | | | | | | | | IF | ID | ID | ID | ID | EX | M |
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* 关键等待：
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* I3 需等 R1@5 写回，故在 ID 等到第 6 拍读寄存器→7 EX→9 WB；
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* I4 需等 I3 的 R1 在第 9 拍写回，故在第 10 拍读寄存器→11 EX→13 WB；
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* I5 需等 R2 在第 13 拍写回，于第 14 拍读寄存器→15 EX→16 M（STORE 在 M 完成写内存）。
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如果你想把这两张表导成可打印的 Word/Excel，我也可以直接帮你生成文件。
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lab1/实验报告/b42.png
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lab1/实验报告/report.fdb_latexmk
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lab1/实验报告/report.fdb_latexmk
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# Fdb version 4
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"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/cjk/UTF8/UTF8.bdg" 1670582841 3857 eb1bacae4debef49a730cd935a17d208 ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/cjk/UTF8/UTF8.chr" 1670582841 8601 48822bfc9ff5adbcc1c7f832dd920f29 ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/cjk/UTF8/UTF8.enc" 1670582841 6111 5a99517ba8cc0c0905d3c54d7c7bcc48 ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/cjk/mule/MULEenc.sty" 1670582841 12177 48c95ebf85a580326918e5eb490b477b ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/cjkpunct/CJKpunct.spa" 1463194434 7 7979211695692235f48c7d3ba95863ea ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/cjkpunct/CJKpunct.sty" 1463224796 17985 35c6beb757001c750ed764f3ac4ef0d6 ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/ctex/config/ctex-name-utf8.cfg" 1657818410 1770 50e40a993c4c5ea72af9155aff7e605c ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/ctex/config/ctex.cfg" 1657818410 1230 140911b70e325208170dc573931e772d ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/ctex/config/ctexbackend.cfg" 1657818410 1904 e0018b8e661c6b3e37f6e4a53f472d74 ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/ctex/config/ctexopts.cfg" 1657818410 1291 feb9a19ff907013e8b3014895a284585 ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/ctex/ctexart.cls" 1657818410 55219 69f0e9646f7b8e2f2ed4c5f3eef59f5c ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/ctex/ctexhook.sty" 1657818410 6505 33157acfddefdd8fd513e2308e07a435 ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/ctex/ctexpatch.sty" 1657818410 8448 194e901f66d106236c72ef098b091d00 ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/ctex/ctexspa.def" 1657818410 10881 81f1c81c512ebcc46745af438dfa73d9 ""
|
||||
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|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/ctex/fd/c70rm.fd" 1657818410 1820 94b600cf0e8675b72e2f47cdec13db0a ""
|
||||
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|
||||
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|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/enumitem/enumitem.sty" 1738917170 52272 63d293bc0d496619edb57585740861a2 ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/epstopdf-pkg/epstopdf-base.sty" 1623003186 13886 d1306dcf79a944f6988e688c1785f9ce ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/etoolbox/etoolbox.sty" 1739279216 46850 d87daedc2abdc653769a6f1067849fe0 ""
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||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/fancyhdr/fancyhdr.sty" 1740138435 31715 19e60610b63819fe670dfa1cd84a4e94 ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/geometry/geometry.cfg" 1578053545 1104 d237cad3f14be9fd91fe1f904d051a01 ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/geometry/geometry.sty" 1578053545 42759 e63af52ccddba7489ac0e17d6a3344bd ""
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||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/graphics-cfg/color.cfg" 1465894292 1213 620bba36b25224fa9b7e1ccb4ecb76fd ""
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||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/graphics-cfg/graphics.cfg" 1465894292 1224 978390e9c2234eab29404bc21b268d1e ""
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||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/graphics-def/pdftex.def" 1713599642 19440 9da9dcbb27470349a580fca7372d454b ""
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||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/graphics/color.sty" 1749322634 7245 a7e8457a46cda4920df85d975267efb4 ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/graphics/graphics.sty" 1749322634 18363 69bb4f5538964bfea50d1e6d89cbe69f ""
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||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/graphics/graphicx.sty" 1749322634 8118 43b99e52946c33a23f5f43b52d5cc5ec ""
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||||
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||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/graphics/mathcolor.ltx" 1749322634 2885 9c645d672ae17285bba324998918efd8 ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/graphics/trig.sty" 1749322634 4023 e66acf578d6b564c4670fb57ff336a7a ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/hycolor/hycolor.sty" 1580380792 18571 5a6205e2f490b14bdc73fa03b48f19d6 ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/hyperref/hpdftex.def" 1752319040 48140 5e8a3a4aa88ae09b90d524926a067201 ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/hyperref/hyperref.sty" 1752319040 223112 93e90b2b1b3ef21af41adaf029922dd3 ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/hyperref/nameref.sty" 1752319040 11027 0fe7ce2c6b5291fd809c2de7bbdca37e ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/hyperref/pd1enc.def" 1752319041 14249 e14b403fb70abdf1f6742598a63b0e2a ""
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||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/hyperref/puenc.def" 1752319041 117118 e2f5f7983a43f89e2ffcd709fc59d37c ""
|
||||
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|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/kvsetkeys/kvsetkeys.sty" 1665066333 13815 760b0c02f691ea230f5359c4e1de23a7 ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/l3backend/l3backend-pdftex.def" 1751005717 30351 a2b09edc6c93a742566b222c33d0278e ""
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||||
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||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/listings/listings.cfg" 1741168183 1865 301ae3c26fb8c0243307b619a6aa2dd3 ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/listings/listings.sty" 1741168182 81640 997090b6c021dc4af9ee00a97b85c5b4 ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/listings/lstlang1.sty" 1741168183 206518 4eb59a801ad842a713fa168c34227290 ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/listings/lstmisc.sty" 1741168182 77051 be68720e5402397a830abb9eed5a2cb4 ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/listings/lstpatch.sty" 1741168182 353 9024412f43e92cd5b21fe9ded82d0610 ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/refcount/refcount.sty" 1576433952 9878 9e94e8fa600d95f9c7731bb21dfb67a4 ""
|
||||
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|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/url/url.sty" 1388490452 12796 8edb7d69a20b857904dd0ea757c14ec9 ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/xcolor/xcolor.sty" 1729265222 55384 b454dec21c2d9f45ec0b793f0995b992 ""
|
||||
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||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/zhnumber/zhnumber-utf8.cfg" 1657817710 5700 603e2f09dad175efabc8594730623a0b ""
|
||||
"C:/Users/26586/AppData/Local/Programs/MiKTeX/tex/latex/zhnumber/zhnumber.sty" 1657817710 38160 aafa8d740e4f21b62a4acd4835e54359 ""
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||||
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||||
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||||
"C:/WINDOWS/Fonts/simhei.ttf" 1711630440 9755440 186b27ff118e04e580eaad8ae78f2420 ""
|
||||
"C:/WINDOWS/Fonts/simsun.ttc" 1753780693.16377 18070492 1615784d420bffd42e8addd1714f7c6a ""
|
||||
"b1.png" 1760016100.1311 133511 c4d7015bc0ffd59062cc43dabb38dee0 ""
|
||||
"b2.png" 1760016308.25508 160026 1cb39dce57540fc47ade8fa5d67427df ""
|
||||
"b3.png" 1760017262.67962 146829 91f9628ae583b81275dd0f7fb2700bc5 ""
|
||||
"b41.png" 1762870341.84854 38634 6ab518edbcd4e070e4e9c7debc494b0e ""
|
||||
"e:/jizu/2025-fall-yatcpu-repo/lab1/实验报告/report.tex" 1762875590.50658 19013 53a6fb21429e9aa6b3f6f5a066409f4b ""
|
||||
"report.aux" 1762875597.9566 5906 e3292a3e7e0121d304f285d918f08e54 "pdflatex"
|
||||
"report.out" 1762875597.9586 2657 419e0e626d89895c61f1e0057f559761 "pdflatex"
|
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(generated)
|
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"report.aux"
|
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"report.log"
|
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"report.out"
|
||||
"report.pdf"
|
||||
(rewritten before read)
|
||||
602
lab1/实验报告/report.fls
Normal file
602
lab1/实验报告/report.fls
Normal file
@@ -0,0 +1,602 @@
|
||||
PWD E:\jizu\2025-fall-yatcpu-repo\lab1\实验报告
|
||||
INPUT C:\Users\26586\AppData\Local\MiKTeX\miktex\data\le\pdftex\pdflatex.fmt
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INPUT e:\jizu\2025-fall-yatcpu-repo\lab1\实验报告\report.tex
|
||||
OUTPUT report.log
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\ctex\ctexart.cls
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\ctex\ctexart.cls
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\ctex\config\ctexbackend.cfg
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\ctex\config\ctexbackend.cfg
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\ctex\config\ctexbackend.cfg
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\l3kernel\expl3.sty
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\l3kernel\expl3.sty
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\l3backend\l3backend-pdftex.def
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\l3backend\l3backend-pdftex.def
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\ctex\engine\ctex-engine-pdftex.def
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\ctex\ctexhook.sty
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\ctex\ctexhook.sty
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\fonts\tfm\public\cm\cmr10.tfm
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\ctex\ctexpatch.sty
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\ctex\ctexpatch.sty
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\base\fix-cm.sty
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\base\fix-cm.sty
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\base\ts1enc.def
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\fonts\tfm\public\cm\cmr10.tfm
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\ctex\config\ctexopts.cfg
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\ctex\config\ctexopts.cfg
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\base\article.cls
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\base\article.cls
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\base\size12.clo
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\base\size12.clo
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\base\size12.clo
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\fonts\tfm\public\cm\cmr12.tfm
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\ctex\engine\ctex-engine-pdftex.def
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\cjk\CJKutf8.sty
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\cjk\CJKutf8.sty
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\generic\iftex\ifpdf.sty
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\generic\iftex\ifpdf.sty
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\generic\iftex\iftex.sty
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\generic\iftex\iftex.sty
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\base\inputenc.sty
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\base\inputenc.sty
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\cjk\CJK.sty
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\cjk\CJK.sty
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\cjk\mule\MULEenc.sty
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\cjk\mule\MULEenc.sty
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\cjk\CJK.enc
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\base\fontenc.sty
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\base\fontenc.sty
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\cjkpunct\CJKpunct.sty
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\cjkpunct\CJKpunct.sty
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\cjkpunct\CJKpunct.spa
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\cjkpunct\CJKpunct.spa
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\cjkpunct\CJKpunct.spa
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\cjk\CJKspace.sty
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\cjk\CJKspace.sty
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\fonts\tfm\public\cm\cmr10.tfm
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\cjk\UTF8\UTF8.bdg
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\cjk\UTF8\UTF8.bdg
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\ctex\ctexspa.def
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\ctex\ctexspa.def
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\hyperref\hyperref.sty
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\zhnumber\zhnumber.sty
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\zhnumber\zhnumber.sty
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\zhnumber\zhnumber-utf8.cfg
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\zhnumber\zhnumber-utf8.cfg
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\ctex\scheme\ctex-scheme-chinese-article.def
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\ctex\scheme\ctex-scheme-chinese-article.def
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\ctex\config\ctex-name-utf8.cfg
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\ctex\config\ctex-name-utf8.cfg
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\ctex\fontset\ctex-fontset-windows.def
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\ctex\fontset\ctex-fontset-windows.def
|
||||
INPUT C:\WINDOWS\Fonts\msyh.ttc
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\ctex\config\ctex.cfg
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\ctex\config\ctex.cfg
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\geometry\geometry.sty
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\geometry\geometry.sty
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\graphics\keyval.sty
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\graphics\keyval.sty
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\generic\iftex\ifvtex.sty
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\generic\iftex\ifvtex.sty
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\geometry\geometry.cfg
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\geometry\geometry.cfg
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\geometry\geometry.cfg
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\graphics\graphicx.sty
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\graphics\graphicx.sty
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\graphics\graphics.sty
|
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INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\tex\latex\graphics\graphics.sty
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
INPUT report.aux
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
INPUT C:\WINDOWS\Fonts\simfang.ttf
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\Users\26586\AppData\Local\MiKTeX\fonts\pk\ljfour\jknappen\ec\dpi600\tcrm1200.pk
|
||||
INPUT C:\Users\26586\AppData\Local\MiKTeX\fonts\pk\ljfour\jknappen\ec\dpi600\tcrm1200.pk
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simhei.ttf
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\WINDOWS\Fonts\simsun.ttc
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\fonts\type1\public\amsfonts\cm\cmbx12.pfb
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\fonts\type1\public\amsfonts\cm\cmbx12.pfb
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\fonts\type1\public\amsfonts\cm\cmitt10.pfb
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\fonts\type1\public\amsfonts\cm\cmitt10.pfb
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\fonts\type1\public\amsfonts\cm\cmmi10.pfb
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\fonts\type1\public\amsfonts\cm\cmmi10.pfb
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\fonts\type1\public\amsfonts\cm\cmmi8.pfb
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\fonts\type1\public\amsfonts\cm\cmmi8.pfb
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\fonts\type1\public\amsfonts\cm\cmr10.pfb
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\fonts\type1\public\amsfonts\cm\cmr10.pfb
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\fonts\type1\public\amsfonts\cm\cmr12.pfb
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\fonts\type1\public\amsfonts\cm\cmr12.pfb
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\fonts\type1\public\amsfonts\cm\cmtt10.pfb
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\fonts\type1\public\amsfonts\cm\cmtt10.pfb
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\fonts\type1\public\amsfonts\cm\cmtt12.pfb
|
||||
INPUT C:\Users\26586\AppData\Local\Programs\MiKTeX\fonts\type1\public\amsfonts\cm\cmtt12.pfb
|
||||
BIN
lab1/朱梓涵24325356.rar
Normal file
BIN
lab1/朱梓涵24325356.rar
Normal file
Binary file not shown.
70
lab1/朱梓涵24325356/core/ALU.scala
Normal file
70
lab1/朱梓涵24325356/core/ALU.scala
Normal file
@@ -0,0 +1,70 @@
|
||||
// Copyright 2021 Howard Lau
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
package riscv.core
|
||||
|
||||
import chisel3._
|
||||
import chisel3.experimental.ChiselEnum
|
||||
import chisel3.util._
|
||||
import riscv.Parameters
|
||||
|
||||
object ALUFunctions extends ChiselEnum {
|
||||
val zero, add, sub, sll, slt, xor, or, and, srl, sra, sltu = Value
|
||||
}
|
||||
|
||||
class ALU extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val func = Input(ALUFunctions())
|
||||
|
||||
val op1 = Input(UInt(Parameters.DataWidth))
|
||||
val op2 = Input(UInt(Parameters.DataWidth))
|
||||
|
||||
val result = Output(UInt(Parameters.DataWidth))
|
||||
})
|
||||
|
||||
io.result := 0.U
|
||||
switch(io.func) {
|
||||
is(ALUFunctions.add) {
|
||||
io.result := io.op1 + io.op2
|
||||
}
|
||||
is(ALUFunctions.sub) {
|
||||
io.result := io.op1 - io.op2
|
||||
}
|
||||
is(ALUFunctions.sll) {
|
||||
io.result := io.op1 << io.op2(4, 0)
|
||||
}
|
||||
is(ALUFunctions.slt) {
|
||||
io.result := io.op1.asSInt < io.op2.asSInt
|
||||
}
|
||||
is(ALUFunctions.xor) {
|
||||
io.result := io.op1 ^ io.op2
|
||||
}
|
||||
is(ALUFunctions.or) {
|
||||
io.result := io.op1 | io.op2
|
||||
}
|
||||
is(ALUFunctions.and) {
|
||||
io.result := io.op1 & io.op2
|
||||
}
|
||||
is(ALUFunctions.srl) {
|
||||
io.result := io.op1 >> io.op2(4, 0)
|
||||
}
|
||||
is(ALUFunctions.sra) {
|
||||
io.result := (io.op1.asSInt >> io.op2(4, 0)).asUInt
|
||||
}
|
||||
is(ALUFunctions.sltu) {
|
||||
io.result := io.op1 < io.op2
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
86
lab1/朱梓涵24325356/core/ALUControl.scala
Normal file
86
lab1/朱梓涵24325356/core/ALUControl.scala
Normal file
@@ -0,0 +1,86 @@
|
||||
// Copyright 2021 Howard Lau
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
package riscv.core
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
|
||||
class ALUControl extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val opcode = Input(UInt(7.W))
|
||||
val funct3 = Input(UInt(3.W))
|
||||
val funct7 = Input(UInt(7.W))
|
||||
|
||||
val alu_funct = Output(ALUFunctions())
|
||||
})
|
||||
|
||||
io.alu_funct := ALUFunctions.zero
|
||||
|
||||
switch(io.opcode) {
|
||||
is(InstructionTypes.I) {
|
||||
io.alu_funct := MuxLookup(
|
||||
io.funct3,
|
||||
ALUFunctions.zero,
|
||||
IndexedSeq(
|
||||
InstructionsTypeI.addi -> ALUFunctions.add,
|
||||
InstructionsTypeI.slli -> ALUFunctions.sll,
|
||||
InstructionsTypeI.slti -> ALUFunctions.slt,
|
||||
InstructionsTypeI.sltiu -> ALUFunctions.sltu,
|
||||
InstructionsTypeI.xori -> ALUFunctions.xor,
|
||||
InstructionsTypeI.ori -> ALUFunctions.or,
|
||||
InstructionsTypeI.andi -> ALUFunctions.and,
|
||||
InstructionsTypeI.sri -> Mux(io.funct7(5), ALUFunctions.sra, ALUFunctions.srl)
|
||||
),
|
||||
)
|
||||
}
|
||||
is(InstructionTypes.RM) {
|
||||
io.alu_funct := MuxLookup(
|
||||
io.funct3,
|
||||
ALUFunctions.zero,
|
||||
IndexedSeq(
|
||||
InstructionsTypeR.add_sub -> Mux(io.funct7(5), ALUFunctions.sub, ALUFunctions.add),
|
||||
InstructionsTypeR.sll -> ALUFunctions.sll,
|
||||
InstructionsTypeR.slt -> ALUFunctions.slt,
|
||||
InstructionsTypeR.sltu -> ALUFunctions.sltu,
|
||||
InstructionsTypeR.xor -> ALUFunctions.xor,
|
||||
InstructionsTypeR.or -> ALUFunctions.or,
|
||||
InstructionsTypeR.and -> ALUFunctions.and,
|
||||
InstructionsTypeR.sr -> Mux(io.funct7(5), ALUFunctions.sra, ALUFunctions.srl)
|
||||
),
|
||||
)
|
||||
}
|
||||
is(InstructionTypes.B) {
|
||||
io.alu_funct := ALUFunctions.add
|
||||
}
|
||||
is(InstructionTypes.L) {
|
||||
io.alu_funct := ALUFunctions.add
|
||||
}
|
||||
is(InstructionTypes.S) {
|
||||
io.alu_funct := ALUFunctions.add
|
||||
}
|
||||
is(Instructions.jal) {
|
||||
io.alu_funct := ALUFunctions.add
|
||||
}
|
||||
is(Instructions.jalr) {
|
||||
io.alu_funct := ALUFunctions.add
|
||||
}
|
||||
is(Instructions.lui) {
|
||||
io.alu_funct := ALUFunctions.add
|
||||
}
|
||||
is(Instructions.auipc) {
|
||||
io.alu_funct := ALUFunctions.add
|
||||
}
|
||||
}
|
||||
}
|
||||
82
lab1/朱梓涵24325356/core/CPU.scala
Normal file
82
lab1/朱梓涵24325356/core/CPU.scala
Normal file
@@ -0,0 +1,82 @@
|
||||
// Copyright 2021 Howard Lau
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
package riscv.core
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util.Cat
|
||||
import riscv.{CPUBundle, Parameters}
|
||||
|
||||
class CPU extends Module {
|
||||
val io = IO(new CPUBundle)
|
||||
|
||||
val regs = Module(new RegisterFile)
|
||||
val inst_fetch = Module(new InstructionFetch)
|
||||
val id = Module(new InstructionDecode)
|
||||
val ex = Module(new Execute)
|
||||
val mem = Module(new MemoryAccess)
|
||||
val wb = Module(new WriteBack)
|
||||
|
||||
|
||||
io.deviceSelect := mem.io.memory_bundle.address(Parameters.AddrBits - 1, Parameters.AddrBits - Parameters.SlaveDeviceCountBits)
|
||||
|
||||
inst_fetch.io.jump_address_id := ex.io.if_jump_address
|
||||
inst_fetch.io.jump_flag_id := ex.io.if_jump_flag
|
||||
inst_fetch.io.instruction_valid := io.instruction_valid
|
||||
inst_fetch.io.instruction_read_data := io.instruction
|
||||
io.instruction_address := inst_fetch.io.instruction_address
|
||||
|
||||
regs.io.write_enable := id.io.reg_write_enable
|
||||
regs.io.write_address := id.io.reg_write_address
|
||||
regs.io.write_data := wb.io.regs_write_data
|
||||
regs.io.read_address1 := id.io.regs_reg1_read_address
|
||||
regs.io.read_address2 := id.io.regs_reg2_read_address
|
||||
|
||||
regs.io.debug_read_address := io.debug_read_address
|
||||
io.debug_read_data := regs.io.debug_read_data
|
||||
|
||||
id.io.instruction := inst_fetch.io.instruction
|
||||
|
||||
// lab1(cpu)
|
||||
|
||||
ex.io.instruction := inst_fetch.io.instruction
|
||||
ex.io.instruction_address := inst_fetch.io.instruction_address
|
||||
ex.io.reg1_data := regs.io.read_data1
|
||||
ex.io.reg2_data := regs.io.read_data2
|
||||
ex.io.immediate := id.io.ex_immediate
|
||||
ex.io.aluop1_source := id.io.ex_aluop1_source
|
||||
ex.io.aluop2_source := id.io.ex_aluop2_source
|
||||
|
||||
|
||||
|
||||
// lab1(cpu) end
|
||||
|
||||
|
||||
mem.io.alu_result := ex.io.mem_alu_result
|
||||
mem.io.reg2_data := regs.io.read_data2
|
||||
mem.io.memory_read_enable := id.io.memory_read_enable
|
||||
mem.io.memory_write_enable := id.io.memory_write_enable
|
||||
mem.io.funct3 := inst_fetch.io.instruction(14, 12)
|
||||
|
||||
io.memory_bundle.address := Cat(0.U(Parameters.SlaveDeviceCountBits.W),mem.io.memory_bundle.address(Parameters.AddrBits - 1 - Parameters.SlaveDeviceCountBits, 0))
|
||||
io.memory_bundle.write_enable := mem.io.memory_bundle.write_enable
|
||||
io.memory_bundle.write_data := mem.io.memory_bundle.write_data
|
||||
io.memory_bundle.write_strobe := mem.io.memory_bundle.write_strobe
|
||||
mem.io.memory_bundle.read_data := io.memory_bundle.read_data
|
||||
|
||||
wb.io.instruction_address := inst_fetch.io.instruction_address
|
||||
wb.io.alu_result := ex.io.mem_alu_result
|
||||
wb.io.memory_read_data := mem.io.wb_memory_read_data
|
||||
wb.io.regs_write_source := id.io.wb_reg_write_source
|
||||
}
|
||||
81
lab1/朱梓涵24325356/core/Execute.scala
Normal file
81
lab1/朱梓涵24325356/core/Execute.scala
Normal file
@@ -0,0 +1,81 @@
|
||||
// Copyright 2021 Howard Lau
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
package riscv.core
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util.{Cat, MuxLookup}
|
||||
import riscv.Parameters
|
||||
|
||||
class Execute extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val instruction = Input(UInt(Parameters.InstructionWidth))
|
||||
val instruction_address = Input(UInt(Parameters.AddrWidth))
|
||||
val reg1_data = Input(UInt(Parameters.DataWidth))
|
||||
val reg2_data = Input(UInt(Parameters.DataWidth))
|
||||
val immediate = Input(UInt(Parameters.DataWidth))
|
||||
val aluop1_source = Input(UInt(1.W))
|
||||
val aluop2_source = Input(UInt(1.W))
|
||||
|
||||
val mem_alu_result = Output(UInt(Parameters.DataWidth))
|
||||
val if_jump_flag = Output(Bool())
|
||||
val if_jump_address = Output(UInt(Parameters.DataWidth))
|
||||
})
|
||||
|
||||
val opcode = io.instruction(6, 0)
|
||||
val funct3 = io.instruction(14, 12)
|
||||
val funct7 = io.instruction(31, 25)
|
||||
val rd = io.instruction(11, 7)
|
||||
val uimm = io.instruction(19, 15)
|
||||
|
||||
val alu = Module(new ALU)
|
||||
val alu_ctrl = Module(new ALUControl)
|
||||
|
||||
alu_ctrl.io.opcode := opcode
|
||||
alu_ctrl.io.funct3 := funct3
|
||||
alu_ctrl.io.funct7 := funct7
|
||||
|
||||
// lab1(Execute)
|
||||
alu.io.func := alu_ctrl.io.alu_funct
|
||||
alu.io.op1 := Mux(
|
||||
io.aluop1_source === ALUOp1Source.Register,
|
||||
io.reg1_data,
|
||||
io.instruction_address
|
||||
)
|
||||
alu.io.op2 := Mux(
|
||||
io.aluop2_source === ALUOp2Source.Register,
|
||||
io.reg2_data,
|
||||
io.immediate
|
||||
)
|
||||
|
||||
|
||||
// lab1(Execute) end
|
||||
|
||||
io.mem_alu_result := alu.io.result
|
||||
io.if_jump_flag := opcode === Instructions.jal ||
|
||||
(opcode === Instructions.jalr) ||
|
||||
(opcode === InstructionTypes.B) && MuxLookup(
|
||||
funct3,
|
||||
false.B,
|
||||
IndexedSeq(
|
||||
InstructionsTypeB.beq -> (io.reg1_data === io.reg2_data),
|
||||
InstructionsTypeB.bne -> (io.reg1_data =/= io.reg2_data),
|
||||
InstructionsTypeB.blt -> (io.reg1_data.asSInt < io.reg2_data.asSInt),
|
||||
InstructionsTypeB.bge -> (io.reg1_data.asSInt >= io.reg2_data.asSInt),
|
||||
InstructionsTypeB.bltu -> (io.reg1_data.asUInt < io.reg2_data.asUInt),
|
||||
InstructionsTypeB.bgeu -> (io.reg1_data.asUInt >= io.reg2_data.asUInt)
|
||||
)
|
||||
)
|
||||
io.if_jump_address := io.immediate + Mux(opcode === Instructions.jalr, io.reg1_data, io.instruction_address)
|
||||
}
|
||||
205
lab1/朱梓涵24325356/core/InstructionDecode.scala
Normal file
205
lab1/朱梓涵24325356/core/InstructionDecode.scala
Normal file
@@ -0,0 +1,205 @@
|
||||
// Copyright 2021 Howard Lau
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
package riscv.core
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import riscv.Parameters
|
||||
|
||||
object InstructionTypes {
|
||||
val L = "b0000011".U
|
||||
val I = "b0010011".U
|
||||
val S = "b0100011".U
|
||||
val RM = "b0110011".U
|
||||
val B = "b1100011".U
|
||||
}
|
||||
|
||||
object Instructions {
|
||||
val lui = "b0110111".U
|
||||
val nop = "b0000001".U
|
||||
val jal = "b1101111".U
|
||||
val jalr = "b1100111".U
|
||||
val auipc = "b0010111".U
|
||||
val csr = "b1110011".U
|
||||
val fence = "b0001111".U
|
||||
}
|
||||
|
||||
object InstructionsTypeL {
|
||||
val lb = "b000".U
|
||||
val lh = "b001".U
|
||||
val lw = "b010".U
|
||||
val lbu = "b100".U
|
||||
val lhu = "b101".U
|
||||
}
|
||||
|
||||
object InstructionsTypeI {
|
||||
val addi = 0.U
|
||||
val slli = 1.U
|
||||
val slti = 2.U
|
||||
val sltiu = 3.U
|
||||
val xori = 4.U
|
||||
val sri = 5.U
|
||||
val ori = 6.U
|
||||
val andi = 7.U
|
||||
}
|
||||
|
||||
object InstructionsTypeS {
|
||||
val sb = "b000".U
|
||||
val sh = "b001".U
|
||||
val sw = "b010".U
|
||||
}
|
||||
|
||||
object InstructionsTypeR {
|
||||
val add_sub = 0.U
|
||||
val sll = 1.U
|
||||
val slt = 2.U
|
||||
val sltu = 3.U
|
||||
val xor = 4.U
|
||||
val sr = 5.U
|
||||
val or = 6.U
|
||||
val and = 7.U
|
||||
}
|
||||
|
||||
object InstructionsTypeM {
|
||||
val mul = 0.U
|
||||
val mulh = 1.U
|
||||
val mulhsu = 2.U
|
||||
val mulhum = 3.U
|
||||
val div = 4.U
|
||||
val divu = 5.U
|
||||
val rem = 6.U
|
||||
val remu = 7.U
|
||||
}
|
||||
|
||||
object InstructionsTypeB {
|
||||
val beq = "b000".U
|
||||
val bne = "b001".U
|
||||
val blt = "b100".U
|
||||
val bge = "b101".U
|
||||
val bltu = "b110".U
|
||||
val bgeu = "b111".U
|
||||
}
|
||||
|
||||
object InstructionsTypeCSR {
|
||||
val csrrw = "b001".U
|
||||
val csrrs = "b010".U
|
||||
val csrrc = "b011".U
|
||||
val csrrwi = "b101".U
|
||||
val csrrsi = "b110".U
|
||||
val csrrci = "b111".U
|
||||
}
|
||||
|
||||
object InstructionsNop {
|
||||
val nop = 0x00000013L.U(Parameters.DataWidth)
|
||||
}
|
||||
|
||||
object InstructionsRet {
|
||||
val mret = 0x30200073L.U(Parameters.DataWidth)
|
||||
val ret = 0x00008067L.U(Parameters.DataWidth)
|
||||
}
|
||||
|
||||
object InstructionsEnv {
|
||||
val ecall = 0x00000073L.U(Parameters.DataWidth)
|
||||
val ebreak = 0x00100073L.U(Parameters.DataWidth)
|
||||
}
|
||||
|
||||
object ALUOp1Source {
|
||||
val Register = 0.U(1.W)
|
||||
val InstructionAddress = 1.U(1.W)
|
||||
}
|
||||
|
||||
object ALUOp2Source {
|
||||
val Register = 0.U(1.W)
|
||||
val Immediate = 1.U(1.W)
|
||||
}
|
||||
|
||||
object RegWriteSource {
|
||||
val ALUResult = 0.U(2.W)
|
||||
val Memory = 1.U(2.W)
|
||||
//val CSR = 2.U(2.W)
|
||||
val NextInstructionAddress = 3.U(2.W)
|
||||
}
|
||||
|
||||
class InstructionDecode extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val instruction = Input(UInt(Parameters.InstructionWidth))
|
||||
|
||||
val regs_reg1_read_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
|
||||
val regs_reg2_read_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
|
||||
val ex_immediate = Output(UInt(Parameters.DataWidth))
|
||||
val ex_aluop1_source = Output(UInt(1.W))
|
||||
val ex_aluop2_source = Output(UInt(1.W))
|
||||
val memory_read_enable = Output(Bool())
|
||||
val memory_write_enable = Output(Bool())
|
||||
val wb_reg_write_source = Output(UInt(2.W))
|
||||
val reg_write_enable = Output(Bool())
|
||||
val reg_write_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
|
||||
})
|
||||
val opcode = io.instruction(6, 0)
|
||||
val funct3 = io.instruction(14, 12)
|
||||
val funct7 = io.instruction(31, 25)
|
||||
val rd = io.instruction(11, 7)
|
||||
val rs1 = io.instruction(19, 15)
|
||||
val rs2 = io.instruction(24, 20)
|
||||
|
||||
io.regs_reg1_read_address := Mux(opcode === Instructions.lui, 0.U(Parameters.PhysicalRegisterAddrWidth), rs1)
|
||||
io.regs_reg2_read_address := rs2
|
||||
val immediate = MuxLookup(
|
||||
opcode,
|
||||
Cat(Fill(20, io.instruction(31)), io.instruction(31, 20)),
|
||||
IndexedSeq(
|
||||
InstructionTypes.I -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 20)),
|
||||
InstructionTypes.L -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 20)),
|
||||
Instructions.jalr -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 20)),
|
||||
InstructionTypes.S -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 25), io.instruction(11, 7)),
|
||||
InstructionTypes.B -> Cat(Fill(20, io.instruction(31)), io.instruction(7), io.instruction(30, 25), io.instruction(11, 8), 0.U(1.W)),
|
||||
Instructions.lui -> Cat(io.instruction(31, 12), 0.U(12.W)),
|
||||
Instructions.auipc -> Cat(io.instruction(31, 12), 0.U(12.W)),
|
||||
Instructions.jal -> Cat(Fill(12, io.instruction(31)), io.instruction(19, 12), io.instruction(20), io.instruction(30, 21), 0.U(1.W))
|
||||
)
|
||||
)
|
||||
io.ex_immediate := immediate
|
||||
io.ex_aluop1_source := Mux(
|
||||
opcode === Instructions.auipc || opcode === InstructionTypes.B || opcode === Instructions.jal,
|
||||
ALUOp1Source.InstructionAddress,
|
||||
ALUOp1Source.Register
|
||||
)
|
||||
|
||||
// lab1(InstructionDecode)
|
||||
io.ex_aluop2_source := Mux(opcode === InstructionTypes.RM,
|
||||
ALUOp2Source.Register,
|
||||
ALUOp2Source.Immediate
|
||||
)
|
||||
// 仅当指令是 Load 类型时，才使能内存读。
|
||||
io.memory_read_enable := opcode === InstructionTypes.L
|
||||
// 仅当指令是 Store 类型时，才使能内存写。
|
||||
io.memory_write_enable := opcode === InstructionTypes.S
|
||||
// 根据指令类型，选择写回寄存器的数据来源。
|
||||
io.wb_reg_write_source := MuxLookup(
|
||||
opcode,
|
||||
RegWriteSource.ALUResult // 默认来源是ALU计算结果
|
||||
)( // 使用新的 MuxLookup 语法
|
||||
IndexedSeq(
|
||||
InstructionTypes.L -> RegWriteSource.Memory, // Load 指令来源是内存
|
||||
Instructions.jal -> RegWriteSource.NextInstructionAddress, // jal/jalr 来源是下一条指令地址 (PC+4)
|
||||
Instructions.jalr -> RegWriteSource.NextInstructionAddress
|
||||
)
|
||||
)
|
||||
// lab1(InstructionDecode) end
|
||||
io.reg_write_enable := (opcode === InstructionTypes.RM) || (opcode === InstructionTypes.I) ||
|
||||
(opcode === InstructionTypes.L) || (opcode === Instructions.auipc) || (opcode === Instructions.lui) ||
|
||||
(opcode === Instructions.jal) || (opcode === Instructions.jalr)
|
||||
io.reg_write_address := io.instruction(11, 7)
|
||||
}
|
||||
55
lab1/朱梓涵24325356/core/InstructionFetch.scala
Normal file
55
lab1/朱梓涵24325356/core/InstructionFetch.scala
Normal file
@@ -0,0 +1,55 @@
|
||||
// Copyright 2021 Howard Lau
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
package riscv.core
|
||||
|
||||
import chisel3._
|
||||
import riscv.Parameters
|
||||
|
||||
object ProgramCounter {
|
||||
val EntryAddress = Parameters.EntryAddress
|
||||
}
|
||||
|
||||
class InstructionFetch extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val jump_flag_id = Input(Bool())
|
||||
val jump_address_id = Input(UInt(Parameters.AddrWidth))
|
||||
val instruction_read_data = Input(UInt(Parameters.DataWidth))
|
||||
val instruction_valid = Input(Bool())
|
||||
|
||||
val instruction_address = Output(UInt(Parameters.AddrWidth))
|
||||
val instruction = Output(UInt(Parameters.InstructionWidth))
|
||||
})
|
||||
val pc = RegInit(ProgramCounter.EntryAddress)
|
||||
|
||||
when(io.instruction_valid) {
|
||||
io.instruction := io.instruction_read_data
|
||||
// lab1(InstructionFetch)
|
||||
|
||||
when(io.jump_flag_id) {
|
||||
pc := io.jump_address_id
|
||||
}.otherwise {
|
||||
pc := pc + 4.U
|
||||
}
|
||||
|
||||
|
||||
// la1(InstructionFetch) end
|
||||
|
||||
|
||||
}.otherwise{
|
||||
pc := pc
|
||||
io.instruction := 0x00000013.U
|
||||
}
|
||||
io.instruction_address := pc
|
||||
}
|
||||
106
lab1/朱梓涵24325356/core/MemoryAccess.scala
Normal file
106
lab1/朱梓涵24325356/core/MemoryAccess.scala
Normal file
@@ -0,0 +1,106 @@
|
||||
// Copyright 2022 Canbin Huang
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
package riscv.core
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import peripheral.RAMBundle
|
||||
import riscv.Parameters
|
||||
|
||||
class MemoryAccess extends Module {
|
||||
val io = IO(new Bundle() {
|
||||
val alu_result = Input(UInt(Parameters.DataWidth))
|
||||
val reg2_data = Input(UInt(Parameters.DataWidth))
|
||||
val memory_read_enable = Input(Bool())
|
||||
val memory_write_enable = Input(Bool())
|
||||
val funct3 = Input(UInt(3.W))
|
||||
|
||||
val wb_memory_read_data = Output(UInt(Parameters.DataWidth))
|
||||
|
||||
val memory_bundle = Flipped(new RAMBundle)
|
||||
})
|
||||
val mem_address_index = io.alu_result(log2Up(Parameters.WordSize) - 1, 0).asUInt
|
||||
|
||||
io.memory_bundle.write_enable := false.B
|
||||
io.memory_bundle.write_data := 0.U
|
||||
io.memory_bundle.address := io.alu_result
|
||||
io.memory_bundle.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B))
|
||||
io.wb_memory_read_data := 0.U
|
||||
|
||||
when(io.memory_read_enable) {
|
||||
val data = io.memory_bundle.read_data
|
||||
io.wb_memory_read_data := MuxLookup(
|
||||
io.funct3,
|
||||
0.U,
|
||||
IndexedSeq(
|
||||
InstructionsTypeL.lb -> MuxLookup(
|
||||
mem_address_index,
|
||||
Cat(Fill(24, data(31)), data(31, 24)),
|
||||
IndexedSeq(
|
||||
0.U -> Cat(Fill(24, data(7)), data(7, 0)),
|
||||
1.U -> Cat(Fill(24, data(15)), data(15, 8)),
|
||||
2.U -> Cat(Fill(24, data(23)), data(23, 16))
|
||||
)
|
||||
),
|
||||
InstructionsTypeL.lbu -> MuxLookup(
|
||||
mem_address_index,
|
||||
Cat(Fill(24, 0.U), data(31, 24)),
|
||||
IndexedSeq(
|
||||
0.U -> Cat(Fill(24, 0.U), data(7, 0)),
|
||||
1.U -> Cat(Fill(24, 0.U), data(15, 8)),
|
||||
2.U -> Cat(Fill(24, 0.U), data(23, 16))
|
||||
)
|
||||
),
|
||||
InstructionsTypeL.lh -> Mux(
|
||||
mem_address_index === 0.U,
|
||||
Cat(Fill(16, data(15)), data(15, 0)),
|
||||
Cat(Fill(16, data(31)), data(31, 16))
|
||||
|
||||
),
|
||||
InstructionsTypeL.lhu -> Mux(
|
||||
mem_address_index === 0.U,
|
||||
Cat(Fill(16, 0.U), data(15, 0)),
|
||||
Cat(Fill(16, 0.U), data(31, 16))
|
||||
),
|
||||
InstructionsTypeL.lw -> data
|
||||
)
|
||||
)
|
||||
}.elsewhen(io.memory_write_enable) {
|
||||
io.memory_bundle.write_data := io.reg2_data
|
||||
io.memory_bundle.write_enable := true.B
|
||||
io.memory_bundle.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B))
|
||||
when(io.funct3 === InstructionsTypeS.sb) {
|
||||
io.memory_bundle.write_strobe(mem_address_index) := true.B
|
||||
io.memory_bundle.write_data := io.reg2_data(Parameters.ByteBits, 0) << (mem_address_index << log2Up(Parameters.ByteBits).U)
|
||||
}.elsewhen(io.funct3 === InstructionsTypeS.sh) {
|
||||
when(mem_address_index === 0.U) {
|
||||
for (i <- 0 until Parameters.WordSize / 2) {
|
||||
io.memory_bundle.write_strobe(i) := true.B
|
||||
}
|
||||
io.memory_bundle.write_data := io.reg2_data(Parameters.WordSize / 2 * Parameters.ByteBits, 0)
|
||||
}.otherwise {
|
||||
for (i <- Parameters.WordSize / 2 until Parameters.WordSize) {
|
||||
io.memory_bundle.write_strobe(i) := true.B
|
||||
}
|
||||
io.memory_bundle.write_data := io.reg2_data(Parameters.WordSize / 2 * Parameters.ByteBits, 0) << (Parameters
|
||||
.WordSize / 2 * Parameters.ByteBits)
|
||||
}
|
||||
}.elsewhen(io.funct3 === InstructionsTypeS.sw) {
|
||||
for (i <- 0 until Parameters.WordSize) {
|
||||
io.memory_bundle.write_strobe(i) := true.B
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
70
lab1/朱梓涵24325356/core/RegisterFile.scala
Normal file
70
lab1/朱梓涵24325356/core/RegisterFile.scala
Normal file
@@ -0,0 +1,70 @@
|
||||
// Copyright 2021 Howard Lau
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
package riscv.core
|
||||
|
||||
import chisel3._
|
||||
import riscv.Parameters
|
||||
|
||||
object Registers extends Enumeration {
|
||||
type Register = Value
|
||||
val zero,
|
||||
ra, sp, gp, tp,
|
||||
t0, t1, t2, fp,
|
||||
s1,
|
||||
a0, a1, a2, a3, a4, a5, a6, a7,
|
||||
s2, s3, s4, s5, s6, s7, s8, s9, s10, s11,
|
||||
t3, t4, t5, t6 = Value
|
||||
}
|
||||
|
||||
class RegisterFile extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val write_enable = Input(Bool())
|
||||
val write_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
|
||||
val write_data = Input(UInt(Parameters.DataWidth))
|
||||
|
||||
val read_address1 = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
|
||||
val read_address2 = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
|
||||
val read_data1 = Output(UInt(Parameters.DataWidth))
|
||||
val read_data2 = Output(UInt(Parameters.DataWidth))
|
||||
|
||||
val debug_read_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
|
||||
val debug_read_data = Output(UInt(Parameters.DataWidth))
|
||||
})
|
||||
val registers = RegInit(VecInit(Seq.fill(Parameters.PhysicalRegisters)(0.U(Parameters.DataWidth))))
|
||||
|
||||
when(!reset.asBool) {
|
||||
when(io.write_enable && io.write_address =/= 0.U) {
|
||||
registers(io.write_address) := io.write_data
|
||||
}
|
||||
}
|
||||
|
||||
io.read_data1 := Mux(
|
||||
io.read_address1 === 0.U,
|
||||
0.U,
|
||||
registers(io.read_address1)
|
||||
)
|
||||
|
||||
io.read_data2 := Mux(
|
||||
io.read_address2 === 0.U,
|
||||
0.U,
|
||||
registers(io.read_address2)
|
||||
)
|
||||
|
||||
io.debug_read_data := Mux(
|
||||
io.debug_read_address === 0.U,
|
||||
0.U,
|
||||
registers(io.debug_read_address)
|
||||
)
|
||||
}
|
||||
37
lab1/朱梓涵24325356/core/WriteBack.scala
Normal file
37
lab1/朱梓涵24325356/core/WriteBack.scala
Normal file
@@ -0,0 +1,37 @@
|
||||
// Copyright 2022 Canbin Huang
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
package riscv.core
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import riscv.Parameters
|
||||
|
||||
class WriteBack extends Module {
|
||||
val io = IO(new Bundle() {
|
||||
val instruction_address = Input(UInt(Parameters.AddrWidth))
|
||||
val alu_result = Input(UInt(Parameters.DataWidth))
|
||||
val memory_read_data = Input(UInt(Parameters.DataWidth))
|
||||
val regs_write_source = Input(UInt(2.W))
|
||||
val regs_write_data = Output(UInt(Parameters.DataWidth))
|
||||
})
|
||||
io.regs_write_data := MuxLookup(
|
||||
io.regs_write_source,
|
||||
io.alu_result,
|
||||
IndexedSeq(
|
||||
RegWriteSource.Memory -> io.memory_read_data,
|
||||
RegWriteSource.NextInstructionAddress -> (io.instruction_address + 4.U)
|
||||
)
|
||||
)
|
||||
}
|
||||
BIN
lab1/朱梓涵24325356/report.pdf
Normal file
BIN
lab1/朱梓涵24325356/report.pdf
Normal file
Binary file not shown.
204
lab1/测试文件报告.tex
Normal file
204
lab1/测试文件报告.tex
Normal file
@@ -0,0 +1,204 @@
|
||||
\section{测试文件}
|
||||
\label{sec:testing}
|
||||
|
||||
CPUTest.scala 测试了整个 CPU 运行三个程序的正确性。本节选择其中两个程序的运行进行详细分析，查看 csrc 文件夹下对应 C 文件的内容，概述该程序做了什么，执行结果如何在 Chisel 测试中被检查；在测试波形图上简单分析其执行，并说明波形图最后几个周期检查执行结果时的波形。
|
||||
|
||||
\subsection{整体测试框架}
|
||||
|
||||
CPUTest.scala 定义了三个主要的测试类：FibonacciTest、QuicksortTest 和 ByteAccessTest。每个测试都基于 ChiselTest 框架，通过 TestTopModule 作为顶层模块来驱动 CPU 执行相应的程序。测试框架的核心结构如下：
|
||||
|
||||
\begin{lstlisting}[caption={CPUTest.scala 测试框架结构}, style=ScalaChiselStyle]
|
||||
class TestTopModule(exeFilename: String) extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val mem_debug_read_address = Input(UInt(Parameters.AddrWidth))
|
||||
val regs_debug_read_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
|
||||
val regs_debug_read_data = Output(UInt(Parameters.DataWidth))
|
||||
val mem_debug_read_data = Output(UInt(Parameters.DataWidth))
|
||||
})
|
||||
// 实例化内存、指令ROM、CPU等模块
|
||||
// 提供调试接口用于验证执行结果
|
||||
}
|
||||
\end{lstlisting}
|
||||
|
||||
测试框架通过调试接口读取内存和寄存器的值，与预期结果进行比较，从而验证 CPU 执行程序的正确性。
|
||||
|
||||
\subsection{斐波那契数列计算测试}
|
||||
|
||||
\subsubsection{程序功能分析}
|
||||
|
||||
fibonacci.c 程序实现了一个递归计算斐波那契数列的功能。程序代码如下：
|
||||
|
||||
\begin{lstlisting}[language=C, caption={fibonacci.c 程序代码}, style=CStyle]
|
||||
int fib(int a) {
|
||||
if (a == 1 || a == 2) return 1;
|
||||
return fib(a - 1) + fib(a - 2);
|
||||
}
|
||||
|
||||
int main() {
|
||||
*(int *)(4) = fib(10);
|
||||
}
|
||||
\end{lstlisting}
|
||||
|
||||
该程序通过递归算法计算斐波那契数列的第 10 项（fib(10)），并将结果存储到内存地址 0x4 处。斐波那契数列的递归定义为：
|
||||
\begin{itemize}
|
||||
\item fib(1) = 1
|
||||
\item fib(2) = 1
|
||||
\item fib(n) = fib(n-1) + fib(n-2) (n > 2)
|
||||
\end{itemize}
|
||||
|
||||
因此，fib(10) 的计算结果为 55。
|
||||
|
||||
\subsubsection{测试结果检查}
|
||||
|
||||
在 FibonacciTest 中，测试代码通过以下方式检查结果：
|
||||
|
||||
\begin{lstlisting}[caption={斐波那契测试的结果检查}, style=ScalaChiselStyle]
|
||||
c.io.mem_debug_read_address.poke(4.U)
|
||||
c.clock.step()
|
||||
c.io.mem_debug_read_data.expect(55.U)
|
||||
\end{lstlisting}
|
||||
|
||||
测试首先执行 50,000 个时钟周期（50 × 1000），确保递归计算完成。然后通过内存调试接口读取地址 0x4 的值，验证是否为预期的 55。
|
||||
|
||||
\subsubsection{波形图分析}
|
||||
|
||||
基于 VCD 文件分析，斐波那契程序执行过程中的关键信号包括：
|
||||
|
||||
\begin{itemize}
|
||||
\item \texttt{cpu\_io\_instruction\_address}：程序计数器值，显示指令执行流程
|
||||
\item \texttt{mem\_io\_bundle\_write\_enable}：内存写使能信号，标识数据写入操作
|
||||
\item \texttt{mem\_io\_bundle\_address}：内存访问地址
|
||||
\item \texttt{mem\_io\_bundle\_write\_data}：要写入内存的数据
|
||||
\item \texttt{io\_mem\_debug\_read\_data}：调试接口读取的内存数据
|
||||
\end{itemize}
|
||||
|
||||
在程序执行的最后阶段，可以观察到：
|
||||
\begin{enumerate}
|
||||
\item \texttt{mem\_io\_bundle\_write\_enable} 信号置高，表示正在进行内存写入
|
||||
\item \texttt{mem\_io\_bundle\_address} 显示为 0x00000004，写入地址为 4
|
||||
\item \texttt{mem\_io\_bundle\_write\_data} 显示为 0x00000037（十进制 55），即 fib(10) 的计算结果
|
||||
\item 调试接口 \texttt{io\_mem\_debug\_read\_data} 最终稳定显示 0x00000037
|
||||
\end{enumerate}
|
||||
|
||||
\subsection{快速排序算法测试}
|
||||
|
||||
\subsubsection{程序功能分析}
|
||||
|
||||
quicksort.c 程序实现了快速排序算法，对 10 个整数进行排序：
|
||||
|
||||
\begin{lstlisting}[language=C, caption={quicksort.c 程序代码}, style=CStyle]
|
||||
void quicksort(int *arr, int l, int r) {
|
||||
if (l >= r) return;
|
||||
int pivot = arr[l];
|
||||
int i = l, j = r;
|
||||
while (i < j) {
|
||||
while(arr[j] >= pivot && i < j) --j;
|
||||
arr[i] = arr[j];
|
||||
while(arr[i] < pivot && i < j) ++i;
|
||||
arr[j] = arr[i];
|
||||
}
|
||||
arr[i] = pivot;
|
||||
quicksort(arr, l, i - 1);
|
||||
quicksort(arr, i + 1, r);
|
||||
}
|
||||
|
||||
int main() {
|
||||
int nums[10];
|
||||
// 初始化数组：[6, 2, 4, 5, 3, 1, 0, 9, 7, 8]
|
||||
nums[0] = 6; nums[1] = 2; nums[2] = 4; nums[3] = 5;
|
||||
nums[4] = 3; nums[5] = 1; nums[6] = 0; nums[7] = 9;
|
||||
nums[8] = 7; nums[9] = 8;
|
||||
|
||||
quicksort(nums, 0, 9);
|
||||
|
||||
// 将排序结果写入内存地址 4, 8, 12, ..., 40
|
||||
for (int i = 1; i <= 10; ++i) {
|
||||
*(int *)(i * 4) = nums[i - 1];
|
||||
}
|
||||
}
|
||||
\end{lstlisting}
|
||||
|
||||
程序将初始数组 [6, 2, 4, 5, 3, 1, 0, 9, 7, 8] 排序为 [0, 1, 2, 3, 4, 5, 6, 7, 8, 9]，然后将结果依次写入内存地址 4, 8, 12, ..., 40。
|
||||
|
||||
\subsubsection{测试结果检查}
|
||||
|
||||
在 QuicksortTest 中，测试代码验证排序结果：
|
||||
|
||||
\begin{lstlisting}[caption={快速排序测试的结果检查}, style=ScalaChiselStyle]
|
||||
for (i <- 1 to 10) {
|
||||
c.io.mem_debug_read_address.poke((4 * i).U)
|
||||
c.clock.step()
|
||||
c.io.mem_debug_read_data.expect((i - 1).U)
|
||||
}
|
||||
\end{lstlisting}
|
||||
|
||||
测试循环读取内存地址 4, 8, 12, ..., 40 的值，期望得到 0, 1, 2, ..., 9，验证排序的正确性。
|
||||
|
||||
\subsubsection{波形图分析}
|
||||
|
||||
快速排序程序执行过程中的关键信号变化：
|
||||
\begin{itemize}
|
||||
\item 多次内存写入操作，\texttt{mem\_io\_bundle\_write\_enable} 信号周期性置高
|
||||
\item \texttt{mem\_io\_bundle\_address} 依次显示 0x00000004, 0x00000008, ..., 0x00000028
|
||||
\item \texttt{mem\_io\_bundle\_write\_data} 依次显示 0x00000000, 0x00000001, ..., 0x00000009
|
||||
\item 调试接口验证阶段，\texttt{io\_mem\_debug\_read\_data} 依次显示正确的排序值
|
||||
\end{itemize}
|
||||
|
||||
\subsection{字节访问测试}
|
||||
|
||||
\subsubsection{程序功能分析}
|
||||
|
||||
ByteAccessTest 测试 CPU 对单个字节的存储和加载功能，验证字节级内存访问的正确性。该测试使用 sb.asmbin 程序，主要测试 Store Byte (sb) 和 Load Byte (lb) 指令。
|
||||
|
||||
\subsubsection{测试结果检查}
|
||||
|
||||
测试通过寄存器调试接口验证字节操作的正确性：
|
||||
|
||||
\begin{lstlisting}[caption={字节访问测试的结果检查}, style=ScalaChiselStyle]
|
||||
c.io.regs_debug_read_address.poke(5.U)
|
||||
c.io.regs_debug_read_data.expect(0xDEADBEEFL.U)
|
||||
c.io.regs_debug_read_address.poke(6.U)
|
||||
c.io.regs_debug_read_data.expect(0xEF.U)
|
||||
c.io.regs_debug_read_address.poke(1.U)
|
||||
c.io.regs_debug_read_data.expect(0x15EF.U)
|
||||
\end{lstlisting}
|
||||
|
||||
测试验证了字节存储和加载操作对寄存器值的影响，确保字节级内存访问的正确实现。
|
||||
|
||||
\subsection{波形图截取建议}
|
||||
|
||||
基于 VCD 文件分析，建议截取以下关键波形图：
|
||||
|
||||
\begin{enumerate}
|
||||
\item \textbf{斐波那契程序执行结果写入阶段}
|
||||
\begin{itemize}
|
||||
\item 信号：\texttt{mem\_io\_bundle\_write\_enable}, \texttt{mem\_io\_bundle\_address}, \texttt{mem\_io\_bundle\_write\_data}
|
||||
\item 时间点：程序最后几个周期，fib(10) 结果写入内存地址 0x4
|
||||
\item 特征：写使能置高，地址为 0x00000004，数据为 0x00000037
|
||||
\end{itemize}
|
||||
|
||||
\item \textbf{快速排序程序内存写入序列}
|
||||
\begin{itemize}
|
||||
\item 信号：\texttt{mem\_io\_bundle\_write\_enable}, \texttt{mem\_io\_bundle\_address}, \texttt{mem\_io\_bundle\_write\_data}
|
||||
\item 时间点：排序完成后，结果依次写入内存的阶段
|
||||
\item 特征：连续的写操作，地址递增，数据为排序后的序列 0-9
|
||||
\end{itemize}
|
||||
|
||||
\item \textbf{调试接口读取阶段}
|
||||
\begin{itemize}
|
||||
\item 信号：\texttt{io\_mem\_debug\_read\_address}, \texttt{io\_mem\_debug\_read\_data}
|
||||
\item 时间点：测试的最后阶段，验证执行结果
|
||||
\item 特征：调试地址变化，对应数据正确显示
|
||||
\end{itemize}
|
||||
\end{enumerate}
|
||||
|
||||
\subsection{测试总结}
|
||||
|
||||
CPUTest.scala 通过三个不同复杂度的测试程序全面验证了单周期 CPU 的功能：
|
||||
\begin{itemize}
|
||||
\item \textbf{斐波那契测试}验证了 CPU 的递归函数调用能力，包括栈操作、参数传递和返回值处理
|
||||
\item \textbf{快速排序测试}验证了 CPU 的数组处理、循环控制和复杂算法执行能力
|
||||
\item \textbf{字节访问测试}验证了 CPU 对不同类型内存访问指令的支持
|
||||
\end{itemize}
|
||||
|
||||
所有测试都通过内存和寄存器调试接口验证执行结果，确保 CPU 能够正确执行各种程序。波形图分析显示了程序执行过程中的关键信号变化，验证了数据通路的正确性和控制信号的时序准确性。
|
||||
9
lab4/.claude/settings.local.json
Normal file
9
lab4/.claude/settings.local.json
Normal file
@@ -0,0 +1,9 @@
|
||||
{
|
||||
"permissions": {
|
||||
"allow": [
|
||||
"Bash(sbt \"testOnly *BusTest\")"
|
||||
],
|
||||
"deny": [],
|
||||
"ask": []
|
||||
}
|
||||
}
|
||||
124
lab4/要求.txt
Normal file
124
lab4/要求.txt
Normal file
@@ -0,0 +1,124 @@
|
||||
在本实验中，您将学习到：
|
||||
|
||||
AXI4-Lite 协议
|
||||
使用状态机实现总线协议
|
||||
在开始实现 AXI4-Lite 总线协议前，请您阅读 总线 以了解 AXI4-Lite 协议的基本知识。
|
||||
|
||||
不管使用 IDE 还是执行命令，根目录是 lab4 文件夹。
|
||||
|
||||
框架与接口总览🚁
|
||||
|
||||
|
||||
本实验中使用 AXI4-Lite 协议通信的框架图
|
||||
|
||||
为了使基于多周期流水线的 CPU 拥有使用 AXI4-Lite 协议与外部通信的能力，本实验中修改了 CPU 部件之间、CPU与外部设备之间 的通信框架，如上图所示： 左侧的 CPU 和右侧的 内存模块使用 AXI4-Lite 协议通信，但 AXI4-Lite 的通信协议较为复杂，我们将 AXI4-Lite 的通信实现包装在类 AXI4LiteMaster 和 AXI4LiteSlave 中，使得需要调用 AXI4-Lite 通信的硬件直接使用这两个类即可。
|
||||
|
||||
在 AXI4LiteMaster 和 AXI4LiteSlave 之间通信的接口是 AXI4LiteChannels ，其包含 AXI4-Lite 所定义的 5 个通道及相应信号线。当您实现自己的 AXI4LiteMaster 和 AXI4LiteSlave 后，您的硬件设备就可以和其他厂商的设备进行通信，只要其支持 AXI4-Lite 协议。
|
||||
|
||||
AXI4LiteSlaveBundle 和 AXI4LiteMasterBundle 是本实验中硬件操纵 AXI4LiteMaster 和 AXI4LiteSlave 的接口，其接口定义比 AXI4-Lite 简单得多，为的就是用简单地把读写操作告知 AXI4LiteMaster 或 AXI4LiteSlave，并由它们执行。
|
||||
|
||||
为让您更好地理解，上面的框架可以比作用户用不同语言向手机输入消息，手机通过无线网络传输信息。CPU 内需要通信的部件如同一个用户，需要和另一个用户 —— 内存进行通信，于是我们开发了一种遵循无线通信协议的手机，手机对应于 AXI4LiteMaster 和 AXI4LiteSlave，通信协议则对应于符合 AXI4-Lite 规范的 AXI4LiteChannels 。用户使用语音输入，即 CPU 或 内存通过 两个 Bundle 将读写操作告知 AXI4LiteMaster 和 AXI4LiteSlave，而两台手机之间的通信则对应总线上以 AXI4-Lite 的通信。
|
||||
|
||||
您在此处的工作就是打造一部这样的手机，使得不仅两台您造出的手机能相互通信，也能和其他厂商的手机进行通信。
|
||||
|
||||
|
||||
|
||||
将本实验 AXI4-Lite 通信框架比作用户通过语音输入消息通信
|
||||
|
||||
设备与 AXI4LiteMaster 和 AXI4LiteSlave 通信🚁
|
||||
这一部分对应上图类比中如何实现不同 用户☺️ 语音输入到 手机📱 的部分。
|
||||
|
||||
主机侧（Master）的通信接口在 AXI4Lite.scala 中 AXI4LiteMasterBundle定义，各信号含义为：
|
||||
|
||||
信号 含义及时序要求
|
||||
address 读或写地址
|
||||
read 执行读操作，每个操作该信号置1持续1周期
|
||||
write 执行写操作，每个操作该信号置1持续1周期
|
||||
read_data/write_data 读写数据
|
||||
write_strobe 写选通
|
||||
read_valid 读完成，当从设备返回数据时，该信号置1持续1周期
|
||||
write_valid 写完成，当从设备确认写入后，该信号置1持续1周期
|
||||
busy AXI4LiteMaster正忙，暂不接收任何读写请求
|
||||
这样，CPU 作为主动发出读写请求的一方，其通过 read, write, write_data 和 address 发出请求，并等待 [read|write]_valid 信号以得知操作完成。 相应地，内存、定时器、键盘等作为被动接收读写请求的一方，其需要提供 read_data 和 [read|write]_valid 信号。
|
||||
|
||||
为什么需要 valid 信号
|
||||
|
||||
valid 信号指示数据有效或操作完成。例如读操作完成并在 read_data 传回数据时，需要 read_valid 来指示此时 read_data 上是有效的数据。这一方面是因为 read_data 不会一直保持，另一方面也不知道读请求发送后过多久能读回。 read_valid 的作用就像提醒您外卖到了的短信。
|
||||
|
||||
用状态机实现总线协议🚁
|
||||
本实验的主要内容就是实现 AXI4-Lite 总线协议里面的主从设备间的读写流程的状态转换。 这对应之前类比中手机📱 间通过某种无线协议进行通信。
|
||||
|
||||
为简单起见，我们使用状态机来实现 AXI4 接口，即 AXI4LiteMaster 和 AXI4LiteSlave 用状态机实现，在握手完成时进行状态转换，以此逐个完成事务。 我们给出一个可参考的状态机，如下图，左图是主设备总线接口的状态机，右图是从设备总线接口的状态机：
|
||||
|
||||
axi-fsm
|
||||
|
||||
进行一次读操作🚁
|
||||
现在我们以 CPU 取指令过程为例，说明如何进行一次读操作。
|
||||
|
||||
首先，取指阶段（IF）发出取指信号，包括将 AXI4LiteMasterBundle 的 read 置 1，并将 PC 送至 address， 此时 CPU 的 AXI 主机（AXI Master）收到 IF 的信号，主机内部状态由空闲（Idle）跳转到 读地址状态 (ReadAddr)，产生并发送读请求 (ARVALID)、读地址 (ARADDR)。
|
||||
|
||||
当内存模块的从机（AXI Slave） 收到 ARVALID 时，其内部状态跳转至 读地址状态 (ReadAddr)，保存 ARADDR ，并将 读地址准备(ARREADY) 信号置 1 表明读地址已收取，此时即完成了一次握手，并完成读地址的传输。获取读取地址后，从机通过 AXI4LiteSlaveBundle 告知内存芯片读取指定位置的数据，并等待读操作完成。
|
||||
|
||||
当内存芯片读回数据时，其通过 read_valid 和 read_data 传回。从机 跳转至 读数据状态 (ReadData) ，将读回数据传入 读数据 (RDATA)、读返回请求 (RVALID)；主机此时也转移至 读数据状态 (ReadData)，并将 RREADY 置 1，表明准备好接收读出的数据。
|
||||
|
||||
当主机发现 RVALID 和 RREADY 均为 1 时完成握手，其将读出数据 RDATA 通过 AXI4LiteMasterBundle 的 read_data 传回至 IF，同时将 read_valid 置 1 持续 1 个时钟，表明这次读取操作成功，随后主机重返空闲。
|
||||
|
||||
另一边，当从机发现 RVALID 和 RREADY完成握手时，其也重返空闲状态。
|
||||
|
||||
当主机不在空闲状态时，其将 busy 置 1，“婉拒”期间到来的请求。
|
||||
|
||||
如何进行写操作🚁
|
||||
相比读操作，写操作的流程还需写反馈的握手，若您理解了读操作的机制，写操作应不成问题。
|
||||
|
||||
状态机的具体实现
|
||||
|
||||
我们提供了灵活的测试方法，主从机的状态转换可以不必按照上面所说的一字不差，只需要能达到测试中要求的读写正确、功能正常即可。您可观察测试产生的波形图，从而优化实现以减少读写操作的周期数，甚至跳过某些上述的主从机状态。
|
||||
|
||||
总线上的 MMIO🚁
|
||||
CPU 的内存空间按地址划分为多个部分，分别与不同设备通信。目前的实验代码中，CPU 使用地址的高 3 位以选择设备：b000 映射至内存，b010映射至 UART，b100 映射至定时器。
|
||||
|
||||
BusSwitch.scala 中包含了已实现上述功能的多选交换器，具体的接线在各 Top.scala 中满足了上面说明的映射关系。
|
||||
|
||||
把总线加到流水线上🚁
|
||||
从预备知识里面我们知道了需要有总线仲裁这个模块，来协调总线主机响应来自 CPU 哪个阶段的读写请求信号。
|
||||
|
||||
目前我们的流水线上，无论是三级还是五级，都只存在 取指单元 和 访存单元 之间的冲突。这显然也是一种结构冲突（Structural Hazard），所以可以用 Lab 3 实验中解决冲突的思路：阻塞流水线以保证指令流的执行，即如果访存阶段没有占用总线，取指单元 才能够取指。
|
||||
|
||||
实验任务🚁
|
||||
根据前面的主从设备状态机，实验代码框架已准备好相应寄存器及 IO 接口，您主要关注实现状态机。 若您修改或改进了主从设备状态机，您应简述其逻辑或给出相应图例。
|
||||
|
||||
实验任务：实现 AXI4-Lite 协议主从机
|
||||
|
||||
主从设备的代码位于 src/main/scala/bus/AXI4Lite.scala，请在标有 //lab4 (BUS) 的注释处，实现AXI4Lite主从机的内部逻辑，并：
|
||||
|
||||
通过 src\test\scala\riscv 下的 BusTest.scala，和三级、五级流水线下的 CPUTest.scala 中的测试
|
||||
查看 BusTest 中 FunctionalTest 输出的读写事务消耗了多少个周期
|
||||
查看 CPUTest 中 Fibonacci 和 Quicksort 输出的消耗时钟周期
|
||||
如何检测自己实现的 AXI4-Lite 主从机正确性
|
||||
|
||||
上一版的测试代码要求严格按照给定状态机实现，这一版提供了允许自由实现 AXI4-Lite 协议的测试，并加入测量读写事务耗时的功能。
|
||||
|
||||
若您发现代码无法通过测试，可以查看 BusTest.scala 中 FunctionalTest 产生的波形图，并查看相应通道的信号，来了解自己实现能否完成最基本的读和写操作。该方法也可助您改进实现，减少读写操作的周期数。
|
||||
|
||||
实验报告🚁
|
||||
简述您的 AXI4-Lite 主从机实现逻辑。如果有，描述您通过什么方法改进了实现及性能提升。
|
||||
简要概括BusTest中测试的原理，以及测试用例的执行结果。
|
||||
【可选】参考硬件调试一节的内容，用硬件波形的方法捕获程序运行结果。分析 Vivado 是否能正确识别并组合 AXI4 总线协议的传输信号以及过程。
|
||||
在完成实验的过程中，遇到的关于实验指导不明确或者其他问题，或者改进的建议。
|
||||
更多关于总线的知识🚁
|
||||
实际上把总线加到我们原来的 CPU 上后，会发现 IPC 大幅下降。
|
||||
|
||||
主要原因是总线握手花费了大量的时间。而 AXI4-Lite 协议又是 AXI4 协议的简化版本。为了实现上的简单，所以没有实现突发传输（burst）的功能，所以每次最多读写一个数据总线宽度的数据，即每次都需要重新进行各个读写通道的握手，导致效率很低。
|
||||
|
||||
解决的一个办法就是加缓存。根据局部性原理，我们可以为取值单元与内存之间加上指令 Cache（I-cache），为访存单元与内存间加上数据 Cache（D-cache），这样就可以加速数据的存取。
|
||||
|
||||
而这样的实现方案里面 D-cache 和 I-cache 同样是需要通过总线访问内存的。但是由于 Cache 是以 Cache Line 为单位存取的。假设一个 Cache Line 为 128 字节，当我们的总线数据位宽为 4 字节的时候，填充缓存行需要从内存读 128 / 4 = 32 次， 并且这每一次需要重新进行读地址握手、读数据握手。而 AXI4 协议就是在AXI4-Lite的基础上加上了 Burst 的功能，即在读写请求中可以指定传送数据的个数，从指定地址传连续的多个数据给从机， 而读数据握手时，就可以连续获取相应的那么多个数据。这样的协议就是突发传输（burst），为了实现这个协议，主从设备为了握手通信，需要设置更多的寄存器（指定读取数据个数的 RLEN，指示是否为最后一个数据的 RLAST 等），状态机转换也需要更为复杂。
|
||||
|
||||
这样一来我们从两个方面来加速我们的 CPU，一是 Cache，我们不需要通过总线来获取数据；二是实现完整的 AXI4 协议。而从理论上来说，如果实现了 Cache 而没有实现 AXI4 的 burst 机制，加速效果也不会很明显。所以可以先实现 Cache 然后实现 burst 来体会一下。
|
||||
|
||||
What's next?🚁
|
||||
同学们在完成了本实验后，就应该具备根据状态转移图来实现状态机的能力了。如果有兴趣的话，可以尝试一下实现简单的 Cache，然后再实现 burst。包括后面希望实现 MMU，最简单的实现也可以用状态机来实现。所以，你可以放开手脚在 YatCPU 的基础上探索了（当然你也可以自己从头实现）。
|
||||
|
||||
实现好总线模块的逻辑后，你可以尝试给 Lab 3 的基础上或者是给 Lab 2 的 CPU 接上总线（现有的 YatCPU 的五阶段流水线+总线代码里面的一些逻辑问题在 Lab 3 实验代码中修复了，但是还没有合并到主仓库，Lab 4 用的还是主仓库现有的代码）
|
||||
|
||||
此外同学们也可以思考如何做CPU设计架构的优化，比如现在的 CPU 只有 ID 和 MemoryAccess 阶段对总线有需求，所以总线仲裁比较简单（集成在 CPU.scala 里了）。但是如果后面再加上 MMU，那么 CPU 的总线主机模块应该由哪个模块使用，这部分逻辑就会变得更复杂点，而这部分逻辑其实是可以单独拿出来实现的。
|
||||
Reference in New Issue
Block a user