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https://github.com/handsomezhuzhu/2025-yatcpu.git
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38 lines
1.2 KiB
Scala
38 lines
1.2 KiB
Scala
// Copyright 2022 Canbin Huang
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package riscv.core
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import chisel3._
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import chisel3.util._
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import riscv.Parameters
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class WriteBack extends Module {
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val io = IO(new Bundle() {
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val instruction_address = Input(UInt(Parameters.AddrWidth))
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val alu_result = Input(UInt(Parameters.DataWidth))
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val memory_read_data = Input(UInt(Parameters.DataWidth))
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val regs_write_source = Input(UInt(2.W))
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val regs_write_data = Output(UInt(Parameters.DataWidth))
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})
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io.regs_write_data := MuxLookup(
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io.regs_write_source,
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io.alu_result,
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IndexedSeq(
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RegWriteSource.Memory -> io.memory_read_data,
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RegWriteSource.NextInstructionAddress -> (io.instruction_address + 4.U)
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)
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)
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}
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