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https://github.com/handsomezhuzhu/2025-yatcpu.git
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56 lines
1.5 KiB
Scala
56 lines
1.5 KiB
Scala
// Copyright 2021 Howard Lau
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package riscv.core
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import chisel3._
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import riscv.Parameters
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object ProgramCounter {
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val EntryAddress = Parameters.EntryAddress
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}
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class InstructionFetch extends Module {
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val io = IO(new Bundle {
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val jump_flag_id = Input(Bool())
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val jump_address_id = Input(UInt(Parameters.AddrWidth))
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val instruction_read_data = Input(UInt(Parameters.DataWidth))
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val instruction_valid = Input(Bool())
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val instruction_address = Output(UInt(Parameters.AddrWidth))
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val instruction = Output(UInt(Parameters.InstructionWidth))
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})
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val pc = RegInit(ProgramCounter.EntryAddress)
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when(io.instruction_valid) {
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io.instruction := io.instruction_read_data
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// lab1(InstructionFetch)
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when(io.jump_flag_id) {
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pc := io.jump_address_id
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}.otherwise {
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pc := pc + 4.U
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}
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// la1(InstructionFetch) end
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}.otherwise{
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pc := pc
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io.instruction := 0x00000013.U
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}
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io.instruction_address := pc
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}
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