mirror of
https://github.com/handsomezhuzhu/2025-yatcpu.git
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107 lines
3.8 KiB
Scala
107 lines
3.8 KiB
Scala
// Copyright 2022 Canbin Huang
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package riscv.core
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import chisel3._
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import chisel3.util._
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import peripheral.RAMBundle
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import riscv.Parameters
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class MemoryAccess extends Module {
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val io = IO(new Bundle() {
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val alu_result = Input(UInt(Parameters.DataWidth))
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val reg2_data = Input(UInt(Parameters.DataWidth))
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val memory_read_enable = Input(Bool())
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val memory_write_enable = Input(Bool())
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val funct3 = Input(UInt(3.W))
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val wb_memory_read_data = Output(UInt(Parameters.DataWidth))
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val memory_bundle = Flipped(new RAMBundle)
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})
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val mem_address_index = io.alu_result(log2Up(Parameters.WordSize) - 1, 0).asUInt
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io.memory_bundle.write_enable := false.B
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io.memory_bundle.write_data := 0.U
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io.memory_bundle.address := io.alu_result
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io.memory_bundle.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B))
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io.wb_memory_read_data := 0.U
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when(io.memory_read_enable) {
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val data = io.memory_bundle.read_data
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io.wb_memory_read_data := MuxLookup(
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io.funct3,
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0.U,
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IndexedSeq(
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InstructionsTypeL.lb -> MuxLookup(
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mem_address_index,
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Cat(Fill(24, data(31)), data(31, 24)),
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IndexedSeq(
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0.U -> Cat(Fill(24, data(7)), data(7, 0)),
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1.U -> Cat(Fill(24, data(15)), data(15, 8)),
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2.U -> Cat(Fill(24, data(23)), data(23, 16))
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)
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),
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InstructionsTypeL.lbu -> MuxLookup(
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mem_address_index,
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Cat(Fill(24, 0.U), data(31, 24)),
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IndexedSeq(
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0.U -> Cat(Fill(24, 0.U), data(7, 0)),
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1.U -> Cat(Fill(24, 0.U), data(15, 8)),
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2.U -> Cat(Fill(24, 0.U), data(23, 16))
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)
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),
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InstructionsTypeL.lh -> Mux(
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mem_address_index === 0.U,
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Cat(Fill(16, data(15)), data(15, 0)),
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Cat(Fill(16, data(31)), data(31, 16))
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),
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InstructionsTypeL.lhu -> Mux(
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mem_address_index === 0.U,
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Cat(Fill(16, 0.U), data(15, 0)),
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Cat(Fill(16, 0.U), data(31, 16))
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),
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InstructionsTypeL.lw -> data
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)
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)
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}.elsewhen(io.memory_write_enable) {
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io.memory_bundle.write_data := io.reg2_data
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io.memory_bundle.write_enable := true.B
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io.memory_bundle.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B))
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when(io.funct3 === InstructionsTypeS.sb) {
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io.memory_bundle.write_strobe(mem_address_index) := true.B
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io.memory_bundle.write_data := io.reg2_data(Parameters.ByteBits, 0) << (mem_address_index << log2Up(Parameters.ByteBits).U)
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}.elsewhen(io.funct3 === InstructionsTypeS.sh) {
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when(mem_address_index === 0.U) {
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for (i <- 0 until Parameters.WordSize / 2) {
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io.memory_bundle.write_strobe(i) := true.B
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}
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io.memory_bundle.write_data := io.reg2_data(Parameters.WordSize / 2 * Parameters.ByteBits, 0)
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}.otherwise {
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for (i <- Parameters.WordSize / 2 until Parameters.WordSize) {
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io.memory_bundle.write_strobe(i) := true.B
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}
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io.memory_bundle.write_data := io.reg2_data(Parameters.WordSize / 2 * Parameters.ByteBits, 0) << (Parameters
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.WordSize / 2 * Parameters.ByteBits)
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}
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}.elsewhen(io.funct3 === InstructionsTypeS.sw) {
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for (i <- 0 until Parameters.WordSize) {
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io.memory_bundle.write_strobe(i) := true.B
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}
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}
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}
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}
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