7 Commits

Author	SHA1	Message	Date
PurplePower	b9865cd612	Lab3 pipelined CPU renewed ... - added tutorial - fix ID reg addr invalid in certain types of instructions - renamed some variables for better understanding	2025-08-14 16:55:53 +08:00
PurplePower	ddb70fa967	Fixing Z710 frequency TNS too large ... - now Z7-10 vivado project no longer copy files to local folder, so vivado can auto update it in generate_bitstream.tcl - Z7-10 clock freq is divided by 5 from 125MHz to 25MHz in clock_control.v - adds Zynq7000 v1.3 for lab2	2024-11-18 22:30:07 +08:00
PurplePower	28380be03b	fixex typo in clock_control.v	2024-11-18 17:37:50 +08:00
PurplePower	3e3c8ba6c0	board updates and fixes ... - now VCD is written in all tests by default, turn it on/off in TestAnnotations.scala - updated cmakelists.txt - added board program scripts and sources for Zynq 7000 v1.3 2024/02 board, lab1 only currently	2024-11-18 10:50:45 +08:00
PurplePower	844cb062c2	Deleted useless verilog files	2023-12-26 01:18:54 +08:00
TOKISAKIX\21168	d7c8c1b030	finished lab1	2023-12-12 22:14:02 +08:00
TOKISAKIX\21168	910ee11168	init repo	2023-12-11 21:50:22 +08:00