Commit Graph

4 Commits

Author SHA1 Message Date
PurplePower
3e3c8ba6c0 board updates and fixes
- now VCD is written in all tests by default, turn it on/off in TestAnnotations.scala
- updated cmakelists.txt
- added board program scripts and sources for Zynq 7000 v1.3 2024/02 board, lab1 only currently
2024-11-18 10:50:45 +08:00
PurplePower
844cb062c2 Deleted useless verilog files 2023-12-26 01:18:54 +08:00
TOKISAKIX\21168
d7c8c1b030 finished lab1 2023-12-12 22:14:02 +08:00
TOKISAKIX\21168
910ee11168 init repo 2023-12-11 21:50:22 +08:00