update clock_control.v for lab4 Z710

2026-02-20 20:10:14 +00:00 · 2024-11-19 01:17:53 +08:00
parent 3abdb32f47
commit e4a4c6bf20
1 changed files with 3 additions and 3 deletions
--- a/lab4/verilog/z710/clock_control.v
+++ b/lab4/verilog/z710/clock_control.v
@@ -21,9 +21,9 @@
 module clock_control(
-    input clk_in,
+    input clock_in,
    input enable_clk,
-    output clk_out
+    output reg clock_out
    );
-    assign clk_out = clk_in & enable_clk;
+    assign clock_out = clock_in & enable_clk;
 endmodule