From e4a4c6bf20c67ed553055a9bddb2717019c94667 Mon Sep 17 00:00:00 2001
From: PurplePower <60787289+PurplePower@users.noreply.github.com>
Date: Tue, 19 Nov 2024 01:17:53 +0800
Subject: [PATCH] update clock_control.v for lab4 Z710

---
 lab4/verilog/z710/clock_control.v | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/lab4/verilog/z710/clock_control.v b/lab4/verilog/z710/clock_control.v
index f4e882d..873ee85 100644
--- a/lab4/verilog/z710/clock_control.v
+++ b/lab4/verilog/z710/clock_control.v
@@ -21,9 +21,9 @@
 
 
 module clock_control(
-    input clk_in,
+    input clock_in,
     input enable_clk,
-    output clk_out
+    output reg clock_out
     );
-    assign clk_out = clk_in & enable_clk;
+    assign clock_out = clock_in & enable_clk;
 endmodule