diff --git a/lab4/verilog/z710/clock_control.v b/lab4/verilog/z710/clock_control.v
index f4e882d..873ee85 100644
--- a/lab4/verilog/z710/clock_control.v
+++ b/lab4/verilog/z710/clock_control.v
@@ -21,9 +21,9 @@
 
 
 module clock_control(
-    input clk_in,
+    input clock_in,
     input enable_clk,
-    output clk_out
+    output reg clock_out
     );
-    assign clk_out = clk_in & enable_clk;
+    assign clock_out = clock_in & enable_clk;
 endmodule