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实验一的执行组合成 CPU

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handsomezhuzhu
2025-10-09 19:51:07 +08:00
parent b7578fdc84
commit dec22fa2cd
1 changed files with 7 additions and 0 deletions
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7
lab1/src/main/scala/riscv/core/CPU.scala
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@@ -50,6 +50,13 @@ class CPU extends Module {
// lab1(cpu)
ex.io.instruction := inst_fetch.io.instruction
ex.io.instruction_address := inst_fetch.io.instruction_address
ex.io.reg1_data := regs.io.read_data1
ex.io.reg2_data := regs.io.read_data2
ex.io.immediate := id.io.ex_immediate
ex.io.aluop1_source := id.io.ex_aluop1_source
ex.io.aluop2_source := id.io.ex_aluop2_source