From dec22fa2cdab671451b9c65aa28dee235f8ef3ba Mon Sep 17 00:00:00 2001
From: handsomezhuzhu <2658601135@qq.com>
Date: Thu, 9 Oct 2025 19:51:07 +0800
Subject: [PATCH] =?UTF-8?q?=E5=AE=9E=E9=AA=8C=E4=B8=80=E7=9A=84=E6=89=A7?=
 =?UTF-8?q?=E8=A1=8C=E7=BB=84=E5=90=88=E6=88=90=20CPU?=
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---
 lab1/src/main/scala/riscv/core/CPU.scala | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/lab1/src/main/scala/riscv/core/CPU.scala b/lab1/src/main/scala/riscv/core/CPU.scala
index 5d16bfc..094229d 100644
--- a/lab1/src/main/scala/riscv/core/CPU.scala
+++ b/lab1/src/main/scala/riscv/core/CPU.scala
@@ -50,6 +50,13 @@ class CPU extends Module {
 
   // lab1(cpu)
 
+  ex.io.instruction := inst_fetch.io.instruction
+  ex.io.instruction_address := inst_fetch.io.instruction_address
+  ex.io.reg1_data := regs.io.read_data1
+  ex.io.reg2_data := regs.io.read_data2
+  ex.io.immediate := id.io.ex_immediate
+  ex.io.aluop1_source := id.io.ex_aluop1_source
+  ex.io.aluop2_source := id.io.ex_aluop2_source