init repo

2026-02-20 20:10:14 +00:00 · 2023-12-11 21:50:22 +08:00
commit 910ee11168
449 changed files with 41705 additions and 0 deletions
--- a/lab1/src/main/resources/fibonacci.asmbin
+++ b/lab1/src/main/resources/fibonacci.asmbin
--- a/lab1/src/main/resources/hello.asmbin
+++ b/lab1/src/main/resources/hello.asmbin
--- a/lab1/src/main/resources/litenes.asmbin
+++ b/lab1/src/main/resources/litenes.asmbin
--- a/lab1/src/main/resources/mmio.asmbin
+++ b/lab1/src/main/resources/mmio.asmbin
--- a/lab1/src/main/resources/quicksort.asmbin
+++ b/lab1/src/main/resources/quicksort.asmbin
--- a/lab1/src/main/resources/sb.asmbin
+++ b/lab1/src/main/resources/sb.asmbin
--- a/lab1/src/main/resources/tetris.asmbin
+++ b/lab1/src/main/resources/tetris.asmbin
--- a/lab1/src/main/resources/vga_font_8x16.bmp
+++ b/lab1/src/main/resources/vga_font_8x16.bmp
--- a/lab1/src/main/scala/board/basys3/BCD2Segments.scala
+++ b/lab1/src/main/scala/board/basys3/BCD2Segments.scala
@@ -0,0 +1,54 @@
+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package board.basys3
+
+import chisel3._
+import chisel3.util._
+
+class BCD2Segments extends Module {
+  val io = IO(new Bundle {
+    val bcd = Input(UInt(4.W))
+    val segs = Output(UInt(8.W))
+  })
+
+  val bcd = io.bcd
+  val segs = Wire(UInt(8.W))
+
+  segs := MuxLookup(
+    bcd,
+    0xFF.U,
+    IndexedSeq(
+      0.U -> "b10000001".U,
+      1.U -> "b11001111".U,
+      2.U -> "b10010010".U,
+      3.U -> "b10000110".U,
+      4.U -> "b11001100".U,
+      5.U -> "b10100100".U,
+      6.U -> "b10100000".U,
+      7.U -> "b10001111".U,
+      8.U -> "b10000000".U,
+      9.U -> "b10000100".U,
+      10.U -> "b00001000".U,
+      11.U -> "b01100000".U,
+      12.U -> "b00110001".U,
+      13.U -> "b01000010".U,
+      14.U -> "b00110000".U,
+      15.U -> "b00111000".U,
+    )
+  )
+
+  io.segs := segs
+}
+
--- a/lab1/src/main/scala/board/basys3/OnboardDigitDisplay.scala
+++ b/lab1/src/main/scala/board/basys3/OnboardDigitDisplay.scala
@@ -0,0 +1,32 @@
+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package board.basys3
+
+import chisel3._
+
+class OnboardDigitDisplay extends Module {
+  val io = IO(new Bundle {
+    val digit_mask = Output(UInt(4.W))
+  })
+
+  val counter = RegInit(UInt(16.W), 0.U)
+  val digit_mask = RegInit(UInt(4.W), "b0111".U)
+
+  counter := counter + 1.U
+  when(counter === 0.U) {
+    digit_mask := (digit_mask << 1.U).asUInt + digit_mask(3)
+  }
+  io.digit_mask := digit_mask
+}
--- a/lab1/src/main/scala/board/basys3/SYSULogo.scala
+++ b/lab1/src/main/scala/board/basys3/SYSULogo.scala
@@ -0,0 +1,34 @@
+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package board.basys3
+
+import chisel3._
+import chisel3.util._
+
+class SYSULogo extends Module {
+  val io = IO(new Bundle {
+    val digit_mask = Input(UInt(4.W))
+    val segs = Output(UInt(8.W))
+  })
+
+  io.segs := MuxLookup(
+    io.digit_mask,
+    "b00100100".U, // "b0111".U, "b1101".U -> S
+    IndexedSeq(
+      "b1011".U -> "b01000100".U, // Y
+      "b1110".U -> "b01000001".U, // U
+    )
+  )
+}
--- a/lab1/src/main/scala/board/basys3/SegmentMux.scala
+++ b/lab1/src/main/scala/board/basys3/SegmentMux.scala
@@ -0,0 +1,42 @@
+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package board.basys3
+
+import chisel3._
+import chisel3.util._
+
+class SegmentMux extends Module {
+  val io = IO(new Bundle {
+    val digit_mask = Input(UInt(4.W))
+    val numbers = Input(UInt(16.W))
+    val segs = Output(UInt(8.W))
+  })
+
+
+  val digit = RegInit(UInt(4.W), 0.U)
+  val bcd2segs = Module(new BCD2Segments)
+
+  bcd2segs.io.bcd := digit
+  io.segs := bcd2segs.io.segs
+  digit := MuxLookup(
+    io.digit_mask,
+    io.numbers(3, 0), // "b1110".U
+    IndexedSeq(
+      "b1101".U -> io.numbers(7, 4),
+      "b1011".U -> io.numbers(11, 8),
+      "b0111".U -> io.numbers(15, 12)
+    )
+  )
+}
--- a/lab1/src/main/scala/board/basys3/Top.scala
+++ b/lab1/src/main/scala/board/basys3/Top.scala
@@ -0,0 +1,123 @@
+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package board.basys3
+
+import chisel3._
+import chisel3.experimental.ChiselEnum
+import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
+import chisel3.util._
+import peripheral.{CharacterDisplay, Dummy, InstructionROM, Memory, ROMLoader, VGADisplay}
+import riscv._
+import riscv.core.{CPU, ProgramCounter}
+
+object BootStates extends ChiselEnum {
+  val Init, Loading, Finished = Value
+}
+
+class Top extends Module {
+  val binaryFilename = "tetris.asmbin"
+  val io = IO(new Bundle {
+    val switch = Input(UInt(16.W))
+
+    val segs = Output(UInt(8.W))
+    val digit_mask = Output(UInt(4.W))
+
+    val hsync = Output(Bool())
+    val vsync = Output(Bool())
+    val rgb = Output(UInt(12.W))
+    val led = Output(UInt(16.W))
+
+  })
+  val vga_display = Module(new VGADisplay)
+  val display = Module(new CharacterDisplay)
+
+  val mem = Module(new Memory(Parameters.MemorySizeInWords))
+  val dummy = Module(new Dummy)
+
+  display.io.bundle <> dummy.io.bundle
+  mem.io.bundle <> dummy.io.bundle
+  mem.io.debug_read_address := 0.U
+
+  val instruction_rom = Module(new InstructionROM(binaryFilename))
+  val rom_loader = Module(new ROMLoader(instruction_rom.capacity))
+
+  rom_loader.io.rom_data := instruction_rom.io.data
+  rom_loader.io.load_address := Parameters.EntryAddress
+  instruction_rom.io.address := rom_loader.io.rom_address
+
+  val CPU_clkdiv = RegInit(UInt(2.W), 0.U)
+  val CPU_tick = Wire(Bool())
+  val CPU_next = Wire(UInt(2.W))
+  CPU_next := Mux(CPU_clkdiv === 3.U, 0.U, CPU_clkdiv + 1.U)
+  CPU_tick := CPU_clkdiv === 0.U
+  CPU_clkdiv := CPU_next
+
+  withClock(CPU_tick.asClock) {
+    val cpu = Module(new CPU)
+    cpu.io.debug_read_address := 0.U
+    cpu.io.instruction_valid := rom_loader.io.load_finished
+    mem.io.instruction_address := cpu.io.instruction_address
+    cpu.io.instruction := mem.io.instruction
+
+    when(!rom_loader.io.load_finished) {
+      rom_loader.io.bundle <> mem.io.bundle
+      cpu.io.memory_bundle.read_data := 0.U
+    }.otherwise {
+      rom_loader.io.bundle.read_data := 0.U
+      when(cpu.io.deviceSelect === 1.U) {
+        cpu.io.memory_bundle <> display.io.bundle
+      }.otherwise {
+        cpu.io.memory_bundle <> mem.io.bundle
+      }
+    }
+  }
+  io.hsync := vga_display.io.hsync
+  io.vsync := vga_display.io.vsync
+
+  display.io.x := vga_display.io.x
+  display.io.y := vga_display.io.y
+  display.io.video_on := vga_display.io.video_on
+
+  io.rgb := display.io.rgb
+
+  mem.io.debug_read_address := io.switch(15, 1).asUInt << 2
+  io.led := Mux(
+    io.switch(0),
+    mem.io.debug_read_data(31, 16).asUInt,
+    mem.io.debug_read_data(15, 0).asUInt,
+  )
+
+  val onboard_display = Module(new OnboardDigitDisplay)
+  io.digit_mask := onboard_display.io.digit_mask
+
+  val sysu_logo = Module(new SYSULogo)
+  sysu_logo.io.digit_mask := io.digit_mask
+
+  val seg_mux = Module(new SegmentMux)
+  seg_mux.io.digit_mask := io.digit_mask
+  seg_mux.io.numbers := io.led
+
+  io.segs := MuxLookup(
+    io.switch,
+    seg_mux.io.segs,
+    IndexedSeq(
+      0.U -> sysu_logo.io.segs
+    )
+  )
+}
+
+object VerilogGenerator extends App {
+  (new ChiselStage).execute(Array("-X", "verilog", "-td", "verilog/basys3"), Seq(ChiselGeneratorAnnotation(() => new Top)))
+}
--- a/lab1/src/main/scala/board/pynq/Top.scala
+++ b/lab1/src/main/scala/board/pynq/Top.scala
@@ -0,0 +1,93 @@
+// Copyright 2022 Canbin Huang
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package board.pynq
+
+import chisel3._
+import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
+import peripheral._
+import riscv.Parameters
+import riscv.core.{CPU, ProgramCounter}
+
+class Top extends Module {
+  val binaryFilename = "hello.asmbin"
+  val io = IO(new Bundle() {
+    val hdmi_clk_n = Output(Bool())
+    val hdmi_clk_p = Output(Bool())
+    val hdmi_data_n = Output(UInt(3.W))
+    val hdmi_data_p = Output(UInt(3.W))
+    val hdmi_hpdn = Output(Bool())
+
+    val led = Output(UInt(4.W))
+  })
+  val hdmi_display = Module(new HDMIDisplay)
+  val display = Module(new CharacterDisplay)
+  val mem = Module(new Memory(Parameters.MemorySizeInWords))
+  val dummy = Module(new Dummy)
+
+  display.io.bundle <> dummy.io.bundle
+  mem.io.bundle <> dummy.io.bundle
+  mem.io.debug_read_address := 0.U
+
+  val instruction_rom = Module(new InstructionROM(binaryFilename))
+  val rom_loader = Module(new ROMLoader(instruction_rom.capacity))
+
+  rom_loader.io.rom_data := instruction_rom.io.data
+  rom_loader.io.load_address := Parameters.EntryAddress
+  instruction_rom.io.address := rom_loader.io.rom_address
+
+  val CPU_clkdiv = RegInit(UInt(2.W),0.U)
+  val CPU_tick = Wire(Bool())
+  val CPU_next = Wire(UInt(2.W))
+  CPU_next := Mux(CPU_clkdiv === 3.U, 0.U, CPU_clkdiv + 1.U)
+  CPU_tick := CPU_clkdiv === 0.U
+  CPU_clkdiv := CPU_next
+
+  withClock(CPU_tick.asClock) {
+    val cpu = Module(new CPU)
+    cpu.io.debug_read_address := 0.U
+    cpu.io.instruction_valid := rom_loader.io.load_finished
+    mem.io.instruction_address := cpu.io.instruction_address
+    cpu.io.instruction := mem.io.instruction
+
+    when(!rom_loader.io.load_finished) {
+      rom_loader.io.bundle <> mem.io.bundle
+      cpu.io.memory_bundle.read_data := 0.U
+    }.otherwise {
+      rom_loader.io.bundle.read_data := 0.U
+      when(cpu.io.deviceSelect === 1.U) {
+        cpu.io.memory_bundle <> display.io.bundle
+      }.otherwise {
+        cpu.io.memory_bundle <> mem.io.bundle
+      }
+    }
+  }
+
+  io.led := 15.U(4.W)
+
+  display.io.x := hdmi_display.io.x
+  display.io.y := hdmi_display.io.y
+  display.io.video_on := hdmi_display.io.video_on
+  hdmi_display.io.rgb := display.io.rgb
+
+  io.hdmi_hpdn := 1.U
+  io.hdmi_data_n := hdmi_display.io.TMDSdata_n
+  io.hdmi_data_p := hdmi_display.io.TMDSdata_p
+  io.hdmi_clk_n := hdmi_display.io.TMDSclk_n
+  io.hdmi_clk_p := hdmi_display.io.TMDSclk_p
+}
+
+object VerilogGenerator extends App {
+  (new ChiselStage).execute(Array("-X", "verilog", "-td", "verilog/pynq"), Seq(ChiselGeneratorAnnotation(() => new Top)))
+}
--- a/lab1/src/main/scala/board/verilator/Top.scala
+++ b/lab1/src/main/scala/board/verilator/Top.scala
@@ -0,0 +1,43 @@
+// Copyright 2022 Canbin Huang
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package board.verilator
+
+import chisel3._
+import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
+import peripheral._
+import riscv.{CPUBundle, Parameters}
+import riscv.core.CPU
+
+class Top extends Module {
+  val io = IO(new CPUBundle)
+
+  val cpu = Module(new CPU)
+
+  io.deviceSelect := 0.U
+  cpu.io.debug_read_address := io.debug_read_address
+  io.debug_read_data := cpu.io.debug_read_data
+
+  io.memory_bundle <> cpu.io.memory_bundle
+  io.instruction_address := cpu.io.instruction_address
+  cpu.io.instruction := io.instruction
+
+  cpu.io.instruction_valid := io.instruction_valid
+
+}
+
+object VerilogGenerator extends App {
+  (new ChiselStage).execute(Array("-X", "verilog", "-td", "verilog/verilator"), Seq(ChiselGeneratorAnnotation(() =>
+    new Top())))
+}
--- a/lab1/src/main/scala/peripheral/CharacterDisplay.scala
+++ b/lab1/src/main/scala/peripheral/CharacterDisplay.scala
@@ -0,0 +1,84 @@
+// Copyright 2022 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package peripheral
+
+import chisel3.util.{MuxLookup, log2Up}
+import chisel3.{Bool, Bundle, Module, Mux, Output, UInt, Wire, _}
+import peripheral.ScreenInfo.{DisplayHorizontal, DisplayVertical}
+import riscv.Parameters
+
+object GlyphInfo {
+  val glyphWidth = 8
+  val glyphHeight = 16
+  // ASCII printable characters start from here
+  val spaceIndex = 1
+}
+
+object ScreenInfo {
+  val DisplayHorizontal = 640
+  val DisplayVertical = 480
+}
+
+object CharacterBufferInfo {
+  val CharCols = DisplayHorizontal / GlyphInfo.glyphWidth
+  val CharRows = DisplayVertical / GlyphInfo.glyphHeight
+  val Chars = CharCols * CharRows
+}
+
+class CharacterDisplay extends Module {
+  val io = IO(new Bundle() {
+    val bundle = new RAMBundle()
+
+    val x = Input(UInt(16.W))
+    val y = Input(UInt(16.W))
+    val video_on = Input(Bool())
+
+    val rgb = Output(UInt(24.W))
+  })
+
+  val mem = Module(new BlockRAM(CharacterBufferInfo.Chars / Parameters.WordSize))
+  mem.io.write_enable := io.bundle.write_enable
+  mem.io.write_data := io.bundle.write_data
+  mem.io.write_address := io.bundle.address
+  mem.io.write_strobe := io.bundle.write_strobe
+  mem.io.read_address := io.bundle.address
+  io.bundle.read_data := mem.io.read_data
+
+
+  val font_rom = Module(new FontROM)
+  val row = (io.y >> log2Up(GlyphInfo.glyphHeight)).asUInt
+  val col = (io.x >> log2Up(GlyphInfo.glyphWidth)).asUInt
+  val char_index = (row * CharacterBufferInfo.CharCols.U) + col
+  val offset = char_index(1, 0)
+  val ch = Wire(UInt(8.W))
+
+  mem.io.debug_read_address := char_index
+  ch := MuxLookup(
+    offset,
+    0.U,
+    IndexedSeq(
+      0.U -> mem.io.debug_read_data(7, 0).asUInt,
+      1.U -> mem.io.debug_read_data(15, 8).asUInt,
+      2.U -> mem.io.debug_read_data(23, 16).asUInt,
+      3.U -> mem.io.debug_read_data(31, 24).asUInt
+    )
+  )
+  font_rom.io.glyph_index := Mux(ch >= 32.U, ch - 31.U, 0.U)
+  font_rom.io.glyph_y := io.y(log2Up(GlyphInfo.glyphHeight) - 1, 0)
+
+  // White if pixel_on and glyph pixel on
+  val glyph_x = io.x(log2Up(GlyphInfo.glyphWidth) - 1, 0)
+  io.rgb := Mux(io.video_on && font_rom.io.glyph_pixel_byte(glyph_x), 0xFFFFFF.U, 0.U)
+}
--- a/lab1/src/main/scala/peripheral/Dummy.scala
+++ b/lab1/src/main/scala/peripheral/Dummy.scala
@@ -0,0 +1,29 @@
+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package peripheral
+
+import chisel3._
+import riscv.Parameters
+
+// A dummy master that never initiates reads or writes
+class Dummy extends Module {
+  val io = IO(new Bundle {
+    val bundle = Flipped(new RAMBundle)
+  })
+  io.bundle.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B))
+  io.bundle.write_data := 0.U
+  io.bundle.write_enable := false.B
+  io.bundle.address := 0.U
+}
--- a/lab1/src/main/scala/peripheral/FontROM.scala
+++ b/lab1/src/main/scala/peripheral/FontROM.scala
@@ -0,0 +1,64 @@
+package peripheral
+
+import chisel3.experimental.{ChiselAnnotation, annotate}
+import chisel3.util.experimental.loadMemoryFromFileInline
+import chisel3.{Bundle, Input, Module, Output, SyncReadMem, UInt, _}
+import firrtl.annotations.MemorySynthInit
+
+import java.io.FileWriter
+import java.nio.file.Paths
+import javax.imageio.ImageIO
+
+class FontROM(fontBitmapFilename: String = "vga_font_8x16.bmp") extends Module {
+  val glyphWidth = GlyphInfo.glyphWidth
+  val glyphHeight = GlyphInfo.glyphHeight
+
+  val io = IO(new Bundle {
+    val glyph_index = Input(UInt(7.W))
+    val glyph_y = Input(UInt(4.W))
+
+    val glyph_pixel_byte = Output(UInt(8.W))
+  })
+
+  annotate(new ChiselAnnotation {
+    override def toFirrtl =
+      MemorySynthInit
+  })
+
+  val (hexTxtPath, glyphCount) = readFontBitmap()
+  val mem = SyncReadMem(glyphCount, UInt(8.W))
+  loadMemoryFromFileInline(mem, hexTxtPath.toString.replaceAll("\\\\", "/"))
+  io.glyph_pixel_byte := mem.read(io.glyph_index * GlyphInfo.glyphHeight.U + io.glyph_y, true.B)
+
+  def readFontBitmap() = {
+    val inputStream = getClass.getClassLoader.getResourceAsStream(fontBitmapFilename)
+    val image = ImageIO.read(inputStream)
+
+    val glyphColumns = image.getWidth() / glyphWidth
+    val glyphRows = image.getHeight / glyphHeight
+    val glyphCount = glyphColumns * glyphRows
+    val glyphs = new Array[UInt](glyphCount * GlyphInfo.glyphHeight)
+
+    for (row <- 0 until glyphRows) {
+      for (col <- 0 until glyphColumns) {
+        for (i <- 0 until glyphHeight) {
+          var lineInt = 0
+          for (j <- 0 until glyphWidth) {
+            if (image.getRGB(col * glyphWidth + j, row * glyphHeight + i) != 0xFFFFFFFF) {
+              lineInt |= (1 << j)
+            }
+          }
+          glyphs((row * glyphColumns + col) * GlyphInfo.glyphHeight + i) = lineInt.U(8.W)
+        }
+      }
+    }
+    val currentDir = System.getProperty("user.dir")
+    val hexTxtPath = Paths.get(currentDir, "verilog", f"${fontBitmapFilename}.txt")
+    val writer = new FileWriter(hexTxtPath.toString)
+    for (i <- glyphs.indices) {
+      writer.write(f"@$i%x\n${glyphs(i).litValue}%02x\n")
+    }
+    writer.close()
+    (hexTxtPath, glyphs.length)
+  }
+}
--- a/lab1/src/main/scala/peripheral/HDMIDisplay.scala
+++ b/lab1/src/main/scala/peripheral/HDMIDisplay.scala
@@ -0,0 +1,394 @@
+// Copyright 2022 hrpccs
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package peripheral
+
+import chisel3._
+import chisel3.util._
+
+class HDMISync extends Module {
+  val io = IO(new Bundle {
+    val hsync = Output(Bool())
+    val vsync = Output(Bool())
+    val video_on = Output(Bool())
+    val p_tick = Output(Bool())
+    val f_tick = Output(Bool())
+    val x = Output(UInt(10.W))
+    val y = Output(UInt(10.W))
+    val x_next = Output(UInt(10.W))
+    val y_next = Output(UInt(10.W))
+  })
+
+  val DisplayHorizontal = ScreenInfo.DisplayHorizontal
+  val DisplayVertical = ScreenInfo.DisplayVertical
+
+  val BorderLeft = 48
+  val BorderRight = 16
+  val BorderTop = 10
+  val BorderBottom = 33
+
+  val RetraceHorizontal = 96
+  val RetraceVertical = 2
+
+  val MaxHorizontal = DisplayHorizontal + BorderLeft + BorderRight + RetraceHorizontal - 1
+  val MaxVertical = DisplayVertical + BorderTop + BorderBottom + RetraceVertical - 1
+
+  val RetraceHorizontalStart = DisplayHorizontal + BorderRight
+  val RetraceHorizontalEnd = RetraceHorizontalStart + RetraceHorizontal - 1
+
+  val RetraceVerticalStart = DisplayVertical + BorderBottom
+  val RetraceVerticalEnd = RetraceVerticalStart + RetraceVertical - 1
+
+  val pixel = RegInit(UInt(3.W), 0.U)
+  val pixel_next = Wire(UInt(3.W))
+  val pixel_tick = Wire(Bool())
+
+  val v_count_reg = RegInit(UInt(10.W), 0.U)
+  val h_count_reg = RegInit(UInt(10.W), 0.U)
+
+  val v_count_next = Wire(UInt(10.W))
+  val h_count_next = Wire(UInt(10.W))
+
+  val vsync_reg = RegInit(Bool(), false.B)
+  val hsync_reg = RegInit(Bool(), false.B)
+
+  val vsync_next = Wire(Bool())
+  val hsync_next = Wire(Bool())
+
+  pixel_next := Mux(pixel === 4.U, 0.U, pixel + 1.U)
+  pixel_tick := pixel === 0.U
+
+  h_count_next := Mux(
+    pixel_tick,
+    Mux(h_count_reg === MaxHorizontal.U, 0.U, h_count_reg + 1.U),
+    h_count_reg
+  )
+
+  v_count_next := Mux(
+    pixel_tick && h_count_reg === MaxHorizontal.U,
+    Mux(v_count_reg === MaxVertical.U, 0.U, v_count_reg + 1.U),
+    v_count_reg
+  )
+
+  hsync_next := h_count_reg >= RetraceHorizontalStart.U && h_count_reg <= RetraceHorizontalEnd.U
+  vsync_next := v_count_reg >= RetraceVerticalStart.U && v_count_reg <= RetraceVerticalEnd.U
+
+  pixel := pixel_next
+  hsync_reg := hsync_next
+  vsync_reg := vsync_next
+  v_count_reg := v_count_next
+  h_count_reg := h_count_next
+
+  io.video_on := h_count_reg < DisplayHorizontal.U && v_count_reg < DisplayVertical.U
+  io.hsync := hsync_reg
+  io.vsync := vsync_reg
+  io.x := h_count_reg
+  io.y := v_count_reg
+  io.x_next := h_count_next
+  io.y_next := v_count_next
+  io.p_tick := pixel_tick
+  io.f_tick := io.x === 0.U && io.y === 0.U
+}
+
+class TMDS_encoder extends Module {
+  val io = IO(new Bundle() {
+    val video_data = Input(UInt(8.W)) //r,g,b,8bit
+    val control_data = Input(UInt(2.W))
+    val video_on = Input(Bool())
+    val TMDS = Output(UInt(10.W))
+  })
+  val Nb1s = PopCount(io.video_data)
+  val xored = xorfct(io.video_data)
+  val xnored = xnorfct(io.video_data)
+  val XNOR = (Nb1s > 4.U(4.W)) || (Nb1s === 4.U(4.W) && io.video_data(0) === 0.U)
+  val q_m = RegInit(0.U(9.W))
+  val diffSize = 4
+  val diff = RegInit(0.S(diffSize.W))
+  q_m := Mux(
+    XNOR,
+    xnored,
+    xored
+  )
+  val disparitySize = 4
+  val disparityReg = RegInit(0.S(disparitySize.W))
+  diff := PopCount(q_m).asSInt - 4.S
+  val doutReg = RegInit("b1010101011".U(10.W))
+
+  def xorfct(value: UInt): UInt = {
+    val vin = VecInit(value.asBools)
+    val res = VecInit(511.U.asBools)
+    res(0) := vin(0)
+    for (i <- 1 to 7) {
+      res(i) := res(i - 1) ^ vin(i)
+    }
+    res(8) := 1.U
+    res.asUInt
+  }
+
+  def xnorfct(value: UInt): UInt = {
+    val vin = VecInit(value.asBools)
+    val res = VecInit(511.U.asBools)
+    res(0) := vin(0)
+    for (i <- 1 to 7) {
+      res(i) := !(res(i - 1) ^ vin(i))
+    }
+    res(8) := 0.U
+    res.asUInt
+  }
+
+  when(io.video_on === false.B) {
+    disparityReg := 0.S
+    doutReg := "b1010101011".U(10.W)
+    switch(io.control_data) {
+      is("b00".U(2.W)) {
+        doutReg := "b1101010100".U(10.W)
+      }
+      is("b01".U(2.W)) {
+        doutReg := "b0010101011".U(10.W)
+      }
+      is("b10".U(2.W)) {
+        doutReg := "b0101010100".U(10.W)
+      }
+    }
+  }.otherwise {
+    when(disparityReg === 0.S || diff === 0.S) {
+      when(q_m(8) === false.B) {
+        doutReg := "b10".U(2.W) ## ~q_m(7, 0)
+        disparityReg := disparityReg - diff
+      }.otherwise {
+        doutReg := "b01".U(2.W) ## q_m(7, 0)
+        disparityReg := disparityReg + diff
+      }
+    }.elsewhen((!diff(diffSize - 1) && !disparityReg(disparitySize - 1))
+      || (diff(diffSize - 1) && disparityReg(disparitySize - 1))) {
+      doutReg := 1.U(1.W) ## q_m(8) ## ~q_m(7, 0)
+      when(q_m(8)) {
+        disparityReg := disparityReg + 1.S - diff
+      }.otherwise {
+        disparityReg := disparityReg - diff
+      }
+    }.otherwise {
+      doutReg := 0.U(1.W) ## q_m
+      when(q_m(8)) {
+        disparityReg := disparityReg + diff
+      }.otherwise {
+        disparityReg := disparityReg - 1.S + diff
+      }
+    }
+  }
+
+  io.TMDS := doutReg
+}
+
+class HDMIDisplay extends Module {
+  val io = IO(new Bundle() {
+    val rgb = Input(UInt(24.W))
+    val x = Output(UInt(16.W))
+    val y = Output(UInt(16.W))
+    val x_next = Output(UInt(16.W))
+    val y_next = Output(UInt(16.W))
+    val video_on = Output(Bool())
+
+    val TMDSclk_p = Output(Bool())
+    val TMDSdata_p = Output(UInt(3.W))
+    val TMDSclk_n = Output(Bool())
+    val TMDSdata_n = Output(UInt(3.W))
+  })
+  val rgb = io.rgb
+  val pixel_clk = Wire(Bool())
+  val hsync = Wire(Bool())
+  val vsync = Wire(Bool())
+  val sync = Module(new HDMISync)
+
+  io.x := sync.io.x
+  io.y := sync.io.y
+  io.x_next := sync.io.x_next
+  io.y_next := sync.io.y_next
+  io.video_on := sync.io.video_on
+
+  hsync := sync.io.hsync
+  vsync := sync.io.vsync
+  pixel_clk := sync.io.p_tick
+
+  // TMDS_PLLVR is a vivado IP core, check it in /verilog/pynq/TMDS_PLLVR.v
+  val serial_clk = Wire(Clock())
+  val pll_lock = Wire(Bool())
+  val tmdspll = Module(new TMDS_PLLVR)
+  val rst = Wire(Reset())
+  tmdspll.io.clkin := pixel_clk.asClock
+  serial_clk := tmdspll.io.clkout
+  pll_lock := tmdspll.io.lock
+  tmdspll.io.reset := reset
+  rst := ~pll_lock
+
+  val tmds = Wire(UInt(3.W))
+  val tmds_clk = Wire(Bool())
+  withClockAndReset(pixel_clk.asClock, rst) {
+    val tmds_channel1 = Wire(UInt(10.W))
+    val tmds_channel2 = Wire(UInt(10.W))
+    val tmds_channel0 = Wire(UInt(10.W))
+
+    val tmds_green = Module(new TMDS_encoder)
+    val tmds_red = Module(new TMDS_encoder)
+    val tmds_blue = Module(new TMDS_encoder)
+
+    tmds_red.io.video_on := sync.io.video_on
+    tmds_blue.io.video_on := sync.io.video_on
+    tmds_green.io.video_on := sync.io.video_on
+
+    tmds_blue.io.control_data := sync.io.vsync ## sync.io.hsync
+    tmds_green.io.control_data := 0.U
+    tmds_red.io.control_data := 0.U
+
+    tmds_red.io.video_data := rgb(23, 16)
+    tmds_blue.io.video_data := rgb(7, 0)
+    tmds_green.io.video_data := rgb(15, 8)
+
+    tmds_channel0 := tmds_blue.io.TMDS
+    tmds_channel1 := tmds_green.io.TMDS
+    tmds_channel2 := tmds_red.io.TMDS
+
+    val serdesBlue = Module(new Oser10Module())
+    serdesBlue.io.data := tmds_channel0
+    serdesBlue.io.fclk := serial_clk
+
+    val serdesGreen = Module(new Oser10Module())
+    serdesGreen.io.data := tmds_channel1
+    serdesGreen.io.fclk := serial_clk
+
+    val serdesRed = Module(new Oser10Module())
+    serdesRed.io.data := tmds_channel2
+    serdesRed.io.fclk := serial_clk
+
+    tmds := serdesRed.io.q ## serdesGreen.io.q ## serdesBlue.io.q
+
+    //serdesCLk : 25Mhz ,Why not directly use p_tick?
+    //cause Duty Ratio of p_tick is 10% , while which of serdesCLk is 50%
+    val serdesClk = Module(new Oser10Module())
+    serdesClk.io.data := "b1111100000".U(10.W)
+    serdesClk.io.fclk := serial_clk
+
+    tmds_clk := serdesClk.io.q
+
+    val buffDiffBlue = Module(new OBUFDS)
+    buffDiffBlue.io.I := tmds(0)
+    val buffDiffGreen = Module(new OBUFDS)
+    buffDiffGreen.io.I := tmds(1)
+    val buffDiffRed = Module(new OBUFDS)
+    buffDiffRed.io.I := tmds(2)
+    val buffDiffClk = Module(new OBUFDS)
+    buffDiffClk.io.I := tmds_clk
+
+    io.TMDSclk_p := buffDiffClk.io.O
+    io.TMDSclk_n := buffDiffClk.io.OB
+    io.TMDSdata_p := buffDiffRed.io.O ## buffDiffGreen.io.O ## buffDiffBlue.io.O
+    io.TMDSdata_n := buffDiffRed.io.OB ## buffDiffGreen.io.OB ## buffDiffBlue.io.OB
+  }
+}
+
+//----------------------------------------
+//PLL frequency multiplier using BlackBox
+class TMDS_PLLVR extends BlackBox {
+  val io = IO(new Bundle {
+    val clkin = Input(Clock())
+    val reset = Input(Reset())
+    val clkout = Output(Clock())
+    val clkoutd = Output(Clock())
+    val lock = Output(Bool())
+  })
+}
+
+/* OSER10 : serializer 10:1*/
+class OSER10 extends Module {
+  val io = IO(new Bundle {
+    val Q = Output(Bool()) // OSER10 data output signal
+    val D0 = Input(Bool())
+    val D1 = Input(Bool())
+    val D2 = Input(Bool())
+    val D3 = Input(Bool())
+    val D4 = Input(Bool())
+    val D5 = Input(Bool())
+    val D6 = Input(Bool())
+    val D7 = Input(Bool())
+    val D8 = Input(Bool())
+    val D9 = Input(Bool()) //  OSER10 data input signal
+    val PCLK = Input(Clock()) // Primary clock input signal
+    val FCLK = Input(Clock()) // High speed clock input signal
+    val RESET = Input(Reset()) // Asynchronous reset input signal,
+    //active-high.
+  })
+  withClockAndReset(io.FCLK, io.RESET) {
+    val count = RegInit(0.U(4.W))
+    val countnext = Wire(UInt(4.W))
+    io.Q := MuxLookup(
+      count,
+      0.U,
+      IndexedSeq(
+        0.U -> io.D0.asBool,
+        1.U -> io.D1.asBool,
+        2.U -> io.D2.asBool,
+        3.U -> io.D3.asBool,
+        4.U -> io.D4.asBool,
+        5.U -> io.D5.asBool,
+        6.U -> io.D6.asBool,
+        7.U -> io.D7.asBool,
+        8.U -> io.D8.asBool,
+        9.U -> io.D9.asBool
+      )
+    )
+    countnext := Mux(
+      count === 9.U, 0.U, count + 1.U
+    )
+    count := countnext
+  }
+}
+
+class Oser10Module extends Module {
+  val io = IO(new Bundle {
+    val q = Output(Bool())
+    val data = Input(UInt(10.W))
+    val fclk = Input(Clock()) // Fast clock
+  })
+
+  val osr10 = Module(new OSER10())
+  io.q := osr10.io.Q
+  osr10.io.D0 := io.data(0)
+  osr10.io.D1 := io.data(1)
+  osr10.io.D2 := io.data(2)
+  osr10.io.D3 := io.data(3)
+  osr10.io.D4 := io.data(4)
+  osr10.io.D5 := io.data(5)
+  osr10.io.D6 := io.data(6)
+  osr10.io.D7 := io.data(7)
+  osr10.io.D8 := io.data(8)
+  osr10.io.D9 := io.data(9)
+  osr10.io.PCLK := clock
+  osr10.io.FCLK := io.fclk
+  osr10.io.RESET := reset
+}
+
+/* lvds output */
+class OBUFDS extends BlackBox {
+  val io = IO(new Bundle {
+    val O = Output(Bool())
+    val OB = Output(Bool())
+    val I = Input(Bool())
+  })
+}
+//-----------------------------------------
+
+
+//-----------------------------------------
+
+
--- a/lab1/src/main/scala/peripheral/InstructionROM.scala
+++ b/lab1/src/main/scala/peripheral/InstructionROM.scala
@@ -0,0 +1,68 @@
+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package peripheral
+
+import chisel3._
+import chisel3.experimental.{ChiselAnnotation, annotate}
+import chisel3.util.experimental.loadMemoryFromFileInline
+import firrtl.annotations.MemorySynthInit
+import riscv.Parameters
+
+import java.io.FileWriter
+import java.nio.file.{Files, Paths}
+import java.nio.{ByteBuffer, ByteOrder}
+
+class InstructionROM(instructionFilename: String) extends Module {
+  val io = IO(new Bundle {
+    val address = Input(UInt(Parameters.AddrWidth))
+    val data = Output(UInt(Parameters.InstructionWidth))
+  })
+
+  val (instructionsInitFile, capacity) = readAsmBinary(instructionFilename)
+  val mem = Mem(capacity, UInt(Parameters.InstructionWidth))
+  annotate(new ChiselAnnotation {
+    override def toFirrtl =
+      MemorySynthInit
+  })
+  loadMemoryFromFileInline(mem, instructionsInitFile.toString.replaceAll("\\\\", "/"))
+  io.data := mem.read(io.address)
+
+  def readAsmBinary(filename: String) = {
+    val inputStream = if (Files.exists(Paths.get(filename))) {
+      Files.newInputStream(Paths.get(filename))
+    } else {
+      getClass.getClassLoader.getResourceAsStream(filename)
+    }
+    var instructions = new Array[BigInt](0)
+    val arr = new Array[Byte](4)
+    while (inputStream.read(arr) == 4) {
+      val instBuf = ByteBuffer.wrap(arr)
+      instBuf.order(ByteOrder.LITTLE_ENDIAN)
+      val inst = BigInt(instBuf.getInt() & 0xFFFFFFFFL)
+      instructions = instructions :+ inst
+    }
+    instructions = instructions :+ BigInt(0x00000013L)
+    instructions = instructions :+ BigInt(0x00000013L)
+    instructions = instructions :+ BigInt(0x00000013L)
+    val currentDir = System.getProperty("user.dir")
+    val exeTxtPath = Paths.get(currentDir, "verilog", f"${instructionFilename}.txt")
+    val writer = new FileWriter(exeTxtPath.toString)
+    for (i <- instructions.indices) {
+      writer.write(f"@$i%x\n${instructions(i)}%08x\n")
+    }
+    writer.close()
+    (exeTxtPath, instructions.length)
+  }
+}
--- a/lab1/src/main/scala/peripheral/Memory.scala
+++ b/lab1/src/main/scala/peripheral/Memory.scala
@@ -0,0 +1,77 @@
+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package peripheral
+
+import chisel3._
+import chisel3.util._
+import riscv.Parameters
+
+class RAMBundle extends Bundle {
+  val address = Input(UInt(Parameters.AddrWidth))
+  val write_data = Input(UInt(Parameters.DataWidth))
+  val write_enable = Input(Bool())
+  val write_strobe = Input(Vec(Parameters.WordSize, Bool()))
+  val read_data = Output(UInt(Parameters.DataWidth))
+}
+// The purpose of this module is to help the synthesis tool recognize
+// our memory as a Block RAM template
+class BlockRAM(capacity: Int) extends Module {
+  val io = IO(new Bundle {
+    val read_address = Input(UInt(Parameters.AddrWidth))
+    val write_address = Input(UInt(Parameters.AddrWidth))
+    val write_data = Input(UInt(Parameters.DataWidth))
+    val write_enable = Input(Bool())
+    val write_strobe = Input(Vec(Parameters.WordSize, Bool()))
+
+    val debug_read_address = Input(UInt(Parameters.AddrWidth))
+
+    val read_data = Output(UInt(Parameters.DataWidth))
+    val debug_read_data = Output(UInt(Parameters.DataWidth))
+  })
+  val mem = SyncReadMem(capacity, Vec(Parameters.WordSize, UInt(Parameters.ByteWidth)))
+  when(io.write_enable) {
+    val write_data_vec = Wire(Vec(Parameters.WordSize, UInt(Parameters.ByteWidth)))
+    for (i <- 0 until Parameters.WordSize) {
+      write_data_vec(i) := io.write_data((i + 1) * Parameters.ByteBits - 1, i * Parameters.ByteBits)
+    }
+    mem.write((io.write_address >> 2.U).asUInt, write_data_vec, io.write_strobe)
+  }
+  io.read_data := mem.read((io.read_address >> 2.U).asUInt, true.B).asUInt
+  io.debug_read_data := mem.read((io.debug_read_address >> 2.U).asUInt, true.B).asUInt
+}
+
+class Memory(capacity: Int) extends Module {
+  val io = IO(new Bundle {
+    val bundle = new RAMBundle
+
+    val instruction = Output(UInt(Parameters.DataWidth))
+    val instruction_address = Input(UInt(Parameters.AddrWidth))
+
+    val debug_read_address = Input(UInt(Parameters.AddrWidth))
+    val debug_read_data = Output(UInt(Parameters.DataWidth))
+  })
+
+  val mem = SyncReadMem(capacity, Vec(Parameters.WordSize, UInt(Parameters.ByteWidth)))
+  when(io.bundle.write_enable) {
+    val write_data_vec = Wire(Vec(Parameters.WordSize, UInt(Parameters.ByteWidth)))
+    for (i <- 0 until Parameters.WordSize) {
+      write_data_vec(i) := io.bundle.write_data((i + 1) * Parameters.ByteBits - 1, i * Parameters.ByteBits)
+    }
+    mem.write((io.bundle.address >> 2.U).asUInt, write_data_vec, io.bundle.write_strobe)
+  }
+  io.bundle.read_data := mem.read((io.bundle.address >> 2.U).asUInt, true.B).asUInt
+  io.debug_read_data := mem.read((io.debug_read_address >> 2.U).asUInt, true.B).asUInt
+  io.instruction := mem.read((io.instruction_address >> 2.U).asUInt, true.B).asUInt
+}
--- a/lab1/src/main/scala/peripheral/ROMLoader.scala
+++ b/lab1/src/main/scala/peripheral/ROMLoader.scala
@@ -0,0 +1,50 @@
+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package peripheral
+
+import chisel3._
+import riscv.Parameters
+
+class ROMLoader(capacity: Int) extends Module {
+  val io = IO(new Bundle {
+    val bundle = Flipped(new RAMBundle)
+
+    val rom_address = Output(UInt(Parameters.AddrWidth))
+    val rom_data = Input(UInt(Parameters.InstructionWidth))
+
+    val load_address = Input(UInt(Parameters.AddrWidth))
+    val load_finished = Output(Bool())
+  })
+
+  val address = RegInit(0.U(32.W))
+  val valid = RegInit(false.B)
+
+  io.bundle.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B))
+  io.bundle.address := 0.U
+  io.bundle.write_data := 0.U
+  io.bundle.write_enable := false.B
+  when(address <= (capacity - 1).U) {
+    io.bundle.write_enable := true.B
+    io.bundle.write_data := io.rom_data
+    io.bundle.address := (address << 2.U).asUInt + io.load_address
+    io.bundle.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(true.B))
+    address := address + 1.U
+    when(address === (capacity - 1).U) {
+      valid := true.B
+    }
+  }
+  io.load_finished := valid
+  io.rom_address := address
+}
--- a/lab1/src/main/scala/peripheral/VGADisplay.scala
+++ b/lab1/src/main/scala/peripheral/VGADisplay.scala
@@ -0,0 +1,116 @@
+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package peripheral
+
+import chisel3._
+
+
+class VGASync extends Module {
+  val io = IO(new Bundle {
+    val hsync = Output(Bool())
+    val vsync = Output(Bool())
+    val video_on = Output(Bool())
+    val p_tick = Output(Bool())
+    val f_tick = Output(Bool())
+    val x = Output(UInt(10.W))
+    val y = Output(UInt(10.W))
+  })
+
+  val DisplayHorizontal = ScreenInfo.DisplayHorizontal
+  val DisplayVertical = ScreenInfo.DisplayVertical
+
+  val BorderLeft = 48
+  val BorderRight = 16
+  val BorderTop = 10
+  val BorderBottom = 33
+
+  val RetraceHorizontal = 96
+  val RetraceVertical = 2
+
+  val MaxHorizontal = DisplayHorizontal + BorderLeft + BorderRight + RetraceHorizontal - 1
+  val MaxVertical = DisplayVertical + BorderTop + BorderBottom + RetraceVertical - 1
+
+  val RetraceHorizontalStart = DisplayHorizontal + BorderRight
+  val RetraceHorizontalEnd = RetraceHorizontalStart + RetraceHorizontal - 1
+
+  val RetraceVerticalStart = DisplayVertical + BorderBottom
+  val RetraceVerticalEnd = RetraceVerticalStart + RetraceVertical - 1
+
+  val pixel = RegInit(UInt(2.W), 0.U)
+  val pixel_next = Wire(UInt(2.W))
+  val pixel_tick = Wire(Bool())
+
+  val v_count_reg = RegInit(UInt(10.W), 0.U)
+  val h_count_reg = RegInit(UInt(10.W), 0.U)
+
+  val v_count_next = Wire(UInt(10.W))
+  val h_count_next = Wire(UInt(10.W))
+
+  val vsync_reg = RegInit(Bool(), false.B)
+  val hsync_reg = RegInit(Bool(), false.B)
+
+  val vsync_next = Wire(Bool())
+  val hsync_next = Wire(Bool())
+
+  pixel_next := pixel + 1.U
+  pixel_tick := pixel === 0.U
+
+  h_count_next := Mux(
+    pixel_tick,
+    Mux(h_count_reg === MaxHorizontal.U, 0.U, h_count_reg + 1.U),
+    h_count_reg
+  )
+
+  v_count_next := Mux(
+    pixel_tick && h_count_reg === MaxHorizontal.U,
+    Mux(v_count_reg === MaxVertical.U, 0.U, v_count_reg + 1.U),
+    v_count_reg
+  )
+
+  hsync_next := h_count_reg >= RetraceHorizontalStart.U && h_count_reg <= RetraceHorizontalEnd.U
+  vsync_next := v_count_reg >= RetraceVerticalStart.U && v_count_reg <= RetraceVerticalEnd.U
+
+  pixel := pixel_next
+  hsync_reg := hsync_next
+  vsync_reg := vsync_next
+  v_count_reg := v_count_next
+  h_count_reg := h_count_next
+
+  io.video_on := h_count_reg < DisplayHorizontal.U && v_count_reg < DisplayVertical.U
+  io.hsync := hsync_reg
+  io.vsync := vsync_reg
+  io.x := h_count_reg
+  io.y := v_count_reg
+  io.p_tick := pixel_tick
+  io.f_tick := io.x === 0.U && io.y === 0.U
+}
+
+class VGADisplay extends Module {
+  val io = IO(new Bundle() {
+    val x = Output(UInt(16.W))
+    val y = Output(UInt(16.W))
+    val video_on = Output(Bool())
+
+    val hsync = Output(Bool())
+    val vsync = Output(Bool())
+  })
+
+  val sync = Module(new VGASync)
+  io.hsync := sync.io.hsync
+  io.vsync := sync.io.vsync
+  io.x := sync.io.x
+  io.y := sync.io.y
+  io.video_on := sync.io.y
+}
--- a/lab1/src/main/scala/riscv/CPUBundle.scala
+++ b/lab1/src/main/scala/riscv/CPUBundle.scala
@@ -0,0 +1,28 @@
+// Copyright 2022 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv
+
+import chisel3._
+import peripheral.RAMBundle
+
+class CPUBundle extends Bundle {
+  val instruction_address = Output(UInt(Parameters.AddrWidth))
+  val instruction = Input(UInt(Parameters.DataWidth))
+  val memory_bundle = Flipped(new RAMBundle)
+  val instruction_valid = Input(Bool())
+  val deviceSelect = Output(UInt(Parameters.SlaveDeviceCountBits.W))
+  val debug_read_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
+  val debug_read_data = Output(UInt(Parameters.DataWidth))
+}
--- a/lab1/src/main/scala/riscv/Parameters.scala
+++ b/lab1/src/main/scala/riscv/Parameters.scala
@@ -0,0 +1,58 @@
+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv
+
+import chisel3._
+import chisel3.util._
+
+object ImplementationType {
+  val ThreeStage = 0
+  val FiveStage = 1
+}
+
+object Parameters {
+  val AddrBits = 32
+  val AddrWidth = AddrBits.W
+
+  val InstructionBits = 32
+  val InstructionWidth = InstructionBits.W
+  val DataBits = 32
+  val DataWidth = DataBits.W
+  val ByteBits = 8
+  val ByteWidth = ByteBits.W
+  val WordSize = Math.ceil(DataBits / ByteBits).toInt
+
+  val PhysicalRegisters = 32
+  val PhysicalRegisterAddrBits = log2Up(PhysicalRegisters)
+  val PhysicalRegisterAddrWidth = PhysicalRegisterAddrBits.W
+
+  val CSRRegisterAddrBits = 12
+  val CSRRegisterAddrWidth = CSRRegisterAddrBits.W
+
+  val InterruptFlagBits = 32
+  val InterruptFlagWidth = InterruptFlagBits.W
+
+  val HoldStateBits = 3
+  val StallStateWidth = HoldStateBits.W
+
+  val MemorySizeInBytes = 32768
+  val MemorySizeInWords = MemorySizeInBytes / 4
+
+  val EntryAddress = 0x1000.U(Parameters.AddrWidth)
+
+  val MasterDeviceCount = 1
+  val SlaveDeviceCount = 8
+  val SlaveDeviceCountBits = log2Up(Parameters.SlaveDeviceCount)
+}
--- a/lab1/src/main/scala/riscv/core/ALU.scala
+++ b/lab1/src/main/scala/riscv/core/ALU.scala
@@ -0,0 +1,70 @@
+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv.core
+
+import chisel3._
+import chisel3.experimental.ChiselEnum
+import chisel3.util._
+import riscv.Parameters
+
+object ALUFunctions extends ChiselEnum {
+  val zero, add, sub, sll, slt, xor, or, and, srl, sra, sltu = Value
+}
+
+class ALU extends Module {
+  val io = IO(new Bundle {
+    val func = Input(ALUFunctions())
+
+    val op1 = Input(UInt(Parameters.DataWidth))
+    val op2 = Input(UInt(Parameters.DataWidth))
+
+    val result = Output(UInt(Parameters.DataWidth))
+  })
+
+  io.result := 0.U
+  switch(io.func) {
+    is(ALUFunctions.add) {
+      io.result := io.op1 + io.op2
+    }
+    is(ALUFunctions.sub) {
+      io.result := io.op1 - io.op2
+    }
+    is(ALUFunctions.sll) {
+      io.result := io.op1 << io.op2(4, 0)
+    }
+    is(ALUFunctions.slt) {
+      io.result := io.op1.asSInt < io.op2.asSInt
+    }
+    is(ALUFunctions.xor) {
+      io.result := io.op1 ^ io.op2
+    }
+    is(ALUFunctions.or) {
+      io.result := io.op1 | io.op2
+    }
+    is(ALUFunctions.and) {
+      io.result := io.op1 & io.op2
+    }
+    is(ALUFunctions.srl) {
+      io.result := io.op1 >> io.op2(4, 0)
+    }
+    is(ALUFunctions.sra) {
+      io.result := (io.op1.asSInt >> io.op2(4, 0)).asUInt
+    }
+    is(ALUFunctions.sltu) {
+      io.result := io.op1 < io.op2
+    }
+  }
+
+}
--- a/lab1/src/main/scala/riscv/core/ALUControl.scala
+++ b/lab1/src/main/scala/riscv/core/ALUControl.scala
@@ -0,0 +1,86 @@
+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv.core
+
+import chisel3._
+import chisel3.util._
+
+class ALUControl extends Module {
+  val io = IO(new Bundle {
+    val opcode = Input(UInt(7.W))
+    val funct3 = Input(UInt(3.W))
+    val funct7 = Input(UInt(7.W))
+
+    val alu_funct = Output(ALUFunctions())
+  })
+
+  io.alu_funct := ALUFunctions.zero
+
+  switch(io.opcode) {
+    is(InstructionTypes.I) {
+      io.alu_funct := MuxLookup(
+        io.funct3,
+        ALUFunctions.zero,
+        IndexedSeq(
+          InstructionsTypeI.addi -> ALUFunctions.add,
+          InstructionsTypeI.slli -> ALUFunctions.sll,
+          InstructionsTypeI.slti -> ALUFunctions.slt,
+          InstructionsTypeI.sltiu -> ALUFunctions.sltu,
+          InstructionsTypeI.xori -> ALUFunctions.xor,
+          InstructionsTypeI.ori -> ALUFunctions.or,
+          InstructionsTypeI.andi -> ALUFunctions.and,
+          InstructionsTypeI.sri -> Mux(io.funct7(5), ALUFunctions.sra, ALUFunctions.srl)
+        ),
+      )
+    }
+    is(InstructionTypes.RM) {
+      io.alu_funct := MuxLookup(
+        io.funct3,
+        ALUFunctions.zero,
+        IndexedSeq(
+          InstructionsTypeR.add_sub -> Mux(io.funct7(5), ALUFunctions.sub, ALUFunctions.add),
+          InstructionsTypeR.sll -> ALUFunctions.sll,
+          InstructionsTypeR.slt -> ALUFunctions.slt,
+          InstructionsTypeR.sltu -> ALUFunctions.sltu,
+          InstructionsTypeR.xor -> ALUFunctions.xor,
+          InstructionsTypeR.or -> ALUFunctions.or,
+          InstructionsTypeR.and -> ALUFunctions.and,
+          InstructionsTypeR.sr -> Mux(io.funct7(5), ALUFunctions.sra, ALUFunctions.srl)
+        ),
+      )
+    }
+    is(InstructionTypes.B) {
+      io.alu_funct := ALUFunctions.add
+    }
+    is(InstructionTypes.L) {
+      io.alu_funct := ALUFunctions.add
+    }
+    is(InstructionTypes.S) {
+      io.alu_funct := ALUFunctions.add
+    }
+    is(Instructions.jal) {
+      io.alu_funct := ALUFunctions.add
+    }
+    is(Instructions.jalr) {
+      io.alu_funct := ALUFunctions.add
+    }
+    is(Instructions.lui) {
+      io.alu_funct := ALUFunctions.add
+    }
+    is(Instructions.auipc) {
+      io.alu_funct := ALUFunctions.add
+    }
+  }
+}
--- a/lab1/src/main/scala/riscv/core/CPU.scala
+++ b/lab1/src/main/scala/riscv/core/CPU.scala
@@ -0,0 +1,77 @@
+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv.core
+
+import chisel3._
+import chisel3.util.Cat
+import riscv.{CPUBundle, Parameters}
+
+class CPU extends Module {
+  val io = IO(new CPUBundle)
+
+  val regs = Module(new RegisterFile)
+  val inst_fetch = Module(new InstructionFetch)
+  val id = Module(new InstructionDecode)
+  val ex = Module(new Execute)
+  val mem = Module(new MemoryAccess)
+  val wb = Module(new WriteBack)
+
+
+  io.deviceSelect := mem.io.memory_bundle.address(Parameters.AddrBits - 1, Parameters.AddrBits - Parameters.SlaveDeviceCountBits)
+
+  inst_fetch.io.jump_address_id := ex.io.if_jump_address
+  inst_fetch.io.jump_flag_id := ex.io.if_jump_flag
+  inst_fetch.io.instruction_valid := io.instruction_valid
+  inst_fetch.io.instruction_read_data := io.instruction
+  io.instruction_address := inst_fetch.io.instruction_address
+
+  regs.io.write_enable := id.io.reg_write_enable
+  regs.io.write_address := id.io.reg_write_address
+  regs.io.write_data := wb.io.regs_write_data
+  regs.io.read_address1 := id.io.regs_reg1_read_address
+  regs.io.read_address2 := id.io.regs_reg2_read_address
+
+  regs.io.debug_read_address := io.debug_read_address
+  io.debug_read_data := regs.io.debug_read_data
+
+  id.io.instruction := inst_fetch.io.instruction
+
+  // lab1(cpu)
+
+
+
+
+
+
+  // lab1(cpu) end
+
+
+  mem.io.alu_result := ex.io.mem_alu_result
+  mem.io.reg2_data := regs.io.read_data2
+  mem.io.memory_read_enable := id.io.memory_read_enable
+  mem.io.memory_write_enable := id.io.memory_write_enable
+  mem.io.funct3 := inst_fetch.io.instruction(14, 12)
+
+  io.memory_bundle.address := Cat(0.U(Parameters.SlaveDeviceCountBits.W),mem.io.memory_bundle.address(Parameters.AddrBits - 1 - Parameters.SlaveDeviceCountBits, 0))
+  io.memory_bundle.write_enable := mem.io.memory_bundle.write_enable
+  io.memory_bundle.write_data := mem.io.memory_bundle.write_data
+  io.memory_bundle.write_strobe := mem.io.memory_bundle.write_strobe
+  mem.io.memory_bundle.read_data := io.memory_bundle.read_data
+
+  wb.io.instruction_address := inst_fetch.io.instruction_address
+  wb.io.alu_result := ex.io.mem_alu_result
+  wb.io.memory_read_data := mem.io.wb_memory_read_data
+  wb.io.regs_write_source := id.io.wb_reg_write_source
+}
--- a/lab1/src/main/scala/riscv/core/Execute.scala
+++ b/lab1/src/main/scala/riscv/core/Execute.scala
@@ -0,0 +1,75 @@
+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv.core
+
+import chisel3._
+import chisel3.util.{Cat, MuxLookup}
+import riscv.Parameters
+
+class Execute extends Module {
+  val io = IO(new Bundle {
+    val instruction = Input(UInt(Parameters.InstructionWidth))
+    val instruction_address = Input(UInt(Parameters.AddrWidth))
+    val reg1_data = Input(UInt(Parameters.DataWidth))
+    val reg2_data = Input(UInt(Parameters.DataWidth))
+    val immediate = Input(UInt(Parameters.DataWidth))
+    val aluop1_source = Input(UInt(1.W))
+    val aluop2_source = Input(UInt(1.W))
+
+    val mem_alu_result = Output(UInt(Parameters.DataWidth))
+    val if_jump_flag = Output(Bool())
+    val if_jump_address = Output(UInt(Parameters.DataWidth))
+  })
+
+  val opcode = io.instruction(6, 0)
+  val funct3 = io.instruction(14, 12)
+  val funct7 = io.instruction(31, 25)
+  val rd = io.instruction(11, 7)
+  val uimm = io.instruction(19, 15)
+
+  val alu = Module(new ALU)
+  val alu_ctrl = Module(new ALUControl)
+
+  alu_ctrl.io.opcode := opcode
+  alu_ctrl.io.funct3 := funct3
+  alu_ctrl.io.funct7 := funct7
+
+  // lab1(Execute)
+
+
+
+
+
+
+
+  // lab1(Execute) end
+
+  io.mem_alu_result := alu.io.result
+  io.if_jump_flag := opcode === Instructions.jal ||
+    (opcode === Instructions.jalr) ||
+    (opcode === InstructionTypes.B) && MuxLookup(
+      funct3,
+      false.B,
+      IndexedSeq(
+        InstructionsTypeB.beq -> (io.reg1_data === io.reg2_data),
+        InstructionsTypeB.bne -> (io.reg1_data =/= io.reg2_data),
+        InstructionsTypeB.blt -> (io.reg1_data.asSInt < io.reg2_data.asSInt),
+        InstructionsTypeB.bge -> (io.reg1_data.asSInt >= io.reg2_data.asSInt),
+        InstructionsTypeB.bltu -> (io.reg1_data.asUInt < io.reg2_data.asUInt),
+        InstructionsTypeB.bgeu -> (io.reg1_data.asUInt >= io.reg2_data.asUInt)
+      )
+    )
+  io.if_jump_address := io.immediate + Mux(opcode === Instructions.jalr, io.reg1_data, io.instruction_address)
+}
--- a/lab1/src/main/scala/riscv/core/InstructionDecode.scala
+++ b/lab1/src/main/scala/riscv/core/InstructionDecode.scala
@@ -0,0 +1,193 @@
+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv.core
+
+import chisel3._
+import chisel3.util._
+import riscv.Parameters
+
+object InstructionTypes {
+  val L = "b0000011".U
+  val I = "b0010011".U
+  val S = "b0100011".U
+  val RM = "b0110011".U
+  val B = "b1100011".U
+}
+
+object Instructions {
+  val lui = "b0110111".U
+  val nop = "b0000001".U
+  val jal = "b1101111".U
+  val jalr = "b1100111".U
+  val auipc = "b0010111".U
+  val csr = "b1110011".U
+  val fence = "b0001111".U
+}
+
+object InstructionsTypeL {
+  val lb = "b000".U
+  val lh = "b001".U
+  val lw = "b010".U
+  val lbu = "b100".U
+  val lhu = "b101".U
+}
+
+object InstructionsTypeI {
+  val addi = 0.U
+  val slli = 1.U
+  val slti = 2.U
+  val sltiu = 3.U
+  val xori = 4.U
+  val sri = 5.U
+  val ori = 6.U
+  val andi = 7.U
+}
+
+object InstructionsTypeS {
+  val sb = "b000".U
+  val sh = "b001".U
+  val sw = "b010".U
+}
+
+object InstructionsTypeR {
+  val add_sub = 0.U
+  val sll = 1.U
+  val slt = 2.U
+  val sltu = 3.U
+  val xor = 4.U
+  val sr = 5.U
+  val or = 6.U
+  val and = 7.U
+}
+
+object InstructionsTypeM {
+  val mul = 0.U
+  val mulh = 1.U
+  val mulhsu = 2.U
+  val mulhum = 3.U
+  val div = 4.U
+  val divu = 5.U
+  val rem = 6.U
+  val remu = 7.U
+}
+
+object InstructionsTypeB {
+  val beq = "b000".U
+  val bne = "b001".U
+  val blt = "b100".U
+  val bge = "b101".U
+  val bltu = "b110".U
+  val bgeu = "b111".U
+}
+
+object InstructionsTypeCSR {
+  val csrrw = "b001".U
+  val csrrs = "b010".U
+  val csrrc = "b011".U
+  val csrrwi = "b101".U
+  val csrrsi = "b110".U
+  val csrrci = "b111".U
+}
+
+object InstructionsNop {
+  val nop = 0x00000013L.U(Parameters.DataWidth)
+}
+
+object InstructionsRet {
+  val mret = 0x30200073L.U(Parameters.DataWidth)
+  val ret = 0x00008067L.U(Parameters.DataWidth)
+}
+
+object InstructionsEnv {
+  val ecall = 0x00000073L.U(Parameters.DataWidth)
+  val ebreak = 0x00100073L.U(Parameters.DataWidth)
+}
+
+object ALUOp1Source {
+  val Register = 0.U(1.W)
+  val InstructionAddress = 1.U(1.W)
+}
+
+object ALUOp2Source {
+  val Register = 0.U(1.W)
+  val Immediate = 1.U(1.W)
+}
+
+object RegWriteSource {
+  val ALUResult = 0.U(2.W)
+  val Memory = 1.U(2.W)
+  //val CSR = 2.U(2.W)
+  val NextInstructionAddress = 3.U(2.W)
+}
+
+class InstructionDecode extends Module {
+  val io = IO(new Bundle {
+    val instruction = Input(UInt(Parameters.InstructionWidth))
+
+    val regs_reg1_read_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
+    val regs_reg2_read_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
+    val ex_immediate = Output(UInt(Parameters.DataWidth))
+    val ex_aluop1_source = Output(UInt(1.W))
+    val ex_aluop2_source = Output(UInt(1.W))
+    val memory_read_enable = Output(Bool())
+    val memory_write_enable = Output(Bool())
+    val wb_reg_write_source = Output(UInt(2.W))
+    val reg_write_enable = Output(Bool())
+    val reg_write_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth))
+  })
+  val opcode = io.instruction(6, 0)
+  val funct3 = io.instruction(14, 12)
+  val funct7 = io.instruction(31, 25)
+  val rd = io.instruction(11, 7)
+  val rs1 = io.instruction(19, 15)
+  val rs2 = io.instruction(24, 20)
+
+  io.regs_reg1_read_address := Mux(opcode === Instructions.lui, 0.U(Parameters.PhysicalRegisterAddrWidth), rs1)
+  io.regs_reg2_read_address := rs2
+  val immediate = MuxLookup(
+    opcode,
+    Cat(Fill(20, io.instruction(31)), io.instruction(31, 20)),
+    IndexedSeq(
+      InstructionTypes.I -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 20)),
+      InstructionTypes.L -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 20)),
+      Instructions.jalr -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 20)),
+      InstructionTypes.S -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 25), io.instruction(11, 7)),
+      InstructionTypes.B -> Cat(Fill(20, io.instruction(31)), io.instruction(7), io.instruction(30, 25), io.instruction(11, 8), 0.U(1.W)),
+      Instructions.lui -> Cat(io.instruction(31, 12), 0.U(12.W)),
+      Instructions.auipc -> Cat(io.instruction(31, 12), 0.U(12.W)),
+      Instructions.jal -> Cat(Fill(12, io.instruction(31)), io.instruction(19, 12), io.instruction(20), io.instruction(30, 21), 0.U(1.W))
+    )
+  )
+  io.ex_immediate := immediate
+  io.ex_aluop1_source := Mux(
+    opcode === Instructions.auipc || opcode === InstructionTypes.B || opcode === Instructions.jal,
+    ALUOp1Source.InstructionAddress,
+    ALUOp1Source.Register
+  )
+
+  // lab1(InstructionDecode)
+
+
+
+
+
+
+
+  // lab1(InstructionDecode) end
+  io.reg_write_enable := (opcode === InstructionTypes.RM) || (opcode === InstructionTypes.I) ||
+    (opcode === InstructionTypes.L) || (opcode === Instructions.auipc) || (opcode === Instructions.lui) ||
+    (opcode === Instructions.jal) || (opcode === Instructions.jalr)
+  io.reg_write_address := io.instruction(11, 7)
+}
--- a/lab1/src/main/scala/riscv/core/InstructionFetch.scala
+++ b/lab1/src/main/scala/riscv/core/InstructionFetch.scala
@@ -0,0 +1,50 @@
+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv.core
+
+import chisel3._
+import riscv.Parameters
+
+object ProgramCounter {
+  val EntryAddress = Parameters.EntryAddress
+}
+
+class InstructionFetch extends Module {
+  val io = IO(new Bundle {
+    val jump_flag_id = Input(Bool())
+    val jump_address_id = Input(UInt(Parameters.AddrWidth))
+    val instruction_read_data = Input(UInt(Parameters.DataWidth))
+    val instruction_valid = Input(Bool())
+
+    val instruction_address = Output(UInt(Parameters.AddrWidth))
+    val instruction = Output(UInt(Parameters.InstructionWidth))
+  })
+  val pc = RegInit(ProgramCounter.EntryAddress)
+
+  when(io.instruction_valid) {
+    io.instruction := io.instruction_read_data
+    // lab1(InstructionFetch)
+
+
+
+    // la1(InstructionFetch) end
+
+
+  }.otherwise{
+    pc := pc
+    io.instruction := 0x00000013.U
+  }
+  io.instruction_address := pc
+}
--- a/lab1/src/main/scala/riscv/core/MemoryAccess.scala
+++ b/lab1/src/main/scala/riscv/core/MemoryAccess.scala
@@ -0,0 +1,106 @@
+// Copyright 2022 Canbin Huang
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv.core
+
+import chisel3._
+import chisel3.util._
+import peripheral.RAMBundle
+import riscv.Parameters
+
+class MemoryAccess extends Module {
+  val io = IO(new Bundle() {
+    val alu_result = Input(UInt(Parameters.DataWidth))
+    val reg2_data = Input(UInt(Parameters.DataWidth))
+    val memory_read_enable = Input(Bool())
+    val memory_write_enable = Input(Bool())
+    val funct3 = Input(UInt(3.W))
+
+    val wb_memory_read_data = Output(UInt(Parameters.DataWidth))
+
+    val memory_bundle = Flipped(new RAMBundle)
+  })
+  val mem_address_index = io.alu_result(log2Up(Parameters.WordSize) - 1, 0).asUInt
+
+  io.memory_bundle.write_enable := false.B
+  io.memory_bundle.write_data := 0.U
+  io.memory_bundle.address := io.alu_result
+  io.memory_bundle.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B))
+  io.wb_memory_read_data := 0.U
+
+  when(io.memory_read_enable) {
+    val data = io.memory_bundle.read_data
+    io.wb_memory_read_data := MuxLookup(
+      io.funct3,
+      0.U,
+      IndexedSeq(
+        InstructionsTypeL.lb -> MuxLookup(
+          mem_address_index,
+          Cat(Fill(24, data(31)), data(31, 24)),
+          IndexedSeq(
+            0.U -> Cat(Fill(24, data(7)), data(7, 0)),
+            1.U -> Cat(Fill(24, data(15)), data(15, 8)),
+            2.U -> Cat(Fill(24, data(23)), data(23, 16))
+          )
+        ),
+        InstructionsTypeL.lbu -> MuxLookup(
+          mem_address_index,
+          Cat(Fill(24, 0.U), data(31, 24)),
+          IndexedSeq(
+            0.U -> Cat(Fill(24, 0.U), data(7, 0)),
+            1.U -> Cat(Fill(24, 0.U), data(15, 8)),
+            2.U -> Cat(Fill(24, 0.U), data(23, 16))
+          )
+        ),
+        InstructionsTypeL.lh -> Mux(
+          mem_address_index === 0.U,
+          Cat(Fill(16, data(15)), data(15, 0)),
+          Cat(Fill(16, data(31)), data(31, 16))
+
+        ),
+        InstructionsTypeL.lhu -> Mux(
+          mem_address_index === 0.U,
+          Cat(Fill(16, 0.U), data(15, 0)),
+          Cat(Fill(16, 0.U), data(31, 16))
+        ),
+        InstructionsTypeL.lw -> data
+      )
+    )
+  }.elsewhen(io.memory_write_enable) {
+    io.memory_bundle.write_data := io.reg2_data
+    io.memory_bundle.write_enable := true.B
+    io.memory_bundle.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B))
+    when(io.funct3 === InstructionsTypeS.sb) {
+      io.memory_bundle.write_strobe(mem_address_index) := true.B
+      io.memory_bundle.write_data := io.reg2_data(Parameters.ByteBits, 0) << (mem_address_index << log2Up(Parameters.ByteBits).U)
+    }.elsewhen(io.funct3 === InstructionsTypeS.sh) {
+      when(mem_address_index === 0.U) {
+        for (i <- 0 until Parameters.WordSize / 2) {
+          io.memory_bundle.write_strobe(i) := true.B
+        }
+        io.memory_bundle.write_data := io.reg2_data(Parameters.WordSize / 2 * Parameters.ByteBits, 0)
+      }.otherwise {
+        for (i <- Parameters.WordSize / 2 until Parameters.WordSize) {
+          io.memory_bundle.write_strobe(i) := true.B
+        }
+        io.memory_bundle.write_data := io.reg2_data(Parameters.WordSize / 2 * Parameters.ByteBits, 0) << (Parameters
+          .WordSize / 2 * Parameters.ByteBits)
+      }
+    }.elsewhen(io.funct3 === InstructionsTypeS.sw) {
+      for (i <- 0 until Parameters.WordSize) {
+        io.memory_bundle.write_strobe(i) := true.B
+      }
+    }
+  }
+}
--- a/lab1/src/main/scala/riscv/core/RegisterFile.scala
+++ b/lab1/src/main/scala/riscv/core/RegisterFile.scala
@@ -0,0 +1,70 @@
+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv.core
+
+import chisel3._
+import riscv.Parameters
+
+object Registers extends Enumeration {
+  type Register = Value
+  val zero,
+  ra, sp, gp, tp,
+  t0, t1, t2, fp,
+  s1,
+  a0, a1, a2, a3, a4, a5, a6, a7,
+  s2, s3, s4, s5, s6, s7, s8, s9, s10, s11,
+  t3, t4, t5, t6 = Value
+}
+
+class RegisterFile extends Module {
+  val io = IO(new Bundle {
+    val write_enable = Input(Bool())
+    val write_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
+    val write_data = Input(UInt(Parameters.DataWidth))
+
+    val read_address1 = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
+    val read_address2 = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
+    val read_data1 = Output(UInt(Parameters.DataWidth))
+    val read_data2 = Output(UInt(Parameters.DataWidth))
+
+    val debug_read_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
+    val debug_read_data = Output(UInt(Parameters.DataWidth))
+  })
+  val registers = RegInit(VecInit(Seq.fill(Parameters.PhysicalRegisters)(0.U(Parameters.DataWidth))))
+
+  when(!reset.asBool) {
+    when(io.write_enable && io.write_address =/= 0.U) {
+      registers(io.write_address) := io.write_data
+    }
+  }
+
+  io.read_data1 := Mux(
+    io.read_address1 === 0.U,
+    0.U,
+    registers(io.read_address1)
+  )
+
+  io.read_data2 := Mux(
+    io.read_address2 === 0.U,
+    0.U,
+    registers(io.read_address2)
+  )
+
+  io.debug_read_data := Mux(
+    io.debug_read_address === 0.U,
+    0.U,
+    registers(io.debug_read_address)
+  )
+}
--- a/lab1/src/main/scala/riscv/core/WriteBack.scala
+++ b/lab1/src/main/scala/riscv/core/WriteBack.scala
@@ -0,0 +1,37 @@
+// Copyright 2022 Canbin Huang
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv.core
+
+import chisel3._
+import chisel3.util._
+import riscv.Parameters
+
+class WriteBack extends Module {
+  val io = IO(new Bundle() {
+    val instruction_address = Input(UInt(Parameters.AddrWidth))
+    val alu_result = Input(UInt(Parameters.DataWidth))
+    val memory_read_data = Input(UInt(Parameters.DataWidth))
+    val regs_write_source = Input(UInt(2.W))
+    val regs_write_data = Output(UInt(Parameters.DataWidth))
+  })
+  io.regs_write_data := MuxLookup(
+    io.regs_write_source,
+    io.alu_result,
+    IndexedSeq(
+      RegWriteSource.Memory -> io.memory_read_data,
+      RegWriteSource.NextInstructionAddress -> (io.instruction_address + 4.U)
+    )
+  )
+}
--- a/lab1/src/test/scala/riscv/TestAnnotations.scala
+++ b/lab1/src/test/scala/riscv/TestAnnotations.scala
@@ -0,0 +1,52 @@
+// Copyright 2022 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv
+
+import chiseltest.{VerilatorBackendAnnotation, WriteVcdAnnotation}
+import firrtl.AnnotationSeq
+
+import java.nio.file.{Files, Paths}
+
+object VerilatorEnabler {
+  val annos: AnnotationSeq = if (sys.env.contains("Path")) {
+    if (sys.env.getOrElse("Path", "").split(";").exists(path => {
+      Files.exists(Paths.get(path, "verilator"))
+    })) {
+      Seq(VerilatorBackendAnnotation)
+    } else{
+      Seq()
+    }
+  } else {
+    if (sys.env.getOrElse("PATH", "").split(":").exists(path => {
+      Files.exists(Paths.get(path, "verilator"))
+    })) {
+      Seq(VerilatorBackendAnnotation)
+    } else {
+      Seq()
+    }
+  }
+}
+
+object WriteVcdEnabler {
+  val annos: AnnotationSeq = if (sys.env.contains("WRITE_VCD")) {
+    Seq(WriteVcdAnnotation)
+  } else {
+    Seq()
+  }
+}
+
+object TestAnnotations {
+  val annos = VerilatorEnabler.annos ++ WriteVcdEnabler.annos
+}
--- a/lab1/src/test/scala/riscv/singlecycle/CPUTest.scala
+++ b/lab1/src/test/scala/riscv/singlecycle/CPUTest.scala
@@ -0,0 +1,125 @@
+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv.singlecycle
+
+
+import chisel3._
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+import peripheral.{InstructionROM, Memory, ROMLoader}
+import riscv.core.{CPU, ProgramCounter}
+import riscv.{Parameters, TestAnnotations}
+
+import java.nio.{ByteBuffer, ByteOrder}
+
+
+class TestTopModule(exeFilename: String) extends Module {
+  val io = IO(new Bundle {
+    val mem_debug_read_address = Input(UInt(Parameters.AddrWidth))
+    val regs_debug_read_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth))
+    val regs_debug_read_data = Output(UInt(Parameters.DataWidth))
+    val mem_debug_read_data = Output(UInt(Parameters.DataWidth))
+  })
+
+  val mem = Module(new Memory(8192))
+  val instruction_rom = Module(new InstructionROM(exeFilename))
+  val rom_loader = Module(new ROMLoader(instruction_rom.capacity))
+
+  rom_loader.io.rom_data := instruction_rom.io.data
+  rom_loader.io.load_address := Parameters.EntryAddress
+  instruction_rom.io.address := rom_loader.io.rom_address
+
+  val CPU_clkdiv = RegInit(UInt(2.W), 0.U)
+  val CPU_tick = Wire(Bool())
+  val CPU_next = Wire(UInt(2.W))
+  CPU_next := Mux(CPU_clkdiv === 3.U, 0.U, CPU_clkdiv + 1.U)
+  CPU_tick := CPU_clkdiv === 0.U
+  CPU_clkdiv := CPU_next
+
+  withClock(CPU_tick.asClock) {
+    val cpu = Module(new CPU)
+    cpu.io.debug_read_address := 0.U
+    cpu.io.instruction_valid := rom_loader.io.load_finished
+    mem.io.instruction_address := cpu.io.instruction_address
+    cpu.io.instruction := mem.io.instruction
+
+
+    when(!rom_loader.io.load_finished) {
+      rom_loader.io.bundle <> mem.io.bundle
+      cpu.io.memory_bundle.read_data := 0.U
+    }.otherwise {
+      rom_loader.io.bundle.read_data := 0.U
+      cpu.io.memory_bundle <> mem.io.bundle
+    }
+
+    cpu.io.debug_read_address := io.regs_debug_read_address
+    io.regs_debug_read_data := cpu.io.debug_read_data
+  }
+
+  mem.io.debug_read_address := io.mem_debug_read_address
+  io.mem_debug_read_data := mem.io.debug_read_data
+}
+
+
+class FibonacciTest extends AnyFlatSpec with ChiselScalatestTester {
+  behavior of "Single Cycle CPU"
+  it should "calculate recursively fibonacci(10)" in {
+    test(new TestTopModule("fibonacci.asmbin")).withAnnotations(TestAnnotations.annos) { c =>
+      for (i <- 1 to 50) {
+        c.clock.step(1000)
+        c.io.mem_debug_read_address.poke((i * 4).U) // Avoid timeout
+      }
+
+      c.io.mem_debug_read_address.poke(4.U)
+      c.clock.step()
+      c.io.mem_debug_read_data.expect(55.U)
+    }
+  }
+}
+
+class QuicksortTest extends AnyFlatSpec with ChiselScalatestTester {
+  behavior of "Single Cycle CPU"
+  it should "quicksort 10 numbers" in {
+    test(new TestTopModule("quicksort.asmbin")).withAnnotations(TestAnnotations.annos) { c =>
+      for (i <- 1 to 50) {
+        c.clock.step(1000)
+        c.io.mem_debug_read_address.poke((i * 4).U) // Avoid timeout
+      }
+      for (i <- 1 to 10) {
+        c.io.mem_debug_read_address.poke((4 * i).U)
+        c.clock.step()
+        c.io.mem_debug_read_data.expect((i - 1).U)
+      }
+    }
+  }
+}
+
+class ByteAccessTest extends AnyFlatSpec with ChiselScalatestTester {
+  behavior of "Single Cycle CPU"
+  it should "store and load single byte" in {
+    test(new TestTopModule("sb.asmbin")).withAnnotations(TestAnnotations.annos) { c =>
+      for (i <- 1 to 500) {
+        c.clock.step()
+        c.io.mem_debug_read_address.poke((i * 4).U) // Avoid timeout
+      }
+      c.io.regs_debug_read_address.poke(5.U)
+      c.io.regs_debug_read_data.expect(0xDEADBEEFL.U)
+      c.io.regs_debug_read_address.poke(6.U)
+      c.io.regs_debug_read_data.expect(0xEF.U)
+      c.io.regs_debug_read_address.poke(1.U)
+      c.io.regs_debug_read_data.expect(0x15EF.U)
+    }
+  }
+}
--- a/lab1/src/test/scala/riscv/singlecycle/ExecuteTest.scala
+++ b/lab1/src/test/scala/riscv/singlecycle/ExecuteTest.scala
@@ -0,0 +1,72 @@
+// Copyright 2022 hrpccs
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv.singlecycle
+
+import chisel3._
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+import riscv.TestAnnotations
+import riscv.core.{ALUOp1Source, ALUOp2Source, Execute, InstructionTypes}
+
+class ExecuteTest extends AnyFlatSpec with ChiselScalatestTester{
+  behavior of "Exxecute of Single Cycle CPU"
+  it should "execute correctly" in {
+    test(new Execute).withAnnotations(TestAnnotations.annos) { c =>
+
+      // add test
+      c.io.instruction.poke(0x001101b3L.U) //x3 =  x2 + x1
+      //c.io.immediate.poke(0.U)
+      //c.io.aluop1_source.poke(0.U)
+      //c.io.aluop2_source.poke(0.U)
+
+      var x = 0
+      for (x <- 0 to 100) {
+        val op1 = scala.util.Random.nextInt(429496729)
+        val op2 = scala.util.Random.nextInt(429496729)
+        val result = op1 + op2
+        val addr = scala.util.Random.nextInt(32)
+
+        c.io.reg1_data.poke(op1.U)
+        c.io.reg2_data.poke(op2.U)
+
+        c.clock.step()
+        c.io.mem_alu_result.expect(result.U)
+        c.io.if_jump_flag.expect(0.U)
+      }
+
+      // beq test
+      c.io.instruction.poke(0x00208163L.U) //pc + 2 if x1 === x2
+      c.io.instruction_address.poke(2.U)
+      c.io.immediate.poke(2.U)
+      c.io.aluop1_source.poke(1.U)
+      c.io.aluop2_source.poke(1.U)
+      c.clock.step()
+
+      // equ
+      c.io.reg1_data.poke(9.U)
+      c.io.reg2_data.poke(9.U)
+      c.clock.step()//add
+      c.io.if_jump_flag.expect(1.U)
+      c.io.if_jump_address.expect(4.U)
+
+      // not equ
+      c.io.reg1_data.poke(9.U)
+      c.io.reg2_data.poke(19.U)
+      c.clock.step()
+      c.io.if_jump_flag.expect(0.U)
+      c.io.if_jump_address.expect(4.U)
+    }
+  }
+}
--- a/lab1/src/test/scala/riscv/singlecycle/InstructionDecoderTest.scala
+++ b/lab1/src/test/scala/riscv/singlecycle/InstructionDecoderTest.scala
@@ -0,0 +1,46 @@
+// Copyright 2022 hrpccs
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv.singlecycle
+
+import chisel3._
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+import riscv.TestAnnotations
+import riscv.core.{ALUOp1Source, ALUOp2Source, InstructionDecode, InstructionTypes}
+
+class InstructionDecoderTest extends AnyFlatSpec with ChiselScalatestTester{
+  behavior of "InstructionDecoder of Single Cycle CPU"
+  it should "produce correct control signal" in {
+    test(new InstructionDecode).withAnnotations(TestAnnotations.annos) { c =>
+      c.io.instruction.poke(0x00a02223L.U) //S-type
+      c.io.ex_aluop1_source.expect(ALUOp1Source.Register)
+      c.io.ex_aluop2_source.expect(ALUOp2Source.Immediate)
+      c.io.regs_reg1_read_address.expect(0.U)
+      c.io.regs_reg2_read_address.expect(10.U)
+      c.clock.step()
+
+      c.io.instruction.poke(0x000022b7L.U) //lui
+      c.io.regs_reg1_read_address.expect(0.U)
+      c.io.ex_aluop1_source.expect(ALUOp1Source.Register)
+      c.io.ex_aluop2_source.expect(ALUOp2Source.Immediate)
+      c.clock.step()
+
+      c.io.instruction.poke(0x002081b3L.U) //add
+      c.io.ex_aluop1_source.expect(ALUOp1Source.Register)
+      c.io.ex_aluop2_source.expect(ALUOp2Source.Register)
+      c.clock.step()
+    }
+  }
+}
--- a/lab1/src/test/scala/riscv/singlecycle/InstructionFetchTest.scala
+++ b/lab1/src/test/scala/riscv/singlecycle/InstructionFetchTest.scala
@@ -0,0 +1,58 @@
+// Copyright 2022 hrpccs
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv.singlecycle
+
+import chisel3._
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+import riscv.TestAnnotations
+import riscv.Parameters
+import riscv.core.{ALUOp1Source, ALUOp2Source, InstructionFetch, InstructionTypes,ProgramCounter}
+
+
+import scala.math.pow
+import scala.util.Random
+
+
+
+class InstructionFetchTest extends AnyFlatSpec with ChiselScalatestTester{
+  behavior of "InstructionFetch of Single Cycle CPU"
+  it should "fetch instruction" in {
+    test(new InstructionFetch).withAnnotations(TestAnnotations.annos) { c =>
+      val entry = 0x1000
+      var pre = entry
+      var cur = pre
+      c.io.instruction_valid.poke(true.B)
+      var x = 0
+      for (x <- 0 to 100) {
+        Random.nextInt(2) match {
+          case 0 => // no jump
+            cur = pre + 4
+            c.io.jump_flag_id.poke(false.B)
+            c.clock.step()
+            c.io.instruction_address.expect(cur)
+            pre = pre + 4
+          case 1 => // jump
+            c.io.jump_flag_id.poke(true.B)
+            c.io.jump_address_id.poke(entry)
+            c.clock.step()
+            c.io.instruction_address.expect(entry)
+            pre = entry
+        }
+      }
+
+      }
+    }
+}
--- a/lab1/src/test/scala/riscv/singlecycle/RegisterFileTest.scala
+++ b/lab1/src/test/scala/riscv/singlecycle/RegisterFileTest.scala
@@ -0,0 +1,69 @@
+// Copyright 2021 Howard Lau
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package riscv.singlecycle
+
+import chisel3._
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+import riscv.TestAnnotations
+import riscv.core.RegisterFile
+
+class RegisterFileTest extends AnyFlatSpec with ChiselScalatestTester {
+  behavior of "Register File of Single Cycle CPU"
+  it should "read the written content" in {
+    test(new RegisterFile).withAnnotations(TestAnnotations.annos) { c =>
+      timescope {
+        c.io.write_enable.poke(true.B)
+        c.io.write_address.poke(1.U)
+        c.io.write_data.poke(0xDEADBEEFL.U)
+        c.clock.step()
+      }
+      c.io.read_address1.poke(1.U)
+      c.io.read_data1.expect(0xDEADBEEFL.U)
+    }
+  }
+
+  it should "x0 always be zero" in {
+    test(new RegisterFile).withAnnotations(TestAnnotations.annos) { c =>
+      timescope {
+        c.io.write_enable.poke(true.B)
+        c.io.write_address.poke(0.U)
+        c.io.write_data.poke(0xDEADBEEFL.U)
+        c.clock.step()
+      }
+      c.io.read_address1.poke(0.U)
+      c.io.read_data1.expect(0.U)
+    }
+  }
+
+  it should "read the writing content" in {
+    test(new RegisterFile).withAnnotations(TestAnnotations.annos) { c =>
+      timescope {
+        c.io.read_address1.poke(2.U)
+        c.io.read_data1.expect(0.U)
+        c.io.write_enable.poke(true.B)
+        c.io.write_address.poke(2.U)
+        c.io.write_data.poke(0xDEADBEEFL.U)
+        c.clock.step()
+        c.io.read_address1.poke(2.U)
+        c.io.read_data1.expect(0xDEADBEEFL.U)
+        c.clock.step()
+      }
+      c.io.read_address1.poke(2.U)
+      c.io.read_data1.expect(0xDEADBEEFL.U)
+    }
+  }
+
+}