mirror of
https://github.com/handsomezhuzhu/2025-yatcpu.git
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77 lines
3.2 KiB
Scala
77 lines
3.2 KiB
Scala
// Copyright 2021 Howard Lau
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package peripheral
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import chisel3._
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import chisel3.util._
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import riscv.Parameters
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class RAMBundle extends Bundle {
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val address = Input(UInt(Parameters.AddrWidth))
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val write_data = Input(UInt(Parameters.DataWidth))
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val write_enable = Input(Bool())
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val write_strobe = Input(Vec(Parameters.WordSize, Bool()))
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val read_data = Output(UInt(Parameters.DataWidth))
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}
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// The purpose of this module is to help the synthesis tool recognize
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// our memory as a Block RAM template
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class BlockRAM(capacity: Int) extends Module {
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val io = IO(new Bundle {
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val read_address = Input(UInt(Parameters.AddrWidth))
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val write_address = Input(UInt(Parameters.AddrWidth))
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val write_data = Input(UInt(Parameters.DataWidth))
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val write_enable = Input(Bool())
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val write_strobe = Input(Vec(Parameters.WordSize, Bool()))
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val debug_read_address = Input(UInt(Parameters.AddrWidth))
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val read_data = Output(UInt(Parameters.DataWidth))
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val debug_read_data = Output(UInt(Parameters.DataWidth))
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})
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val mem = SyncReadMem(capacity, Vec(Parameters.WordSize, UInt(Parameters.ByteWidth)))
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when(io.write_enable) {
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val write_data_vec = Wire(Vec(Parameters.WordSize, UInt(Parameters.ByteWidth)))
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for (i <- 0 until Parameters.WordSize) {
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write_data_vec(i) := io.write_data((i + 1) * Parameters.ByteBits - 1, i * Parameters.ByteBits)
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}
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mem.write((io.write_address >> 2.U).asUInt, write_data_vec, io.write_strobe)
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}
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io.read_data := mem.read((io.read_address >> 2.U).asUInt, true.B).asUInt
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io.debug_read_data := mem.read((io.debug_read_address >> 2.U).asUInt, true.B).asUInt
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}
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class Memory(capacity: Int) extends Module {
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val io = IO(new Bundle {
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val bundle = new RAMBundle
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val instruction = Output(UInt(Parameters.DataWidth))
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val instruction_address = Input(UInt(Parameters.AddrWidth))
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val debug_read_address = Input(UInt(Parameters.AddrWidth))
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val debug_read_data = Output(UInt(Parameters.DataWidth))
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})
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val mem = SyncReadMem(capacity, Vec(Parameters.WordSize, UInt(Parameters.ByteWidth)))
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when(io.bundle.write_enable) {
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val write_data_vec = Wire(Vec(Parameters.WordSize, UInt(Parameters.ByteWidth)))
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for (i <- 0 until Parameters.WordSize) {
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write_data_vec(i) := io.bundle.write_data((i + 1) * Parameters.ByteBits - 1, i * Parameters.ByteBits)
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}
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mem.write((io.bundle.address >> 2.U).asUInt, write_data_vec, io.bundle.write_strobe)
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}
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io.bundle.read_data := mem.read((io.bundle.address >> 2.U).asUInt, true.B).asUInt
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io.debug_read_data := mem.read((io.debug_read_address >> 2.U).asUInt, true.B).asUInt
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io.instruction := mem.read((io.instruction_address >> 2.U).asUInt, true.B).asUInt
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} |