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https://github.com/handsomezhuzhu/2025-yatcpu.git
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47 lines
1.7 KiB
Scala
47 lines
1.7 KiB
Scala
// Copyright 2022 hrpccs
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package riscv.singlecycle
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import chisel3._
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import chiseltest._
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import org.scalatest.flatspec.AnyFlatSpec
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import riscv.TestAnnotations
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import riscv.core.{ALUOp1Source, ALUOp2Source, InstructionDecode, InstructionTypes}
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class InstructionDecoderTest extends AnyFlatSpec with ChiselScalatestTester{
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behavior of "InstructionDecoder of Single Cycle CPU"
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it should "produce correct control signal" in {
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test(new InstructionDecode).withAnnotations(TestAnnotations.annos) { c =>
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c.io.instruction.poke(0x00a02223L.U) //S-type
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c.io.ex_aluop1_source.expect(ALUOp1Source.Register)
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c.io.ex_aluop2_source.expect(ALUOp2Source.Immediate)
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c.io.regs_reg1_read_address.expect(0.U)
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c.io.regs_reg2_read_address.expect(10.U)
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c.clock.step()
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c.io.instruction.poke(0x000022b7L.U) //lui
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c.io.regs_reg1_read_address.expect(0.U)
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c.io.ex_aluop1_source.expect(ALUOp1Source.Register)
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c.io.ex_aluop2_source.expect(ALUOp2Source.Immediate)
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c.clock.step()
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c.io.instruction.poke(0x002081b3L.U) //add
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c.io.ex_aluop1_source.expect(ALUOp1Source.Register)
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c.io.ex_aluop2_source.expect(ALUOp2Source.Register)
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c.clock.step()
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}
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}
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}
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