zzh/2025-yatcpu
1
0
Fork 0
mirror of https://github.com/handsomezhuzhu/2025-yatcpu.git synced 2026-02-20 20:10:14 +00:00
Code Issues Packages Projects Releases Wiki Activity

add mini-yatcpu

Browse Source
This commit is contained in:
TOKISAKIX\21168
2023-12-12 11:03:06 +08:00
parent fb1bf9d3f4
commit 73df6caf1c
133 changed files with 29085 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

35
mini-yatcpu/verilog/basys3/test.v Normal file
View File

@@ -0,0 +1,35 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2021/12/17 16:31:05
// Design Name:
// Module Name: test
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module test();
reg clock;
reg reset;
initial begin
clock = 0;
forever #1 clock = ~clock;
end
initial begin
reset = 1;
#2 reset = 0;
end
Top top(clock, reset);
endmodule

221
mini-yatcpu/verilog/pynq/TMDS_PLLVR.v Normal file
View File

@@ -0,0 +1,221 @@
// file: TMDS_PLLVR.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// __clkout__250.00000______0.000______50.0______200.536____237.727
// _clkoutd__100.00000______0.000______50.0______226.965____237.727
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary__________25.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "TMDS_PLLVR,clk_wiz_v6_0_5_0_0,{component_name=TMDS_PLLVR,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=2,clkin1_period=40.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=true}" *)
module TMDS_PLLVR
(
// Clock out ports
output clkout,
output clkoutd,
// Status and control signals
input reset,
output lock,
// Clock in ports
input clkin
);
TMDS_PLLVR_clk_wiz inst
(
// Clock out ports
.clkout(clkout),
.clkoutd(clkoutd),
// Status and control signals
.reset(reset),
.lock(lock),
// Clock in ports
.clk_in1(clkin)
);
endmodule
module TMDS_PLLVR_clk_wiz
(// Clock in ports
// Clock out ports
output clkout,
output clkoutd,
// Status and control signals
input reset,
output lock,
input clk_in1
);
// Input buffering
//------------------------------------
wire clk_in1_TMDS_PLLVR;
wire clk_in2_TMDS_PLLVR;
IBUF clkin1_ibufg
(.O (clk_in1_TMDS_PLLVR),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire clkout_TMDS_PLLVR;
wire clkoutd_TMDS_PLLVR;
wire clk_out3_TMDS_PLLVR;
wire clk_out4_TMDS_PLLVR;
wire clk_out5_TMDS_PLLVR;
wire clk_out6_TMDS_PLLVR;
wire clk_out7_TMDS_PLLVR;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire lock_int;
wire clkfbout_TMDS_PLLVR;
wire clkfbout_buf_TMDS_PLLVR;
wire clkfboutb_unused;
wire clkout2_unused;
wire clkout3_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
PLLE2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (40),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (4),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (10),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (40.000))
plle2_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_TMDS_PLLVR),
.CLKOUT0 (clkout_TMDS_PLLVR),
.CLKOUT1 (clkoutd_TMDS_PLLVR),
.CLKOUT2 (clkout2_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_TMDS_PLLVR),
.CLKIN1 (clk_in1_TMDS_PLLVR),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Other control and status signals
.LOCKED (lock_int),
.PWRDWN (1'b0),
.RST (reset_high));
assign reset_high = reset;
assign lock = lock_int;
// Clock Monitor clock assigning
//--------------------------------------
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_TMDS_PLLVR),
.I (clkfbout_TMDS_PLLVR));
BUFG clkout1_buf
(.O (clkout),
.I (clkout_TMDS_PLLVR));
BUFG clkout2_buf
(.O (clkoutd),
.I (clkoutd_TMDS_PLLVR));
endmodule

136
mini-yatcpu/verilog/pynq/design_1_wrapper.v Normal file
View File

@@ -0,0 +1,136 @@
//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
//Date : Thu Jun 9 10:53:21 2022
//Host : DESKTOP-UR8AHA2 running 64-bit major release (build 9200)
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
io_hdmi_clk_n,
io_hdmi_clk_p,
io_hdmi_data_n,
io_hdmi_data_p,
io_hdmi_hpdn,
io_led,
io_rx,
io_tx,
reset);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
output io_hdmi_clk_n;
output io_hdmi_clk_p;
output [2:0]io_hdmi_data_n;
output [2:0]io_hdmi_data_p;
output io_hdmi_hpdn;
output [3:0]io_led;
input io_rx;
output io_tx;
input reset;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire io_hdmi_clk_n;
wire io_hdmi_clk_p;
wire [2:0]io_hdmi_data_n;
wire [2:0]io_hdmi_data_p;
wire io_hdmi_hpdn;
wire [3:0]io_led;
wire io_rx;
wire io_tx;
wire reset;
design_1 design_1_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.io_hdmi_clk_n(io_hdmi_clk_n),
.io_hdmi_clk_p(io_hdmi_clk_p),
.io_hdmi_data_n(io_hdmi_data_n),
.io_hdmi_data_p(io_hdmi_data_p),
.io_hdmi_hpdn(io_hdmi_hpdn),
.io_led(io_led),
.io_rx(io_rx),
.io_tx(io_tx),
.reset(reset));
endmodule

35
mini-yatcpu/verilog/pynq/test.v Normal file
View File

@@ -0,0 +1,35 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2021/12/17 16:31:05
// Design Name:
// Module Name: test
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module test();
reg clock;
reg reset;
initial begin
clock = 0;
forever #1 clock = ~clock;
end
initial begin
reset = 1;
#2 reset = 0;
end
Top top(clock, reset);
endmodule

2102
mini-yatcpu/verilog/say_goodbye.asmbin.txt Normal file
View File

File diff suppressed because it is too large Load Diff

230
mini-yatcpu/verilog/verilator/sim_main.cpp Normal file
View File

@@ -0,0 +1,230 @@
#include <verilated.h>
#include <verilated_vcd_c.h>
#include <algorithm>
#include <fstream>
#include <iostream>
#include <string>
#include <memory>
#include <vector>
#include "VTop.h" // From Verilating "top.v"
class Memory {
std::vector<uint32_t> memory;
public:
Memory(size_t size) : memory(size, 0) {}
uint32_t read(size_t address) {
address = address / 4;
if (address >= memory.size()) {
printf("invalid read address 0x%08x\n", address * 4);
return 0;
}
return memory[address];
}
void write(size_t address, uint32_t value, bool write_strobe[4]) {
address = address / 4;
uint32_t write_mask = 0;
if (write_strobe[0]) write_mask |= 0x000000FF;
if (write_strobe[1]) write_mask |= 0x0000FF00;
if (write_strobe[2]) write_mask |= 0x00FF0000;
if (write_strobe[3]) write_mask |= 0xFF000000;
if (address >= memory.size()) {
printf("invalid write address 0x%08x\n", address * 4);
return;
}
memory[address] = (memory[address] & ~write_mask) | (value & write_mask);
}
void load_binary(std::string const& filename, size_t load_address = 0x1000) {
std::ifstream file(filename, std::ios::binary);
if (!file) {
throw std::runtime_error("Could not open file " + filename);
}
file.seekg(0, std::ios::end);
size_t size = file.tellg();
if (load_address + size > memory.size() * 4) {
throw std::runtime_error("File " + filename + " is too large (File is " +
std::to_string(size) + " bytes. Memory is " +
std::to_string(memory.size() * 4 - load_address) + " bytes.)");
}
file.seekg(0, std::ios::beg);
for (int i = 0; i < size / 4; ++i) {
file.read(reinterpret_cast<char*>(&memory[i + load_address / 4]),
sizeof(uint32_t));
}
}
};
class VCDTracer {
VerilatedVcdC* tfp = nullptr;
public:
void enable(std::string const& filename, VTop& top) {
Verilated::traceEverOn(true);
tfp = new VerilatedVcdC;
top.trace(tfp, 99);
tfp->open(filename.c_str());
tfp->set_time_resolution("1ps");
tfp->set_time_unit("1ns");
if (!tfp->isOpen()) {
throw std::runtime_error("Failed to open VCD dump file " + filename);
}
}
void dump(vluint64_t time) {
if (tfp) {
tfp->dump(time);
}
}
~VCDTracer() {
if (tfp) {
tfp->close();
delete tfp;
}
}
};
uint32_t parse_number(std::string const& str) {
if (str.size() > 2) {
auto&& prefix = str.substr(0, 2);
if (prefix == "0x" || prefix == "0X") {
return std::stoul(str.substr(2), nullptr, 16);
}
}
return std::stoul(str);
}
class Simulator {
vluint64_t main_time = 0;
vluint64_t max_sim_time = 10000;
uint32_t halt_address = 0;
size_t memory_words = 1024 * 1024; // 4MB
bool dump_vcd = false;
std::unique_ptr<VTop> top;
std::unique_ptr<VCDTracer> vcd_tracer;
std::unique_ptr<Memory> memory;
bool dump_signature = false;
unsigned long signature_begin, signature_end;
std::string signature_filename;
std::string instruction_filename;
public:
void parse_args(std::vector<std::string> const& args) {
if (auto it = std::find(args.begin(), args.end(), "-halt");
it != args.end()) {
halt_address = parse_number(*(it + 1));
}
if (auto it = std::find(args.begin(), args.end(), "-memory");
it != args.end()) {
memory_words = std::stoul(*(it + 1));
}
if (auto it = std::find(args.begin(), args.end(), "-time");
it != args.end()) {
max_sim_time = std::stoul(*(it + 1));
}
if (auto it = std::find(args.begin(), args.end(), "-vcd");
it != args.end()) {
vcd_tracer->enable(*(it + 1), *top);
}
if (auto it = std::find(args.begin(), args.end(), "-signature");
it != args.end()) {
dump_signature = true;
signature_begin = parse_number(*(it + 1));
signature_end = parse_number(*(it + 2));
signature_filename = *(it + 3);
}
if (auto it = std::find(args.begin(), args.end(), "-instruction");
it != args.end()) {
instruction_filename = *(it + 1);
}
}
Simulator(std::vector<std::string> const& args)
: top(std::make_unique<VTop>()),
vcd_tracer(std::make_unique<VCDTracer>()) {
parse_args(args);
memory = std::make_unique<Memory>(memory_words);
if (!instruction_filename.empty()) {
memory->load_binary(instruction_filename);
}
}
void run() {
top->reset = 1;
top->clock = 0;
top->io_mem_slave_read_valid = true;
top->eval();
vcd_tracer->dump(main_time);
uint32_t memory_read_word = 0;
bool memory_write_strobe[4] = {false};
bool uart_debounce = false;
while (main_time < max_sim_time && !Verilated::gotFinish()) {
++main_time;
if (main_time > 2) {
top->reset = 0;
}
top->io_mem_slave_read_data = memory_read_word;
top->clock = !top->clock;
top->eval();
if (top->io_uart_slave_write) {
if (uart_debounce && top->clock) {
std::cout << (char)top->io_uart_slave_write_data << std::flush;
}
if (!uart_debounce && top->clock) {
uart_debounce = true;
}
} else {
uart_debounce = false;
}
if (top->io_mem_slave_read) {
memory_read_word = memory->read(top->io_mem_slave_address);
}
if (top->io_mem_slave_write) {
memory_write_strobe[0] = top->io_mem_slave_write_strobe_0;
memory_write_strobe[1] = top->io_mem_slave_write_strobe_1;
memory_write_strobe[2] = top->io_mem_slave_write_strobe_2;
memory_write_strobe[3] = top->io_mem_slave_write_strobe_3;
memory->write(top->io_mem_slave_address, top->io_mem_slave_write_data,
memory_write_strobe);
}
vcd_tracer->dump(main_time);
if (halt_address) {
if (memory->read(halt_address) == 0xBABECAFE) {
break;
}
}
}
if (dump_signature) {
char data[9] = {0};
std::ofstream signature_file(signature_filename);
for (size_t addr = signature_begin; addr < signature_end; addr += 4) {
snprintf(data, 9, "%08x", memory->read(addr));
signature_file << data << std::endl;
}
}
}
~Simulator() {
if (top) {
top->final();
}
}
};
int main(int argc, char** argv) {
Verilated::commandArgs(argc, argv);
std::vector<std::string> args(argv, argv + argc);
Simulator simulator(args);
simulator.run();
return 0;
}

498
mini-yatcpu/verilog/z710/Top.anno.json Normal file
View File

@@ -0,0 +1,498 @@
[
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|AXI4LiteSlave",
"duplicate":"~Top|Top/uart:Uart/slave:AXI4LiteSlave",
"index":0.0
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/if2id:IF2ID/instruction:PipelineRegister",
"index":0.11842105263157894
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_1",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/if2id:IF2ID/instruction_address:PipelineRegister_1",
"index":0.13157894736842105
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_2",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/if2id:IF2ID/interrupt_flag:PipelineRegister_2",
"index":0.14473684210526316
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_3",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/instruction:PipelineRegister",
"index":0.18421052631578946
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_4",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/instruction_address:PipelineRegister_1",
"index":0.19736842105263158
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_5",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/regs_write_enable:PipelineRegister_5",
"index":0.21052631578947367
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_6",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/regs_write_address:PipelineRegister_6",
"index":0.2236842105263158
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_7",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/regs_write_source:PipelineRegister_7",
"index":0.23684210526315788
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_8",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/reg1_data:PipelineRegister_2",
"index":0.25
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_9",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/reg2_data:PipelineRegister_2",
"index":0.2631578947368421
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_10",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/immediate:PipelineRegister_2",
"index":0.27631578947368424
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_11",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/aluop1_source:PipelineRegister_5",
"index":0.2894736842105263
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_12",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/aluop2_source:PipelineRegister_5",
"index":0.3026315789473684
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_13",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/csr_write_enable:PipelineRegister_5",
"index":0.3157894736842105
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_15",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/memory_read_enable:PipelineRegister_5",
"index":0.34210526315789475
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_16",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/memory_write_enable:PipelineRegister_5",
"index":0.35526315789473684
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_17",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/csr_read_data:PipelineRegister_2",
"index":0.3684210526315789
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_18",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/regs_write_enable:PipelineRegister_5",
"index":0.4342105263157895
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_19",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/regs_write_source:PipelineRegister_7",
"index":0.4473684210526316
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_20",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/regs_write_address:PipelineRegister_6",
"index":0.4605263157894737
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_21",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/instruction_address:PipelineRegister_2",
"index":0.47368421052631576
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_22",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/instruction:PipelineRegister_2",
"index":0.4868421052631579
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_23",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/reg1_data:PipelineRegister_2",
"index":0.5
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_24",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/reg2_data:PipelineRegister_2",
"index":0.5131578947368421
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_25",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/alu_result:PipelineRegister_2",
"index":0.5263157894736842
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_26",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/memory_read_enable:PipelineRegister_5",
"index":0.5394736842105263
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_27",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/memory_write_enable:PipelineRegister_5",
"index":0.5526315789473685
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_28",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/csr_read_data:PipelineRegister_2",
"index":0.5657894736842105
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_29",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/alu_result:PipelineRegister_2",
"index":0.6052631578947368
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_30",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/memory_read_data:PipelineRegister_2",
"index":0.618421052631579
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_31",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/regs_write_enable:PipelineRegister_5",
"index":0.631578947368421
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_32",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/regs_write_source:PipelineRegister_7",
"index":0.6447368421052632
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_33",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/regs_write_address:PipelineRegister_6",
"index":0.6578947368421053
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_34",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/instruction_address:PipelineRegister_2",
"index":0.6710526315789473
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|PipelineRegister_35",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/csr_read_data:PipelineRegister_2",
"index":0.6842105263157895
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|AXI4LiteMaster",
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/axi4_master:AXI4LiteMaster",
"index":0.7631578947368421
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|AXI4LiteSlave_1",
"duplicate":"~Top|Top/mem:Memory/slave:AXI4LiteSlave_1",
"index":0.8289473684210527
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|AXI4LiteSlave_2",
"duplicate":"~Top|Top/timer:Timer/slave:AXI4LiteSlave",
"index":0.8552631578947368
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|AXI4LiteSlave_3",
"duplicate":"~Top|Top/dummy:DummySlave/slave:AXI4LiteSlave_1",
"index":0.881578947368421
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|AXI4LiteMaster_1",
"duplicate":"~Top|Top/bus_switch:BusSwitch/dummy:DummyMaster/master:AXI4LiteMaster",
"index":0.9210526315789473
},
{
"class":"firrtl.transforms.DedupedResult",
"original":"~Top|AXI4LiteMaster_2",
"duplicate":"~Top|Top/rom_loader:ROMLoader/master:AXI4LiteMaster",
"index":0.9736842105263158
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.AXI4LiteMaster.state",
"enumTypeName":"bus.AXI4LiteStates"
},
{
"class":"firrtl.annotations.MemorySynthInit$"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.AXI4LiteSlave_1.state",
"enumTypeName":"bus.AXI4LiteStates"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.AXI4LiteSlave.state",
"enumTypeName":"bus.AXI4LiteStates"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation",
"typeName":"riscv.core.fivestage.MEMAccessState",
"definition":{
"if_address_translate":1,
"if_access":4,
"idle":0,
"mem_address_translate":2,
"mem_access":3
}
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.CPU.mem_access_state",
"enumTypeName":"riscv.core.fivestage.MEMAccessState"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation",
"typeName":"riscv.core.fivestage.BUSGranted",
"definition":{
"mmu_if_granted":4,
"if_granted":1,
"mmu_mem_granted":3,
"mem_granted":2,
"idle":0
}
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.CPU.bus_granted",
"enumTypeName":"riscv.core.fivestage.BUSGranted"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation",
"typeName":"riscv.core.fivestage.MMUStates",
"definition":{
"checkpte1":2,
"gotPhyicalAddress":6,
"setADbit":5,
"idle":0,
"checkpte0":4,
"level1":1,
"level0":3
}
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.MMU.state",
"enumTypeName":"riscv.core.fivestage.MMUStates"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation",
"typeName":"riscv.core.fivestage.MemoryAccessStates",
"definition":{
"Idle":0,
"Read":1,
"Write":2,
"ReadWrite":3
}
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.MemoryAccess.mem_access_state",
"enumTypeName":"riscv.core.fivestage.MemoryAccessStates"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_33",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_31",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_29",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_27",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_25",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_23",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_21",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_17",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_15",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_13",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_11",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_9",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_7",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_5",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_3",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl._io_alu_funct_T_1",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALUControl.io_alu_funct",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation",
"typeName":"riscv.core.fivestage.ALUFunctions",
"definition":{
"sll":3,
"sra":9,
"or":6,
"xor":5,
"slt":4,
"sub":2,
"add":1,
"sltu":10,
"and":7,
"srl":8,
"zero":0
}
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.ALU.io_func",
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation",
"typeName":"riscv.core.fivestage.IFAccessStates",
"definition":{
"idle":0,
"read":1
}
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.InstructionFetch.state",
"enumTypeName":"riscv.core.fivestage.IFAccessStates"
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation",
"typeName":"bus.AXI4LiteStates",
"definition":{
"ReadData":2,
"WriteAddr":3,
"WriteResp":5,
"Idle":0,
"WriteData":4,
"ReadAddr":1
}
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation",
"typeName":"board.z710.BootStates",
"definition":{
"Init":0,
"Loading":1,
"BusWait":2,
"Finished":3
}
},
{
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
"target":"Top.Top.boot_state",
"enumTypeName":"board.z710.BootStates"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"verilog/z710"
},
{
"class":"firrtl.annotations.MemoryFileInlineAnnotation",
"target":"~Top|InstructionROM>mem",
"filename":"/workspaces/2023-fall-yatcpu-repo/mini-yatcpu/verilog/say_goodbye.asmbin.txt",
"hexOrBinary":"h"
}
]

4250
mini-yatcpu/verilog/z710/Top.fir Normal file
View File

File diff suppressed because it is too large Load Diff

7795
mini-yatcpu/verilog/z710/Top.v Normal file
View File

File diff suppressed because it is too large Load Diff

32
mini-yatcpu/verilog/z710/Top_reset.v Normal file
View File

@@ -0,0 +1,32 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/12/01 16:32:40
// Design Name:
// Module Name: Top_reset
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Top_reset(
input reset
);
initial begin
reset = 1;
#25 reset = 0;
end
endmodule

29
mini-yatcpu/verilog/z710/clock_control.v Normal file
View File

@@ -0,0 +1,29 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/11/29 15:52:55
// Design Name:
// Module Name: clock_control
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clock_control(
input clk_in,
input enable_clk,
output clk_out
);
assign clk_out = clk_in & enable_clk;
endmodule

459
mini-yatcpu/verilog/z710/design_1.bd Normal file
View File

@@ -0,0 +1,459 @@
{
"design": {
"design_info": {
"boundary_crc": "0xD2682A7282870375",
"device": "xc7z010clg400-1",
"name": "design_1",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "Hierarchical",
"tool_version": "2020.1",
"validated": "true"
},
"design_tree": {
"processing_system7_0": "",
"clock_control_0": "",
"xlconstant_0": "",
"Top_0": ""
},
"interface_ports": {
"DDR": {
"mode": "Master",
"vlnv": "xilinx.com:interface:ddrx_rtl:1.0",
"parameters": {
"CAN_DEBUG": {
"value": "false",
"value_src": "default"
},
"TIMEPERIOD_PS": {
"value": "1250",
"value_src": "default"
},
"MEMORY_TYPE": {
"value": "COMPONENTS",
"value_src": "default"
},
"DATA_WIDTH": {
"value": "8",
"value_src": "default"
},
"CS_ENABLED": {
"value": "true",
"value_src": "default"
},
"DATA_MASK_ENABLED": {
"value": "true",
"value_src": "default"
},
"SLOT": {
"value": "Single",
"value_src": "default"
},
"MEM_ADDR_MAP": {
"value": "ROW_COLUMN_BANK",
"value_src": "default"
},
"BURST_LENGTH": {
"value": "8",
"value_src": "default"
},
"AXI_ARBITRATION_SCHEME": {
"value": "TDM",
"value_src": "default"
},
"CAS_LATENCY": {
"value": "11",
"value_src": "default"
},
"CAS_WRITE_LATENCY": {
"value": "11",
"value_src": "default"
}
}
},
"FIXED_IO": {
"mode": "Master",
"vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0",
"parameters": {
"CAN_DEBUG": {
"value": "false",
"value_src": "default"
}
}
}
},
"ports": {
"io_clock": {
"type": "clk",
"direction": "I",
"parameters": {
"CLK_DOMAIN": {
"value": "design_1_clock",
"value_src": "default"
},
"FREQ_HZ": {
"value": "100000000"
},
"FREQ_TOLERANCE_HZ": {
"value": "0",
"value_src": "default"
},
"INSERT_VIP": {
"value": "0",
"value_src": "default"
},
"PHASE": {
"value": "0.000",
"value_src": "default"
}
}
},
"io_alive_led": {
"direction": "O"
},
"io_reset": {
"direction": "I",
"parameters": {
"POLARITY": {
"value": "",
"value_src": "weak"
}
}
},
"enable_clk": {
"type": "clk",
"direction": "I",
"parameters": {
"CLK_DOMAIN": {
"value": "design_1_enable_clk_0",
"value_src": "default"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "default"
},
"FREQ_TOLERANCE_HZ": {
"value": "0",
"value_src": "default"
},
"INSERT_VIP": {
"value": "0",
"value_src": "default"
},
"PHASE": {
"value": "0.000",
"value_src": "default"
}
}
}
},
"components": {
"processing_system7_0": {
"vlnv": "xilinx.com:ip:processing_system7:5.5",
"xci_name": "design_1_processing_system7_0_0",
"parameters": {
"PCW_ACT_APU_PERIPHERAL_FREQMHZ": {
"value": "666.666687"
},
"PCW_ACT_CAN_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_DCI_PERIPHERAL_FREQMHZ": {
"value": "10.158730"
},
"PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_ENET1_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": {
"value": "50.000000"
},
"PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": {
"value": "200.000000"
},
"PCW_ACT_QSPI_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_SDIO_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_SMC_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_SPI_PERIPHERAL_FREQMHZ": {
"value": "10.000000"
},
"PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": {
"value": "200.000000"
},
"PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_ACT_UART_PERIPHERAL_FREQMHZ": {
"value": "100.000000"
},
"PCW_ACT_WDT_PERIPHERAL_FREQMHZ": {
"value": "111.111115"
},
"PCW_CLK0_FREQ": {
"value": "50000000"
},
"PCW_CLK1_FREQ": {
"value": "10000000"
},
"PCW_CLK2_FREQ": {
"value": "10000000"
},
"PCW_CLK3_FREQ": {
"value": "10000000"
},
"PCW_DDR_RAM_HIGHADDR": {
"value": "0x1FFFFFFF"
},
"PCW_EN_EMIO_UART0": {
"value": "1"
},
"PCW_EN_UART0": {
"value": "1"
},
"PCW_EN_UART1": {
"value": "1"
},
"PCW_FPGA_FCLK0_ENABLE": {
"value": "1"
},
"PCW_MIO_48_IOTYPE": {
"value": "LVCMOS 3.3V"
},
"PCW_MIO_48_PULLUP": {
"value": "enabled"
},
"PCW_MIO_48_SLEW": {
"value": "slow"
},
"PCW_MIO_49_IOTYPE": {
"value": "LVCMOS 3.3V"
},
"PCW_MIO_49_PULLUP": {
"value": "enabled"
},
"PCW_MIO_49_SLEW": {
"value": "slow"
},
"PCW_MIO_TREE_PERIPHERALS": {
"value": "unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 1#UART 1#unassigned#unassigned#unassigned#unassigned"
},
"PCW_MIO_TREE_SIGNALS": {
"value": "unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#tx#rx#unassigned#unassigned#unassigned#unassigned"
},
"PCW_UART0_GRP_FULL_ENABLE": {
"value": "0"
},
"PCW_UART0_PERIPHERAL_ENABLE": {
"value": "1"
},
"PCW_UART0_UART0_IO": {
"value": "EMIO"
},
"PCW_UART1_GRP_FULL_ENABLE": {
"value": "0"
},
"PCW_UART1_PERIPHERAL_ENABLE": {
"value": "1"
},
"PCW_UART1_UART1_IO": {
"value": "MIO 48 .. 49"
},
"PCW_UART_PERIPHERAL_FREQMHZ": {
"value": "100"
},
"PCW_UART_PERIPHERAL_VALID": {
"value": "1"
},
"PCW_UIPARAM_ACT_DDR_FREQ_MHZ": {
"value": "533.333374"
},
"PCW_USE_M_AXI_GP0": {
"value": "0"
}
}
},
"clock_control_0": {
"vlnv": "xilinx.com:module_ref:clock_control:1.0",
"xci_name": "design_1_clock_control_0_0",
"reference_info": {
"ref_type": "hdl",
"ref_name": "clock_control",
"boundary_crc": "0x0"
},
"ports": {
"clk_in": {
"direction": "I",
"parameters": {
"CLK_DOMAIN": {
"value": "design_1_clock",
"value_src": "default_prop"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "user_prop"
},
"PHASE": {
"value": "0.000",
"value_src": "default_prop"
}
}
},
"enable_clk": {
"type": "clk",
"direction": "I",
"parameters": {
"CLK_DOMAIN": {
"value": "design_1_enable_clk_0",
"value_src": "default_prop"
}
}
},
"clk_out": {
"direction": "O",
"parameters": {
"CLK_DOMAIN": {
"value": "",
"value_src": "weak"
},
"FREQ_HZ": {
"value": "",
"value_src": "weak"
},
"PHASE": {
"value": "",
"value_src": "weak"
}
}
}
}
},
"xlconstant_0": {
"vlnv": "xilinx.com:ip:xlconstant:1.1",
"xci_name": "design_1_xlconstant_0_0"
},
"Top_0": {
"vlnv": "xilinx.com:module_ref:Top:1.0",
"xci_name": "design_1_Top_0_0",
"reference_info": {
"ref_type": "hdl",
"ref_name": "Top",
"boundary_crc": "0x0"
},
"ports": {
"clock": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_RESET": {
"value": "reset",
"value_src": "constant"
}
}
},
"reset": {
"type": "rst",
"direction": "I"
},
"io_led": {
"direction": "O"
},
"io_tx": {
"direction": "O"
},
"io_rx": {
"direction": "I"
}
}
}
},
"interface_nets": {
"processing_system7_0_DDR": {
"interface_ports": [
"DDR",
"processing_system7_0/DDR"
]
},
"processing_system7_0_FIXED_IO": {
"interface_ports": [
"FIXED_IO",
"processing_system7_0/FIXED_IO"
]
}
},
"nets": {
"Top_0_io_tx": {
"ports": [
"Top_0/io_tx",
"processing_system7_0/UART0_RX"
]
},
"Top_0_io_led": {
"ports": [
"Top_0/io_led",
"io_alive_led"
]
},
"io_reset_1": {
"ports": [
"io_reset",
"Top_0/reset"
]
},
"io_clock_1": {
"ports": [
"io_clock",
"clock_control_0/clk_in"
]
},
"enable_clk_0_1": {
"ports": [
"enable_clk",
"clock_control_0/enable_clk"
]
},
"clock_control_0_clk_out": {
"ports": [
"clock_control_0/clk_out",
"Top_0/clock"
]
},
"xlconstant_0_dout": {
"ports": [
"xlconstant_0/dout",
"Top_0/io_rx"
]
}
}
}
}

116
mini-yatcpu/verilog/z710/design_1_wrapper.v Normal file
View File

@@ -0,0 +1,116 @@
//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
//Date : Sun Dec 10 14:11:15 2023
//Host : Tokisakix running 64-bit major release (build 9200)
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
enable_clk,
io_alive_led,
io_clock,
io_reset);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
input enable_clk;
output io_alive_led;
input io_clock;
input io_reset;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire enable_clk;
wire io_alive_led;
wire io_clock;
wire io_reset;
design_1 design_1_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.enable_clk(enable_clk),
.io_alive_led(io_alive_led),
.io_clock(io_clock),
.io_reset(io_reset));
endmodule

28
mini-yatcpu/verilog/z710/pass_through.v Normal file
View File

@@ -0,0 +1,28 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/11/29 16:38:00
// Design Name:
// Module Name: pass_through
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pass_through(
input in,
output out
);
assign out = in;
endmodule

35
mini-yatcpu/verilog/z710/test.v Normal file
View File

@@ -0,0 +1,35 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2021/12/17 16:31:05
// Design Name:
// Module Name: test
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module test();
reg clock;
reg reset;
initial begin
clock = 0;
forever #1 clock = ~clock;
end
initial begin
reset = 1;
#2 reset = 0;
end
Top top(clock, reset);
endmodule

47
mini-yatcpu/verilog/z710/top_test.v Normal file
View File

@@ -0,0 +1,47 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/12/01 15:46:54
// Design Name:
// Module Name: top_test
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top_test(
);
reg clock;
reg reset;
reg constant_zero = 1'b0;
wire io_led, io_tx;
localparam CLK_PERIOD = 20;
initial begin
clock = 1'b0;
forever #( CLK_PERIOD / 2 ) clock = ~clock;
end
initial begin
reset = 1; // need a down edge to init all components
#21 reset = 0; // NOTE!!: must happen together with clock down edge!
end
Top mytop(clock, reset, io_led, io_tx, constant_zero);
endmodule

30
mini-yatcpu/verilog/z710/uart_control.v Normal file
View File

@@ -0,0 +1,30 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/11/30 00:51:08
// Design Name:
// Module Name: uart_control
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module uart_control(
input enable_uart,
input tx_in,
output tx_out
);
assign tx_out = (enable_uart) ? tx_in : 1'h1;
endmodule