diff --git a/README.md b/README.md index 84a9b54..fbf5f63 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,8 @@ # YatCPU -本仓库由 [Tokisakix](https://github.com/Tokisakix)、[PurplePower](https://github.com/PurplePower)、[Han Huang](https://github.com/HHTheBest) 在 [2022-fall-yatcpu-repo](https://github.com/hrpccs/2022-fall-yatcpu-repo) 的基础上结合 2023 机组教学实情整理而来 +本仓库由 [Tokisakix](https://github.com/Tokisakix)、[PurplePower](https://github.com/PurplePower)、[Han Huang](https://github.com/HHTheBest) 在 [2022-fall-yatcpu-repo](https://github.com/hrpccs/2022-fall-yatcpu-repo) 的基础上结合 2023 机组教学实情整理而来，有较多原创内容 + +(PS: 能求个 star⭐ 吗 QAQ ~) ## 为什么需要本仓库？ @@ -68,6 +70,9 @@ 2. **使用一键烧板脚本** > 此烧板脚本对任意方式配置的开发环境都有效，因为 vivado 的烧板跟开发环境是**相互独立**的，如果你使用 Dev Container 或 WSL 配置环境，你需要回到 Windows 下打开 PowerShell 进行烧板。 + > **此部分内容借鉴自 [YatCPU 的烧板验证](https://yatcpu.sysu.tech/getting-started/program-device/)** + + 原则上你可以在任意一个 lab 文件夹中使用下方的脚本进行烧板，下方的演示路径为 2023-fall-yatcpu-repo/mini-yatcpu/ **生成 Verilog 文件** @@ -113,6 +118,4 @@ ## 外部参考链接 - [YatCPU 文档地址](https://yatcpu.sysu.tech) - [YatCPU 的 Dev Container 环境配置](http://tokisakix.cn/2023/11/14/%5BDocker%5D%20YatCPU%20%E7%9A%84%20Dev%20container%20%E7%8E%AF%E5%A2%83%E9%85%8D%E7%BD%AE/) -- [测试 Tokisakix 的烧板文件](https://blog.skyw.cc/archives/258.html) - -(PS: 能求个 star⭐ 吗 QAQ ~) +- [测试 Tokisakix 的烧板文件](https://blog.skyw.cc/archives/258.html) \ No newline at end of file diff --git a/mini-yatcpu/.gitignore b/mini-yatcpu/.gitignore new file mode 100644 index 0000000..c89f31f --- /dev/null +++ b/mini-yatcpu/.gitignore @@ -0,0 +1,353 @@ +### Project Specific stuff +.sbt +.cache +test_run_dir/* +**/__pycache__ +**/riscof_work +### XilinxISE template +# intermediate build files +*.bgn +*.bit +*.bld +*.cmd_log +*.drc +*.ll +*.lso +*.msd +*.msk +*.ncd +*.ngc +*.ngd +*.ngr +*.pad +*.par +*.pcf +*.prj +*.ptwx +*.rbb +*.rbd +*.stx +*.syr +*.twr +*.twx +*.unroutes +*.ut +*.xpi +*.xst +*_bitgen.xwbt +*_envsettings.html +*_map.map +*_map.mrp +*_map.ngm +*_map.xrpt +*_ngdbuild.xrpt +*_pad.csv +*_pad.txt +*_par.xrpt +*_summary.html +*_summary.xml +*_usage.xml +*_xst.xrpt + +# project-wide generated files +*.gise +par_usage_statistics.html +usage_statistics_webtalk.html +webtalk.log +webtalk_pn.xml + +# generated folders +iseconfig/ +xlnx_auto_0_xdb/ +xst/ +_ngo/ +_xmsgs/ +### Eclipse template +*.pydevproject +.metadata +.gradle +bin/ +tmp/ +*.tmp +*.bak +*.swp +*~.nib +local.properties +.settings/ +.loadpath + +# Eclipse Core +.project + +# External tool builders +.externalToolBuilders/ + +# Locally stored "Eclipse launch configurations" +*.launch + +# CDT-specific +.cproject + +# JDT-specific (Eclipse Java Development Tools) +.classpath + +# Java annotation processor (APT) +.factorypath + +# PDT-specific +.buildpath + +# sbteclipse plugin +.target + +# TeXlipse plugin +.texlipse +### C template +# Object files +*.o +*.ko +*.obj +*.elf + +# Precompiled Headers +*.gch +*.pch + +# Libraries +*.lib +*.a +*.la +*.lo + +# Shared objects (inc. Windows DLLs) +*.dll +*.so +*.so.* +*.dylib + +# Executables +*.exe +*.out +*.app +*.i*86 +*.x86_64 +*.hex + +# Debug files +*.dSYM/ +### SBT template +# Simple Build Tool +# http://www.scala-sbt.org/release/docs/Getting-Started/Directories.html#configuring-version-control + +target/ +lib_managed/ +src_managed/ +project/boot/ +.history +.cache +### Emacs template +# -*- mode: gitignore; -*- +*~ +\#*\# +/.emacs.desktop +/.emacs.desktop.lock +*.elc +auto-save-list +tramp +.\#* + +# Org-mode +.org-id-locations +*_archive + +# flymake-mode +*_flymake.* + +# eshell files +/eshell/history +/eshell/lastdir + +# elpa packages +/elpa/ + +# reftex files +*.rel + +# AUCTeX auto folder +/auto/ + +# cask packages +.cask/ +### Vim template +[._]*.s[a-w][a-z] +[._]s[a-w][a-z] +*.un~ +Session.vim +.netrwhist +*~ +### JetBrains template +# Covers JetBrains IDEs: IntelliJ, RubyMine, PhpStorm, AppCode, PyCharm, CLion, Android Studio + +*.iml + +## Directory-based project format: +.idea/ +# if you remove the above rule, at least ignore the following: + +# User-specific stuff: +# .idea/workspace.xml +# .idea/tasks.xml +# .idea/dictionaries + +# Sensitive or high-churn files: +# .idea/dataSources.ids +# .idea/dataSources.xml +# .idea/sqlDataSources.xml +# .idea/dynamic.xml +# .idea/uiDesigner.xml + +# Gradle: +# .idea/gradle.xml +# .idea/libraries + +# Mongo Explorer plugin: +# .idea/mongoSettings.xml + +## File-based project format: +*.ipr +*.iws + +## Plugin-specific files: + +# IntelliJ +/out/ + +# mpeltonen/sbt-idea plugin +.idea_modules/ + +# JIRA plugin +atlassian-ide-plugin.xml + +# Crashlytics plugin (for Android Studio and IntelliJ) +com_crashlytics_export_strings.xml +crashlytics.properties +crashlytics-build.properties +### C++ template +# Compiled Object files +*.slo +*.lo +*.o +*.obj + +# Precompiled Headers +*.gch +*.pch + +# Compiled Dynamic libraries +*.so +*.dylib +*.dll + +# Fortran module files +*.mod + +# Compiled Static libraries +*.lai +*.la +*.a +*.lib + +# Executables +*.exe +*.out +*.app +### OSX template +.DS_Store +.AppleDouble +.LSOverride + +# Icon must end with two \r +Icon + +# Thumbnails +._* + +# Files that might appear in the root of a volume +.DocumentRevisions-V100 +.fseventsd +.Spotlight-V100 +.TemporaryItems +.Trashes +.VolumeIcon.icns + +# Directories potentially created on remote AFP share +.AppleDB +.AppleDesktop +Network Trash Folder +Temporary Items +.apdisk +### Xcode template +# Xcode +# +# gitignore contributors: remember to update Global/Xcode.gitignore, Objective-C.gitignore & Swift.gitignore + +## Build generated +build/ +DerivedData + +## Various settings +*.pbxuser +!default.pbxuser +*.mode1v3 +!default.mode1v3 +*.mode2v3 +!default.mode2v3 +*.perspectivev3 +!default.perspectivev3 +xcuserdata + +## Other +*.xccheckout +*.moved-aside +*.xcuserstate +### Scala template +*.class +*.log +/.bsp + +# sbt specific +.cache +.history +.lib/ +dist/* +target/ +lib_managed/ +src_managed/ +project/boot/ +project/plugins/project/ + +# Scala-IDE specific +.scala_dependencies +.worksheet +### Java template +*.class + +# Mobile Tools for Java (J2ME) +.mtj.tmp/ + +# Package Files # +*.jar +*.war +*.ear + +# virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml +hs_err_pid* + +*.jou +*.log +.Xil +vivado/basys3/riscv-basys3 +vivado/pynq/riscv-pynq +vivado/pynq/NA +.vscode +.metals diff --git a/mini-yatcpu/Makefile b/mini-yatcpu/Makefile new file mode 100644 index 0000000..7cd805c --- /dev/null +++ b/mini-yatcpu/Makefile @@ -0,0 +1,61 @@ +# Copyright 2021 Howard Lau +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +test: + sbt test + +verilator: + sbt "runMain board.verilator.VerilogGenerator" + cd verilog/verilator && verilator --trace --exe --cc sim_main.cpp Top.v && make -C obj_dir -f VTop.mk + +verilator-sim: verilator + cd verilog/verilator && obj_dir/VTop $(SIM_TIME) + +basys3: + sbt "runMain board.basys3.VerilogGenerator" + +pynq: + sbt "runMain board.pynq.VerilogGenerator" + +z710: + sbt "runMain board.z710.VerilogGenerator" + +bitstream-basys3: basys3 + cd vivado/basys3 && vivado -mode batch -source generate_bitstream.tcl + +program-basys3: bitstream-basys3 + cd vivado/basys3 && vivado -mode batch -source program_device.tcl + +vivado-sim-basys3: basys3 + cd vivado/basys3 && vivado -mode batch -source run_simulation.tcl + +bitstream-pynq: pynq + cd vivado/pynq && vivado -mode batch -source generate_bitstream.tcl + +program-pynq: bitstream-pynq + cd vivado/pynq && vivado -mode batch -source program_device.tcl + +vivado-sim-pynq: pynq + cd vivado/pynq && vivado -mode batch -source run_simulation.tcl + +bitstream-z710: z710 + cd vivado/z710 && vivado -mode batch -source generate_bitstream.tcl + +program-z710: bitstream-z710 + cd vivado/z710 && vivado -mode batch -source program_device.tcl + +vivado-sim-z710: z710 + cd vivado/z710 && vivado -mode batch -source run_simulation.tcl + +.PHONY: basys3 verilator z710 test bitstream program verilator-sim vivado-sim diff --git a/mini-yatcpu/build.sbt b/mini-yatcpu/build.sbt new file mode 100644 index 0000000..75f138e --- /dev/null +++ b/mini-yatcpu/build.sbt @@ -0,0 +1,24 @@ +import sbt.Keys.libraryDependencies +// See README.md for license details. + +ThisBuild / scalaVersion := "2.13.10" +ThisBuild / version := "0.1.0" +ThisBuild / organization := "io.github.howardlau1999" + +val chiselVersion = "3.6.0" + +lazy val root = (project in file(".")) + .settings( + name := "yatcpu", + libraryDependencies ++= Seq( + "edu.berkeley.cs" %% "chisel3" % chiselVersion, + "edu.berkeley.cs" %% "chiseltest" % "0.6.0" % "test", + ), + scalacOptions ++= Seq( + "-language:reflectiveCalls", + "-deprecation", + "-feature", + "-Xcheckinit", + ), + addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full), + ) diff --git a/mini-yatcpu/project/build.properties b/mini-yatcpu/project/build.properties new file mode 100644 index 0000000..303541e --- /dev/null +++ b/mini-yatcpu/project/build.properties @@ -0,0 +1 @@ +sbt.version = 1.9.6 diff --git a/mini-yatcpu/project/plugins.sbt b/mini-yatcpu/project/plugins.sbt new file mode 100644 index 0000000..5708f81 --- /dev/null +++ b/mini-yatcpu/project/plugins.sbt @@ -0,0 +1 @@ +logLevel := Level.Warn diff --git a/mini-yatcpu/src/main/resources/fibonacci.asmbin b/mini-yatcpu/src/main/resources/fibonacci.asmbin new file mode 100644 index 0000000..91f7740 Binary files /dev/null and b/mini-yatcpu/src/main/resources/fibonacci.asmbin differ diff --git a/mini-yatcpu/src/main/resources/hello.asmbin b/mini-yatcpu/src/main/resources/hello.asmbin new file mode 100644 index 0000000..27a4e32 Binary files /dev/null and b/mini-yatcpu/src/main/resources/hello.asmbin differ diff --git a/mini-yatcpu/src/main/resources/litenes.asmbin b/mini-yatcpu/src/main/resources/litenes.asmbin new file mode 100644 index 0000000..5cf9d43 Binary files /dev/null and b/mini-yatcpu/src/main/resources/litenes.asmbin differ diff --git a/mini-yatcpu/src/main/resources/mmio.asmbin b/mini-yatcpu/src/main/resources/mmio.asmbin new file mode 100644 index 0000000..22cc8f4 Binary files /dev/null and b/mini-yatcpu/src/main/resources/mmio.asmbin differ diff --git a/mini-yatcpu/src/main/resources/paging.asmbin b/mini-yatcpu/src/main/resources/paging.asmbin new file mode 100644 index 0000000..45011d8 Binary files /dev/null and b/mini-yatcpu/src/main/resources/paging.asmbin differ diff --git a/mini-yatcpu/src/main/resources/quicksort.asmbin b/mini-yatcpu/src/main/resources/quicksort.asmbin new file mode 100644 index 0000000..60d10f4 Binary files /dev/null and b/mini-yatcpu/src/main/resources/quicksort.asmbin differ diff --git a/mini-yatcpu/src/main/resources/say_goodbye.asmbin b/mini-yatcpu/src/main/resources/say_goodbye.asmbin new file mode 100644 index 0000000..ec5153e Binary files /dev/null and b/mini-yatcpu/src/main/resources/say_goodbye.asmbin differ diff --git a/mini-yatcpu/src/main/resources/sb.asmbin b/mini-yatcpu/src/main/resources/sb.asmbin new file mode 100644 index 0000000..fde0216 Binary files /dev/null and b/mini-yatcpu/src/main/resources/sb.asmbin differ diff --git a/mini-yatcpu/src/main/resources/tetris.asmbin b/mini-yatcpu/src/main/resources/tetris.asmbin new file mode 100644 index 0000000..fdeaeda Binary files /dev/null and b/mini-yatcpu/src/main/resources/tetris.asmbin differ diff --git a/mini-yatcpu/src/main/resources/tetris_mmu.asmbin b/mini-yatcpu/src/main/resources/tetris_mmu.asmbin new file mode 100644 index 0000000..fe350f0 Binary files /dev/null and b/mini-yatcpu/src/main/resources/tetris_mmu.asmbin differ diff --git a/mini-yatcpu/src/main/resources/vga_font_8x16.bmp b/mini-yatcpu/src/main/resources/vga_font_8x16.bmp new file mode 100644 index 0000000..1aa58b9 Binary files /dev/null and b/mini-yatcpu/src/main/resources/vga_font_8x16.bmp differ diff --git a/mini-yatcpu/src/main/scala/board/basys3/BCD2Segments.scala b/mini-yatcpu/src/main/scala/board/basys3/BCD2Segments.scala new file mode 100644 index 0000000..08d1c74 --- /dev/null +++ b/mini-yatcpu/src/main/scala/board/basys3/BCD2Segments.scala @@ -0,0 +1,52 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package board.basys3 + +import chisel3._ +import chisel3.util._ + +class BCD2Segments extends Module { + val io = IO(new Bundle { + val bcd = Input(UInt(4.W)) + val segs = Output(UInt(8.W)) + }) + + val bcd = io.bcd + val segs = Wire(UInt(8.W)) + + segs := MuxLookup(bcd, 0xFF.U)( + IndexedSeq( + 0.U -> "b10000001".U, + 1.U -> "b11001111".U, + 2.U -> "b10010010".U, + 3.U -> "b10000110".U, + 4.U -> "b11001100".U, + 5.U -> "b10100100".U, + 6.U -> "b10100000".U, + 7.U -> "b10001111".U, + 8.U -> "b10000000".U, + 9.U -> "b10000100".U, + 10.U -> "b00001000".U, + 11.U -> "b01100000".U, + 12.U -> "b00110001".U, + 13.U -> "b01000010".U, + 14.U -> "b00110000".U, + 15.U -> "b00111000".U, + ) + ) + + io.segs := segs +} + diff --git a/mini-yatcpu/src/main/scala/board/basys3/OnboardDigitDisplay.scala b/mini-yatcpu/src/main/scala/board/basys3/OnboardDigitDisplay.scala new file mode 100644 index 0000000..a07819b --- /dev/null +++ b/mini-yatcpu/src/main/scala/board/basys3/OnboardDigitDisplay.scala @@ -0,0 +1,32 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package board.basys3 + +import chisel3._ + +class OnboardDigitDisplay extends Module { + val io = IO(new Bundle { + val digit_mask = Output(UInt(4.W)) + }) + + val counter = RegInit(UInt(16.W), 0.U) + val digit_mask = RegInit(UInt(4.W), "b0111".U) + + counter := counter + 1.U + when(counter === 0.U) { + digit_mask := (digit_mask << 1.U).asUInt + digit_mask(3) + } + io.digit_mask := digit_mask +} diff --git a/mini-yatcpu/src/main/scala/board/basys3/SYSULogo.scala b/mini-yatcpu/src/main/scala/board/basys3/SYSULogo.scala new file mode 100644 index 0000000..7268a01 --- /dev/null +++ b/mini-yatcpu/src/main/scala/board/basys3/SYSULogo.scala @@ -0,0 +1,33 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package board.basys3 + +import chisel3._ +import chisel3.util._ + +class SYSULogo extends Module { + val io = IO(new Bundle { + val digit_mask = Input(UInt(4.W)) + val segs = Output(UInt(8.W)) + }) + + io.segs := MuxLookup(io.digit_mask, "b00100100".U)( + // "b0111".U, "b1101".U -> S + IndexedSeq( + "b1011".U -> "b01000100".U, // Y + "b1110".U -> "b01000001".U, // U + ) + ) +} diff --git a/mini-yatcpu/src/main/scala/board/basys3/SegmentMux.scala b/mini-yatcpu/src/main/scala/board/basys3/SegmentMux.scala new file mode 100644 index 0000000..5fac786 --- /dev/null +++ b/mini-yatcpu/src/main/scala/board/basys3/SegmentMux.scala @@ -0,0 +1,41 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package board.basys3 + +import chisel3._ +import chisel3.util._ + +class SegmentMux extends Module { + val io = IO(new Bundle { + val digit_mask = Input(UInt(4.W)) + val numbers = Input(UInt(16.W)) + val segs = Output(UInt(8.W)) + }) + + + val digit = RegInit(UInt(4.W), 0.U) + val bcd2segs = Module(new BCD2Segments) + + bcd2segs.io.bcd := digit + io.segs := bcd2segs.io.segs + digit := MuxLookup(io.digit_mask, io.numbers(3, 0))( + // "b1110".U + IndexedSeq( + "b1101".U -> io.numbers(7, 4), + "b1011".U -> io.numbers(11, 8), + "b0111".U -> io.numbers(15, 12) + ) + ) +} diff --git a/mini-yatcpu/src/main/scala/board/basys3/Top.scala b/mini-yatcpu/src/main/scala/board/basys3/Top.scala new file mode 100644 index 0000000..d35077f --- /dev/null +++ b/mini-yatcpu/src/main/scala/board/basys3/Top.scala @@ -0,0 +1,142 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package board.basys3 + +import bus.{BusArbiter, BusSwitch} +import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage} +import chisel3.util._ +import chisel3.{ChiselEnum, _} +import peripheral._ +import riscv._ +import riscv.core.CPU + +object BootStates extends ChiselEnum { + val Init, Loading, Finished = Value +} + +class Top extends Module { + val binaryFilename = "tetris.asmbin" + val io = IO(new Bundle { + val switch = Input(UInt(16.W)) + + val segs = Output(UInt(8.W)) + val digit_mask = Output(UInt(4.W)) + + val hsync = Output(Bool()) + val vsync = Output(Bool()) + val rgb = Output(UInt(12.W)) + val led = Output(UInt(16.W)) + + val tx = Output(Bool()) + val rx = Input(Bool()) + }) + val boot_state = RegInit(BootStates.Init) + + val uart = Module(new Uart(100000000, 115200)) + io.tx := uart.io.txd + uart.io.rxd := io.rx + + val cpu = Module(new CPU) + val mem = Module(new Memory(Parameters.MemorySizeInWords)) + val timer = Module(new Timer) + val dummy = Module(new DummySlave) + val bus_arbiter = Module(new BusArbiter) + val bus_switch = Module(new BusSwitch) + + val instruction_rom = Module(new InstructionROM(binaryFilename)) + val rom_loader = Module(new ROMLoader(instruction_rom.capacity)) + + val vga_display = Module(new VGADisplay) + vga_display.io.rgb := 0.U + bus_arbiter.io.bus_request(0) := true.B + + bus_switch.io.master <> cpu.io.axi4_channels + bus_switch.io.address := cpu.io.bus_address + for (i <- 0 until Parameters.SlaveDeviceCount) { + bus_switch.io.slaves(i) <> dummy.io.channels + } + rom_loader.io.load_address := Parameters.EntryAddress + rom_loader.io.load_start := false.B + rom_loader.io.rom_data := instruction_rom.io.data + instruction_rom.io.address := rom_loader.io.rom_address + cpu.io.stall_flag_bus := true.B + cpu.io.instruction_valid := false.B + bus_switch.io.slaves(0) <> mem.io.channels + rom_loader.io.channels <> dummy.io.channels + switch(boot_state) { + is(BootStates.Init) { + rom_loader.io.load_start := true.B + boot_state := BootStates.Loading + rom_loader.io.channels <> mem.io.channels + } + is(BootStates.Loading) { + rom_loader.io.load_start := false.B + rom_loader.io.channels <> mem.io.channels + when(rom_loader.io.load_finished) { + boot_state := BootStates.Finished + } + } + is(BootStates.Finished) { + cpu.io.stall_flag_bus := false.B + cpu.io.instruction_valid := true.B + } + } + val display = Module(new CharacterDisplay) + bus_switch.io.slaves(1) <> display.io.channels + bus_switch.io.slaves(2) <> uart.io.channels + bus_switch.io.slaves(4) <> timer.io.channels + + cpu.io.interrupt_flag := Cat(uart.io.signal_interrupt, timer.io.signal_interrupt) + + cpu.io.debug_read_address := 0.U + mem.io.debug_read_address := 0.U + + io.hsync := vga_display.io.hsync + io.vsync := vga_display.io.vsync + + display.io.x := vga_display.io.x + display.io.y := vga_display.io.y + display.io.video_on := vga_display.io.video_on + + io.rgb := display.io.rgb + + mem.io.debug_read_address := io.switch(15, 1).asUInt << 2 + io.led := Mux( + io.switch(0), + mem.io.debug_read_data(31, 16).asUInt, + mem.io.debug_read_data(15, 0).asUInt, + ) + + val onboard_display = Module(new OnboardDigitDisplay) + io.digit_mask := onboard_display.io.digit_mask + + val sysu_logo = Module(new SYSULogo) + sysu_logo.io.digit_mask := io.digit_mask + + val seg_mux = Module(new SegmentMux) + seg_mux.io.digit_mask := io.digit_mask + seg_mux.io.numbers := io.led + + io.segs := MuxLookup(io.switch, seg_mux.io.segs)( + IndexedSeq( + 0.U -> sysu_logo.io.segs + ) + ) +} + +object VerilogGenerator extends App { + (new ChiselStage).execute(Array("-X", "verilog", "-td", "verilog/basys3"), Seq(ChiselGeneratorAnnotation(() => new + Top))) +} \ No newline at end of file diff --git a/mini-yatcpu/src/main/scala/board/pynq/Top.scala b/mini-yatcpu/src/main/scala/board/pynq/Top.scala new file mode 100644 index 0000000..17674c5 --- /dev/null +++ b/mini-yatcpu/src/main/scala/board/pynq/Top.scala @@ -0,0 +1,149 @@ +// Copyright 2022 Canbin Huang +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package board.pynq + +import bus.{AXI4LiteChannels, AXI4LiteInterface, BusArbiter, BusSwitch} +import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage} +import chisel3.util.{is, switch} +import chisel3.{ChiselEnum, _} +import peripheral._ +import riscv.Parameters +import riscv.core.CPU + +object BootStates extends ChiselEnum { + val Init, Loading, BusWait, Finished = Value +} + +class Top extends Module { + val binaryFilename = "litenes.asmbin" + val io = IO(new Bundle() { + val hdmi_clk_n = Output(Bool()) + val hdmi_clk_p = Output(Bool()) + val hdmi_data_n = Output(UInt(3.W)) + val hdmi_data_p = Output(UInt(3.W)) + val hdmi_hpdn = Output(Bool()) + + val axi_mem = new AXI4LiteInterface(32, 32) + + val tx = Output(Bool()) + val rx = Input(Bool()) + + val led = Output(UInt(4.W)) + }) + val boot_state = RegInit(BootStates.Init) + io.led := boot_state.asUInt + val uart = Module(new Uart(125000000, 115200)) + io.tx := uart.io.txd + uart.io.rxd := io.rx + + val cpu = Module(new CPU) + val mem = Wire(new AXI4LiteChannels(32, 32)) + val timer = Module(new Timer) + val dummy = Module(new DummySlave) + val bus_arbiter = Module(new BusArbiter) + val bus_switch = Module(new BusSwitch) + mem.write_address_channel.AWADDR <> io.axi_mem.AWADDR + mem.write_address_channel.AWPROT <> io.axi_mem.AWPROT + mem.write_address_channel.AWREADY <> io.axi_mem.AWREADY + mem.write_address_channel.AWVALID <> io.axi_mem.AWVALID + mem.read_address_channel.ARADDR <> io.axi_mem.ARADDR + mem.read_address_channel.ARPROT <> io.axi_mem.ARPROT + mem.read_address_channel.ARREADY <> io.axi_mem.ARREADY + mem.read_address_channel.ARVALID <> io.axi_mem.ARVALID + mem.read_data_channel.RDATA <> io.axi_mem.RDATA + mem.read_data_channel.RVALID <> io.axi_mem.RVALID + mem.read_data_channel.RRESP <> io.axi_mem.RRESP + mem.read_data_channel.RREADY <> io.axi_mem.RREADY + mem.write_data_channel.WDATA <> io.axi_mem.WDATA + mem.write_data_channel.WVALID <> io.axi_mem.WVALID + mem.write_data_channel.WSTRB <> io.axi_mem.WSTRB + mem.write_data_channel.WREADY <> io.axi_mem.WREADY + mem.write_response_channel.BVALID <> io.axi_mem.BVALID + mem.write_response_channel.BRESP <> io.axi_mem.BRESP + mem.write_response_channel.BREADY <> io.axi_mem.BREADY + + val instruction_rom = Module(new InstructionROM(binaryFilename)) + val rom_loader = Module(new ROMLoader(instruction_rom.capacity)) + + val hdmi_display = Module(new HDMIDisplay) + bus_arbiter.io.bus_request(0) := true.B + + bus_switch.io.master <> cpu.io.axi4_channels + bus_switch.io.address := cpu.io.bus_address + for (i <- 0 until Parameters.SlaveDeviceCount) { + bus_switch.io.slaves(i) <> dummy.io.channels + } + rom_loader.io.load_address := Parameters.EntryAddress + rom_loader.io.load_start := false.B + rom_loader.io.rom_data := instruction_rom.io.data + instruction_rom.io.address := rom_loader.io.rom_address + cpu.io.stall_flag_bus := true.B + cpu.io.instruction_valid := false.B + rom_loader.io.channels <> dummy.io.channels + bus_switch.io.slaves(0) <> mem + switch(boot_state) { + is(BootStates.Init) { + rom_loader.io.load_start := true.B + boot_state := BootStates.Loading + rom_loader.io.channels <> mem + bus_switch.io.slaves(0) <> dummy.io.channels + } + is(BootStates.Loading) { + rom_loader.io.load_start := false.B + rom_loader.io.channels <> mem + bus_switch.io.slaves(0) <> dummy.io.channels + when(rom_loader.io.load_finished) { + boot_state := BootStates.BusWait + } + } + is(BootStates.BusWait) { + when(!cpu.io.bus_busy) { + boot_state := BootStates.Finished + } + } + is(BootStates.Finished) { + cpu.io.stall_flag_bus := false.B + cpu.io.instruction_valid := true.B + rom_loader.io.channels <> dummy.io.channels + bus_switch.io.slaves(0) <> mem + } + } + + val display = Module(new PixelDisplay) + bus_switch.io.slaves(1) <> display.io.channels + bus_switch.io.slaves(2) <> uart.io.channels + bus_switch.io.slaves(4) <> timer.io.channels + + cpu.io.interrupt_flag := uart.io.signal_interrupt ## timer.io.signal_interrupt + io.led := uart.io.signal_interrupt ## timer.io.signal_interrupt ## boot_state.asUInt + + cpu.io.debug_read_address := 0.U + + display.io.x := hdmi_display.io.x_next + display.io.y := hdmi_display.io.y_next + display.io.video_on := hdmi_display.io.video_on + hdmi_display.io.rgb := display.io.rgb + + io.hdmi_hpdn := 1.U + io.hdmi_data_n := hdmi_display.io.TMDSdata_n + io.hdmi_data_p := hdmi_display.io.TMDSdata_p + io.hdmi_clk_n := hdmi_display.io.TMDSclk_n + io.hdmi_clk_p := hdmi_display.io.TMDSclk_p +} + +object VerilogGenerator extends App { + (new ChiselStage).execute(Array("-X", "verilog", "-td", "verilog/pynq"), Seq(ChiselGeneratorAnnotation(() => new + Top))) +} \ No newline at end of file diff --git a/mini-yatcpu/src/main/scala/board/verilator/Top.scala b/mini-yatcpu/src/main/scala/board/verilator/Top.scala new file mode 100644 index 0000000..4e3e7c1 --- /dev/null +++ b/mini-yatcpu/src/main/scala/board/verilator/Top.scala @@ -0,0 +1,71 @@ +// Copyright 2022 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package board.verilator + +import bus.{AXI4LiteSlave, AXI4LiteSlaveBundle, BusArbiter, BusSwitch} +import chisel3._ +import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage} +import peripheral.DummySlave +import riscv.Parameters +import riscv.core.CPU + +class Top extends Module { + + val io = IO(new Bundle { + val signal_interrupt = Input(Bool()) + + val mem_slave = new AXI4LiteSlaveBundle(Parameters.AddrBits, Parameters.DataBits) + val uart_slave = new AXI4LiteSlaveBundle(Parameters.AddrBits, Parameters.DataBits) + + val cpu_debug_read_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth)) + val cpu_debug_read_data = Output(UInt(Parameters.DataWidth)) + }) + + // Memory is controlled in C++ code + val mem_slave = Module(new AXI4LiteSlave(Parameters.AddrBits, Parameters.DataBits)) + io.mem_slave <> mem_slave.io.bundle + + // UART is controlled in C++ code + val uart_slave = Module(new AXI4LiteSlave(Parameters.AddrBits, Parameters.DataBits)) + io.uart_slave <> uart_slave.io.bundle + + val cpu = Module(new CPU) + val dummy = Module(new DummySlave) + val bus_arbiter = Module(new BusArbiter) + val bus_switch = Module(new BusSwitch) + + bus_arbiter.io.bus_request(0) := true.B + + bus_switch.io.master <> cpu.io.axi4_channels + bus_switch.io.address := cpu.io.bus_address + for (i <- 0 until Parameters.SlaveDeviceCount) { + bus_switch.io.slaves(i) <> dummy.io.channels + } + + cpu.io.stall_flag_bus := false.B + cpu.io.instruction_valid := true.B + bus_switch.io.slaves(0) <> mem_slave.io.channels + bus_switch.io.slaves(2) <> uart_slave.io.channels + + cpu.io.interrupt_flag := io.signal_interrupt + + cpu.io.debug_read_address := io.cpu_debug_read_address + io.cpu_debug_read_data := cpu.io.debug_read_data +} + +object VerilogGenerator extends App { + (new ChiselStage).execute(Array("-X", "verilog", "-td", "verilog/verilator"), Seq(ChiselGeneratorAnnotation(() => + new Top))) +} \ No newline at end of file diff --git a/mini-yatcpu/src/main/scala/board/z710/z710/Top.scala b/mini-yatcpu/src/main/scala/board/z710/z710/Top.scala new file mode 100644 index 0000000..fc7a85d --- /dev/null +++ b/mini-yatcpu/src/main/scala/board/z710/z710/Top.scala @@ -0,0 +1,119 @@ +package board.z710 + + +import chisel3._ +import chisel3.stage.ChiselStage +import chisel3.util._ +import chisel3.{ChiselEnum, _} + +// import circt.stage.ChiselStage +import chisel3.stage.ChiselGeneratorAnnotation + +import bus._ +import peripheral._ +import riscv._ +import riscv.Parameters +import riscv.core.CPU +import javax.print.SimpleDoc + +object BootStates extends ChiselEnum { + val Init, Loading, BusWait, Finished = Value +} + + +class Top(binaryFilename: String ="say_goodbye.asmbin") extends Module { + // val binaryFilename = "say_goodbye.asmbin" + val io = IO(new Bundle { + // val switch = Input(UInt(16.W)) + + // val rgb = Output(UInt(12.W)) + + val led = Output(Bool()) + val tx = Output(Bool()) + val rx = Input(Bool()) + + + }) + val boot_state = RegInit(BootStates.Init) + + val uart = Module(new Uart(125_000_000, 115200)) // this freq is consistent with Zynq 7 PS UART module + io.tx := uart.io.txd + uart.io.rxd := io.rx + + val cpu = Module(new CPU) + val mem = Module(new Memory(Parameters.MemorySizeInWords)) + val timer = Module(new Timer) + val dummy = Module(new DummySlave) + val bus_arbiter = Module(new BusArbiter) + val bus_switch = Module(new BusSwitch) + + val instruction_rom = Module(new InstructionROM(binaryFilename)) + val rom_loader = Module(new ROMLoader(instruction_rom.capacity)) + + bus_arbiter.io.bus_request(0) := true.B + + bus_switch.io.master <> cpu.io.axi4_channels + bus_switch.io.address := cpu.io.bus_address + for (i <- 0 until Parameters.SlaveDeviceCount) { + bus_switch.io.slaves(i) <> dummy.io.channels + } + rom_loader.io.load_address := Parameters.EntryAddress + rom_loader.io.load_start := false.B + rom_loader.io.rom_data := instruction_rom.io.data + instruction_rom.io.address := rom_loader.io.rom_address + cpu.io.stall_flag_bus := true.B + cpu.io.instruction_valid := false.B + bus_switch.io.slaves(0) <> mem.io.channels + rom_loader.io.channels <> dummy.io.channels + switch(boot_state) { + is(BootStates.Init) { + rom_loader.io.load_start := true.B + boot_state := BootStates.Loading + rom_loader.io.channels <> mem.io.channels + } + is(BootStates.Loading) { + rom_loader.io.load_start := false.B + rom_loader.io.channels <> mem.io.channels + when(rom_loader.io.load_finished) { + boot_state := BootStates.Finished + } + } + is(BootStates.Finished) { + cpu.io.stall_flag_bus := false.B + cpu.io.instruction_valid := true.B + } + } + + bus_switch.io.slaves(2) <> uart.io.channels + bus_switch.io.slaves(4) <> timer.io.channels + + cpu.io.interrupt_flag := Cat(uart.io.signal_interrupt, timer.io.signal_interrupt) + + cpu.io.debug_read_address := 0.U + mem.io.debug_read_address := 0.U + + + + val clock_freq = 100_000_000.U + + val led_count = RegInit(0.U(32.W)) + when (led_count >= clock_freq) { // the led blinks every second, clock freq is 100M + led_count := 0.U + }.otherwise { + led_count := led_count + 1.U + } + + io.led := (led_count >= (clock_freq >> 1)) + + +} + + + +object VerilogGenerator extends App { + (new ChiselStage).execute( + Array("-X", "verilog", "--target-dir", "verilog/z710"), + Seq(ChiselGeneratorAnnotation(() => new Top())) // default bin file + ) + +} \ No newline at end of file diff --git a/mini-yatcpu/src/main/scala/bus/AXI4Lite.scala b/mini-yatcpu/src/main/scala/bus/AXI4Lite.scala new file mode 100644 index 0000000..fa8ede4 --- /dev/null +++ b/mini-yatcpu/src/main/scala/bus/AXI4Lite.scala @@ -0,0 +1,312 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package bus + +import chisel3._ +import chisel3.util._ +import riscv.Parameters + +object AXI4Lite { + val protWidth = 3 + val respWidth = 2 +} + +class AXI4LiteWriteAddressChannel(addrWidth: Int) extends Bundle { + + val AWVALID = Output(Bool()) + val AWREADY = Input(Bool()) + val AWADDR = Output(UInt(addrWidth.W)) + val AWPROT = Output(UInt(AXI4Lite.protWidth.W)) + +} + +class AXI4LiteWriteDataChannel(dataWidth: Int) extends Bundle { + val WVALID = Output(Bool()) + val WREADY = Input(Bool()) + val WDATA = Output(UInt(dataWidth.W)) + val WSTRB = Output(UInt((dataWidth / 8).W)) +} + +class AXI4LiteWriteResponseChannel extends Bundle { + val BVALID = Input(Bool()) + val BREADY = Output(Bool()) + val BRESP = Input(UInt(AXI4Lite.respWidth.W)) +} + +class AXI4LiteReadAddressChannel(addrWidth: Int) extends Bundle { + val ARVALID = Output(Bool()) + val ARREADY = Input(Bool()) + val ARADDR = Output(UInt(addrWidth.W)) + val ARPROT = Output(UInt(AXI4Lite.protWidth.W)) +} + +class AXI4LiteReadDataChannel(dataWidth: Int) extends Bundle { + val RVALID = Input(Bool()) + val RREADY = Output(Bool()) + val RDATA = Input(UInt(dataWidth.W)) + val RRESP = Input(UInt(AXI4Lite.respWidth.W)) +} + +class AXI4LiteInterface(addrWidth: Int, dataWidth: Int) extends Bundle { + val AWVALID = Output(Bool()) + val AWREADY = Input(Bool()) + val AWADDR = Output(UInt(addrWidth.W)) + val AWPROT = Output(UInt(AXI4Lite.protWidth.W)) + val WVALID = Output(Bool()) + val WREADY = Input(Bool()) + val WDATA = Output(UInt(dataWidth.W)) + val WSTRB = Output(UInt((dataWidth / 8).W)) + val BVALID = Input(Bool()) + val BREADY = Output(Bool()) + val BRESP = Input(UInt(AXI4Lite.respWidth.W)) + val ARVALID = Output(Bool()) + val ARREADY = Input(Bool()) + val ARADDR = Output(UInt(addrWidth.W)) + val ARPROT = Output(UInt(AXI4Lite.protWidth.W)) + val RVALID = Input(Bool()) + val RREADY = Output(Bool()) + val RDATA = Input(UInt(dataWidth.W)) + val RRESP = Input(UInt(AXI4Lite.respWidth.W)) +} + +class AXI4LiteChannels(addrWidth: Int, dataWidth: Int) extends Bundle { + val write_address_channel = new AXI4LiteWriteAddressChannel(addrWidth) + val write_data_channel = new AXI4LiteWriteDataChannel(dataWidth) + val write_response_channel = new AXI4LiteWriteResponseChannel() + val read_address_channel = new AXI4LiteReadAddressChannel(addrWidth) + val read_data_channel = new AXI4LiteReadDataChannel(dataWidth) +} + +class AXI4LiteSlaveBundle(addrWidth: Int, dataWidth: Int) extends Bundle { + val read = Output(Bool()) + val write = Output(Bool()) + val read_data = Input(UInt(dataWidth.W)) + val read_valid = Input(Bool()) + val write_data = Output(UInt(dataWidth.W)) + val write_strobe = Output(Vec(Parameters.WordSize, Bool())) + val address = Output(UInt(addrWidth.W)) +} + +class AXI4LiteMasterBundle(addrWidth: Int, dataWidth: Int) extends Bundle { + val read = Input(Bool()) + val write = Input(Bool()) + val read_data = Output(UInt(dataWidth.W)) + val write_data = Input(UInt(dataWidth.W)) + val write_strobe = Input(Vec(Parameters.WordSize, Bool())) + val address = Input(UInt(addrWidth.W)) + + val busy = Output(Bool()) + val read_valid = Output(Bool()) + val write_valid = Output(Bool()) +} + +object AXI4LiteStates extends ChiselEnum { + val Idle, ReadAddr, ReadData, WriteAddr, WriteData, WriteResp = Value +} + +// TODO(howard): implement full duplex +class AXI4LiteSlave(addrWidth: Int, dataWidth: Int) extends Module { + val io = IO(new Bundle { + val channels = Flipped(new AXI4LiteChannels(addrWidth, dataWidth)) + val bundle = new AXI4LiteSlaveBundle(addrWidth, dataWidth) + }) + val state = RegInit(AXI4LiteStates.Idle) + val addr = RegInit(0.U(dataWidth.W)) + io.bundle.address := addr + val read = RegInit(false.B) + io.bundle.read := read + val write = RegInit(false.B) + io.bundle.write := write + val write_data = RegInit(0.U(dataWidth.W)) + io.bundle.write_data := write_data + val write_strobe = RegInit(VecInit(Seq.fill(Parameters.WordSize)(false.B))) + io.bundle.write_strobe := write_strobe + + val ARREADY = RegInit(false.B) + io.channels.read_address_channel.ARREADY := ARREADY + val RVALID = RegInit(false.B) + io.channels.read_data_channel.RVALID := RVALID + val RRESP = RegInit(0.U(AXI4Lite.respWidth.W)) + io.channels.read_data_channel.RRESP := RRESP + + io.channels.read_data_channel.RDATA := io.bundle.read_data + + val AWREADY = RegInit(false.B) + io.channels.write_address_channel.AWREADY := AWREADY + val WREADY = RegInit(false.B) + io.channels.write_data_channel.WREADY := WREADY + write_data := io.channels.write_data_channel.WDATA + val BVALID = RegInit(false.B) + io.channels.write_response_channel.BVALID := BVALID + val BRESP = WireInit(0.U(AXI4Lite.respWidth.W)) + io.channels.write_response_channel.BRESP := BRESP + + switch(state) { + is(AXI4LiteStates.Idle) { + read := false.B + write := false.B + RVALID := false.B + BVALID := false.B + when(io.channels.write_address_channel.AWVALID) { + state := AXI4LiteStates.WriteAddr + }.elsewhen(io.channels.read_address_channel.ARVALID) { + state := AXI4LiteStates.ReadAddr + } + } + is(AXI4LiteStates.ReadAddr) { + ARREADY := true.B + when(io.channels.read_address_channel.ARVALID && ARREADY) { + state := AXI4LiteStates.ReadData + addr := io.channels.read_address_channel.ARADDR + read := true.B + ARREADY := false.B + } + } + is(AXI4LiteStates.ReadData) { + RVALID := io.bundle.read_valid + when(io.channels.read_data_channel.RREADY && RVALID) { + state := AXI4LiteStates.Idle + RVALID := false.B + } + } + is(AXI4LiteStates.WriteAddr) { + AWREADY := true.B + when(io.channels.write_address_channel.AWVALID && AWREADY) { + addr := io.channels.write_address_channel.AWADDR + state := AXI4LiteStates.WriteData + AWREADY := false.B + } + } + is(AXI4LiteStates.WriteData) { + WREADY := true.B + when(io.channels.write_data_channel.WVALID && WREADY) { + state := AXI4LiteStates.WriteResp + write_data := io.channels.write_data_channel.WDATA + write_strobe := io.channels.write_data_channel.WSTRB.asBools + write := true.B + WREADY := false.B + } + } + is(AXI4LiteStates.WriteResp) { + WREADY := false.B + BVALID := true.B + when(io.channels.write_response_channel.BREADY && BVALID) { + state := AXI4LiteStates.Idle + write := false.B + BVALID := false.B + } + } + } +} + +class AXI4LiteMaster(addrWidth: Int, dataWidth: Int) extends Module { + val io = IO(new Bundle { + val channels = new AXI4LiteChannels(addrWidth, dataWidth) + val bundle = new AXI4LiteMasterBundle(addrWidth, dataWidth) + }) + val state = RegInit(AXI4LiteStates.Idle) + io.bundle.busy := state =/= AXI4LiteStates.Idle + + val addr = RegInit(0.U(dataWidth.W)) + val read_valid = RegInit(false.B) + io.bundle.read_valid := read_valid + val write_valid = RegInit(false.B) + io.bundle.write_valid := write_valid + val write_data = RegInit(0.U(dataWidth.W)) + val write_strobe = RegInit(VecInit(Seq.fill(Parameters.WordSize)(false.B))) + val read_data = RegInit(0.U(dataWidth.W)) + + io.channels.read_address_channel.ARADDR := 0.U + val ARVALID = RegInit(false.B) + io.channels.read_address_channel.ARVALID := ARVALID + io.channels.read_address_channel.ARPROT := 0.U + val RREADY = RegInit(false.B) + io.channels.read_data_channel.RREADY := RREADY + + io.bundle.read_data := io.channels.read_data_channel.RDATA + val AWVALID = RegInit(false.B) + io.channels.write_address_channel.AWADDR := 0.U + io.channels.write_address_channel.AWVALID := AWVALID + val WVALID = RegInit(false.B) + io.channels.write_data_channel.WVALID := WVALID + io.channels.write_data_channel.WDATA := write_data + io.channels.write_address_channel.AWPROT := 0.U + io.channels.write_data_channel.WSTRB := write_strobe.asUInt + val BREADY = RegInit(false.B) + io.channels.write_response_channel.BREADY := BREADY + + switch(state) { + is(AXI4LiteStates.Idle) { + WVALID := false.B + AWVALID := false.B + ARVALID := false.B + RREADY := false.B + read_valid := false.B + write_valid := false.B + when(io.bundle.write) { + state := AXI4LiteStates.WriteAddr + addr := io.bundle.address + write_data := io.bundle.write_data + write_strobe := io.bundle.write_strobe + }.elsewhen(io.bundle.read) { + state := AXI4LiteStates.ReadAddr + addr := io.bundle.address + } + } + is(AXI4LiteStates.ReadAddr) { + ARVALID := true.B + io.channels.read_address_channel.ARADDR := addr + when(io.channels.read_address_channel.ARREADY && ARVALID) { + state := AXI4LiteStates.ReadData + io.channels.read_address_channel.ARADDR := addr + ARVALID := false.B + } + } + is(AXI4LiteStates.ReadData) { + when(io.channels.read_data_channel.RVALID && io.channels.read_data_channel.RRESP === 0.U) { + state := AXI4LiteStates.Idle + read_valid := true.B + RREADY := true.B + read_data := io.channels.read_data_channel.RDATA + } + } + is(AXI4LiteStates.WriteAddr) { + AWVALID := true.B + io.channels.write_address_channel.AWADDR := addr + when(io.channels.write_address_channel.AWREADY && AWVALID) { + state := AXI4LiteStates.WriteData + io.channels.write_address_channel.AWADDR := addr + AWVALID := false.B + } + } + is(AXI4LiteStates.WriteData) { + WVALID := true.B + io.channels.write_address_channel.AWADDR := addr + when(io.channels.write_data_channel.WREADY && WVALID) { + io.channels.write_address_channel.AWADDR := addr + state := AXI4LiteStates.WriteResp + WVALID := false.B + } + } + is(AXI4LiteStates.WriteResp) { + BREADY := true.B + when(io.channels.write_response_channel.BVALID && BREADY) { + state := AXI4LiteStates.Idle + write_valid := true.B + BREADY := false.B + } + } + } +} diff --git a/mini-yatcpu/src/main/scala/bus/BusArbiter.scala b/mini-yatcpu/src/main/scala/bus/BusArbiter.scala new file mode 100644 index 0000000..57f39f8 --- /dev/null +++ b/mini-yatcpu/src/main/scala/bus/BusArbiter.scala @@ -0,0 +1,40 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package bus + +import chisel3._ +import riscv.Parameters + +class BusArbiter extends Module { + val io = IO(new Bundle { + val bus_request = Input(Vec(Parameters.MasterDeviceCount, Bool())) + val bus_granted = Output(Vec(Parameters.MasterDeviceCount, Bool())) + + val ctrl_stall_flag = Output(Bool()) + }) + val granted = Wire(UInt()) + // Static Priority Arbitration + // Higher number = Higher priority + granted := 0.U + for (i <- 0 until Parameters.MasterDeviceCount) { + when(io.bus_request(i.U)) { + granted := i.U + } + } + for (i <- 0 until Parameters.MasterDeviceCount) { + io.bus_granted(i.U) := i.U === granted + } + io.ctrl_stall_flag := !io.bus_granted(0.U) +} diff --git a/mini-yatcpu/src/main/scala/bus/BusSwitch.scala b/mini-yatcpu/src/main/scala/bus/BusSwitch.scala new file mode 100644 index 0000000..9f9e2de --- /dev/null +++ b/mini-yatcpu/src/main/scala/bus/BusSwitch.scala @@ -0,0 +1,33 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package bus + +import chisel3._ +import peripheral.DummyMaster +import riscv.Parameters + +class BusSwitch extends Module { + val io = IO(new Bundle { + val address = Input(UInt(Parameters.AddrWidth)) + val slaves = Vec(Parameters.SlaveDeviceCount, new AXI4LiteChannels(Parameters.AddrBits, Parameters.DataBits)) + val master = Flipped(new AXI4LiteChannels(Parameters.AddrBits, Parameters.DataBits)) + }) + val dummy = Module(new DummyMaster) + val index = io.address(Parameters.AddrBits - 1, Parameters.AddrBits - Parameters.SlaveDeviceCountBits) + for (i <- 0 until Parameters.SlaveDeviceCount) { + io.slaves(i) <> dummy.io.channels + } + io.master <> io.slaves(index) +} diff --git a/mini-yatcpu/src/main/scala/peripheral/CharacterDisplay.scala b/mini-yatcpu/src/main/scala/peripheral/CharacterDisplay.scala new file mode 100644 index 0000000..271bf18 --- /dev/null +++ b/mini-yatcpu/src/main/scala/peripheral/CharacterDisplay.scala @@ -0,0 +1,86 @@ +// Copyright 2022 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package peripheral + +import bus.{AXI4LiteChannels, AXI4LiteSlave} +import chisel3.util.{MuxLookup, log2Up} +import chisel3.{Bool, Bundle, Flipped, Module, Mux, Output, UInt, Wire, _} +import peripheral.ScreenInfo.{DisplayHorizontal, DisplayVertical} +import riscv.Parameters + +object GlyphInfo { + val glyphWidth = 8 + val glyphHeight = 16 + // ASCII printable characters start from here + val spaceIndex = 1 +} + +object ScreenInfo { + val DisplayHorizontal = 640 + val DisplayVertical = 480 +} + +object CharacterBufferInfo { + val CharCols = DisplayHorizontal / GlyphInfo.glyphWidth + val CharRows = DisplayVertical / GlyphInfo.glyphHeight + val Chars = CharCols * CharRows +} + +class CharacterDisplay extends Module { + val io = IO(new Bundle() { + val channels = Flipped(new AXI4LiteChannels(log2Up(CharacterBufferInfo.Chars), Parameters.DataBits)) + + val x = Input(UInt(16.W)) + val y = Input(UInt(16.W)) + val video_on = Input(Bool()) + + val rgb = Output(UInt(24.W)) + }) + val slave = Module(new AXI4LiteSlave(log2Up(CharacterBufferInfo.Chars), Parameters.DataBits)) + slave.io.channels <> io.channels + val mem = Module(new BlockRAM(CharacterBufferInfo.Chars / Parameters.WordSize)) + slave.io.bundle.read_valid := true.B + mem.io.write_enable := slave.io.bundle.write + mem.io.write_data := slave.io.bundle.write_data + mem.io.write_address := slave.io.bundle.address + mem.io.write_strobe := slave.io.bundle.write_strobe + + mem.io.read_address := slave.io.bundle.address + slave.io.bundle.read_data := mem.io.read_data + + + val font_rom = Module(new FontROM) + val row = (io.y >> log2Up(GlyphInfo.glyphHeight)).asUInt + val col = (io.x >> log2Up(GlyphInfo.glyphWidth)).asUInt + val char_index = (row * CharacterBufferInfo.CharCols.U) + col + val offset = char_index(1, 0) + val ch = Wire(UInt(8.W)) + + mem.io.debug_read_address := char_index + ch := MuxLookup(offset, 0.U)( + IndexedSeq( + 0.U -> mem.io.debug_read_data(7, 0).asUInt, + 1.U -> mem.io.debug_read_data(15, 8).asUInt, + 2.U -> mem.io.debug_read_data(23, 16).asUInt, + 3.U -> mem.io.debug_read_data(31, 24).asUInt + ) + ) + font_rom.io.glyph_index := Mux(ch >= 32.U, ch - 31.U, 0.U) + font_rom.io.glyph_y := io.y(log2Up(GlyphInfo.glyphHeight) - 1, 0) + + // White if pixel_on and glyph pixel on + val glyph_x = io.x(log2Up(GlyphInfo.glyphWidth) - 1, 0) + io.rgb := Mux(io.video_on && font_rom.io.glyph_pixel_byte(glyph_x), 0xFFFFFF.U, 0.U) +} diff --git a/mini-yatcpu/src/main/scala/peripheral/DummyMaster.scala b/mini-yatcpu/src/main/scala/peripheral/DummyMaster.scala new file mode 100644 index 0000000..ced75f5 --- /dev/null +++ b/mini-yatcpu/src/main/scala/peripheral/DummyMaster.scala @@ -0,0 +1,33 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package peripheral + +import bus.{AXI4LiteChannels, AXI4LiteMaster} +import chisel3._ +import riscv.Parameters + +// A dummy master that never initiates reads or writes +class DummyMaster extends Module { + val io = IO(new Bundle { + val channels = new AXI4LiteChannels(Parameters.AddrBits, Parameters.DataBits) + }) + val master = Module(new AXI4LiteMaster(Parameters.AddrBits, Parameters.DataBits)) + master.io.channels <> io.channels + master.io.bundle.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B)) + master.io.bundle.write_data := 0.U + master.io.bundle.write := false.B + master.io.bundle.read := false.B + master.io.bundle.address := 0.U +} diff --git a/mini-yatcpu/src/main/scala/peripheral/DummySlave.scala b/mini-yatcpu/src/main/scala/peripheral/DummySlave.scala new file mode 100644 index 0000000..cdd98d3 --- /dev/null +++ b/mini-yatcpu/src/main/scala/peripheral/DummySlave.scala @@ -0,0 +1,32 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package peripheral + +import bus.{AXI4LiteChannels, AXI4LiteSlave} +import chisel3._ +import riscv.Parameters + +// A dummy AXI4 slave that only returns 0 on read +// and ignores all writes +class DummySlave extends Module { + val io = IO(new Bundle { + val channels = Flipped(new AXI4LiteChannels(4, Parameters.DataBits)) + }) + + val slave = Module(new AXI4LiteSlave(Parameters.AddrBits, Parameters.DataBits)) + slave.io.channels <> io.channels + slave.io.bundle.read_valid := true.B + slave.io.bundle.read_data := 0xDEADBEEFL.U +} diff --git a/mini-yatcpu/src/main/scala/peripheral/FontROM.scala b/mini-yatcpu/src/main/scala/peripheral/FontROM.scala new file mode 100644 index 0000000..b9b0d3b --- /dev/null +++ b/mini-yatcpu/src/main/scala/peripheral/FontROM.scala @@ -0,0 +1,64 @@ +package peripheral + +import chisel3.experimental.{ChiselAnnotation, annotate} +import chisel3.util.experimental.loadMemoryFromFileInline +import chisel3.{Bundle, Input, Module, Output, SyncReadMem, UInt, _} +import firrtl.annotations.MemorySynthInit + +import java.io.FileWriter +import java.nio.file.Paths +import javax.imageio.ImageIO + +class FontROM(fontBitmapFilename: String = "vga_font_8x16.bmp") extends Module { + val glyphWidth = GlyphInfo.glyphWidth + val glyphHeight = GlyphInfo.glyphHeight + + val io = IO(new Bundle { + val glyph_index = Input(UInt(7.W)) + val glyph_y = Input(UInt(4.W)) + + val glyph_pixel_byte = Output(UInt(8.W)) + }) + + annotate(new ChiselAnnotation { + override def toFirrtl = + MemorySynthInit + }) + + val (hexTxtPath, glyphCount) = readFontBitmap() + val mem = SyncReadMem(glyphCount, UInt(8.W)) + loadMemoryFromFileInline(mem, hexTxtPath.toString.replaceAll("\\\\", "/")) + io.glyph_pixel_byte := mem.read(io.glyph_index * GlyphInfo.glyphHeight.U + io.glyph_y, true.B) + + def readFontBitmap() = { + val inputStream = getClass.getClassLoader.getResourceAsStream(fontBitmapFilename) + val image = ImageIO.read(inputStream) + + val glyphColumns = image.getWidth() / glyphWidth + val glyphRows = image.getHeight / glyphHeight + val glyphCount = glyphColumns * glyphRows + val glyphs = new Array[UInt](glyphCount * GlyphInfo.glyphHeight) + + for (row <- 0 until glyphRows) { + for (col <- 0 until glyphColumns) { + for (i <- 0 until glyphHeight) { + var lineInt = 0 + for (j <- 0 until glyphWidth) { + if (image.getRGB(col * glyphWidth + j, row * glyphHeight + i) != 0xFFFFFFFF) { + lineInt |= (1 << j) + } + } + glyphs((row * glyphColumns + col) * GlyphInfo.glyphHeight + i) = lineInt.U(8.W) + } + } + } + val currentDir = System.getProperty("user.dir") + val hexTxtPath = Paths.get(currentDir, "verilog", f"${fontBitmapFilename}.txt") + val writer = new FileWriter(hexTxtPath.toString) + for (i <- glyphs.indices) { + writer.write(f"@$i%x\n${glyphs(i).litValue}%02x\n") + } + writer.close() + (hexTxtPath, glyphs.length) + } +} diff --git a/mini-yatcpu/src/main/scala/peripheral/HDMIDisplay.scala b/mini-yatcpu/src/main/scala/peripheral/HDMIDisplay.scala new file mode 100644 index 0000000..beeb67a --- /dev/null +++ b/mini-yatcpu/src/main/scala/peripheral/HDMIDisplay.scala @@ -0,0 +1,389 @@ +// Copyright 2022 hrpccs +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package peripheral + +import chisel3._ +import chisel3.util._ + +class HDMISync extends Module { + val io = IO(new Bundle { + val hsync = Output(Bool()) + val vsync = Output(Bool()) + val video_on = Output(Bool()) + val p_tick = Output(Bool()) + val f_tick = Output(Bool()) + val x = Output(UInt(10.W)) + val y = Output(UInt(10.W)) + val x_next = Output(UInt(10.W)) + val y_next = Output(UInt(10.W)) + }) + + val DisplayHorizontal = ScreenInfo.DisplayHorizontal + val DisplayVertical = ScreenInfo.DisplayVertical + + val BorderLeft = 48 + val BorderRight = 16 + val BorderTop = 10 + val BorderBottom = 33 + + val RetraceHorizontal = 96 + val RetraceVertical = 2 + + val MaxHorizontal = DisplayHorizontal + BorderLeft + BorderRight + RetraceHorizontal - 1 + val MaxVertical = DisplayVertical + BorderTop + BorderBottom + RetraceVertical - 1 + + val RetraceHorizontalStart = DisplayHorizontal + BorderRight + val RetraceHorizontalEnd = RetraceHorizontalStart + RetraceHorizontal - 1 + + val RetraceVerticalStart = DisplayVertical + BorderBottom + val RetraceVerticalEnd = RetraceVerticalStart + RetraceVertical - 1 + + val pixel = RegInit(UInt(3.W), 0.U) + val pixel_next = Wire(UInt(3.W)) + val pixel_tick = Wire(Bool()) + + val v_count_reg = RegInit(UInt(10.W), 0.U) + val h_count_reg = RegInit(UInt(10.W), 0.U) + + val v_count_next = Wire(UInt(10.W)) + val h_count_next = Wire(UInt(10.W)) + + val vsync_reg = RegInit(Bool(), false.B) + val hsync_reg = RegInit(Bool(), false.B) + + val vsync_next = Wire(Bool()) + val hsync_next = Wire(Bool()) + + pixel_next := Mux(pixel === 4.U, 0.U, pixel + 1.U) + pixel_tick := pixel === 0.U + + h_count_next := Mux( + pixel_tick, + Mux(h_count_reg === MaxHorizontal.U, 0.U, h_count_reg + 1.U), + h_count_reg + ) + + v_count_next := Mux( + pixel_tick && h_count_reg === MaxHorizontal.U, + Mux(v_count_reg === MaxVertical.U, 0.U, v_count_reg + 1.U), + v_count_reg + ) + + hsync_next := h_count_reg >= RetraceHorizontalStart.U && h_count_reg <= RetraceHorizontalEnd.U + vsync_next := v_count_reg >= RetraceVerticalStart.U && v_count_reg <= RetraceVerticalEnd.U + + pixel := pixel_next + hsync_reg := hsync_next + vsync_reg := vsync_next + v_count_reg := v_count_next + h_count_reg := h_count_next + + io.video_on := h_count_reg < DisplayHorizontal.U && v_count_reg < DisplayVertical.U + io.hsync := hsync_reg + io.vsync := vsync_reg + io.x := h_count_reg + io.y := v_count_reg + io.x_next := h_count_next + io.y_next := v_count_next + io.p_tick := pixel_tick + io.f_tick := io.x === 0.U && io.y === 0.U +} + +class TMDS_encoder extends Module { + val io = IO(new Bundle() { + val video_data = Input(UInt(8.W)) //r,g,b,8bit + val control_data = Input(UInt(2.W)) + val video_on = Input(Bool()) + val TMDS = Output(UInt(10.W)) + }) + val Nb1s = PopCount(io.video_data) + val xored = xorfct(io.video_data) + val xnored = xnorfct(io.video_data) + val XNOR = (Nb1s > 4.U(4.W)) || (Nb1s === 4.U(4.W) && io.video_data(0) === 0.U) + val q_m = RegInit(0.U(9.W)) + val diffSize = 4 + val diff = RegInit(0.S(diffSize.W)) + q_m := Mux( + XNOR, + xnored, + xored + ) + val disparitySize = 4 + val disparityReg = RegInit(0.S(disparitySize.W)) + diff := PopCount(q_m).asSInt - 4.S + val doutReg = RegInit("b1010101011".U(10.W)) + + def xorfct(value: UInt): UInt = { + val vin = VecInit(value.asBools) + val res = VecInit(511.U.asBools) + res(0) := vin(0) + for (i <- 1 to 7) { + res(i) := res(i - 1) ^ vin(i) + } + res(8) := 1.U + res.asUInt + } + + def xnorfct(value: UInt): UInt = { + val vin = VecInit(value.asBools) + val res = VecInit(511.U.asBools) + res(0) := vin(0) + for (i <- 1 to 7) { + res(i) := !(res(i - 1) ^ vin(i)) + } + res(8) := 0.U + res.asUInt + } + + when(io.video_on === false.B) { + disparityReg := 0.S + doutReg := "b1010101011".U(10.W) + switch(io.control_data) { + is("b00".U(2.W)) { + doutReg := "b1101010100".U(10.W) + } + is("b01".U(2.W)) { + doutReg := "b0010101011".U(10.W) + } + is("b10".U(2.W)) { + doutReg := "b0101010100".U(10.W) + } + } + }.otherwise { + when(disparityReg === 0.S || diff === 0.S) { + when(q_m(8) === false.B) { + doutReg := "b10".U(2.W) ## ~q_m(7, 0) + disparityReg := disparityReg - diff + }.otherwise { + doutReg := "b01".U(2.W) ## q_m(7, 0) + disparityReg := disparityReg + diff + } + }.elsewhen((!diff(diffSize - 1) && !disparityReg(disparitySize - 1)) + || (diff(diffSize - 1) && disparityReg(disparitySize - 1))) { + doutReg := 1.U(1.W) ## q_m(8) ## ~q_m(7, 0) + when(q_m(8)) { + disparityReg := disparityReg + 1.S - diff + }.otherwise { + disparityReg := disparityReg - diff + } + }.otherwise { + doutReg := 0.U(1.W) ## q_m + when(q_m(8)) { + disparityReg := disparityReg + diff + }.otherwise { + disparityReg := disparityReg - 1.S + diff + } + } + } + + io.TMDS := doutReg +} + +class HDMIDisplay extends Module { + val io = IO(new Bundle() { + val rgb = Input(UInt(24.W)) + val x = Output(UInt(16.W)) + val y = Output(UInt(16.W)) + val x_next = Output(UInt(16.W)) + val y_next = Output(UInt(16.W)) + val video_on = Output(Bool()) + + val TMDSclk_p = Output(Bool()) + val TMDSdata_p = Output(UInt(3.W)) + val TMDSclk_n = Output(Bool()) + val TMDSdata_n = Output(UInt(3.W)) + }) + val rgb = io.rgb + val pixel_clk = Wire(Bool()) + val hsync = Wire(Bool()) + val vsync = Wire(Bool()) + val sync = Module(new HDMISync) + + io.x := sync.io.x + io.y := sync.io.y + io.x_next := sync.io.x_next + io.y_next := sync.io.y_next + io.video_on := sync.io.video_on + + hsync := sync.io.hsync + vsync := sync.io.vsync + pixel_clk := sync.io.p_tick + + // TMDS_PLLVR is a vivado IP core, check it in /verilog/pynq/TMDS_PLLVR.v + val serial_clk = Wire(Clock()) + val pll_lock = Wire(Bool()) + val tmdspll = Module(new TMDS_PLLVR) + val rst = Wire(Reset()) + tmdspll.io.clkin := pixel_clk.asClock + serial_clk := tmdspll.io.clkout + pll_lock := tmdspll.io.lock + tmdspll.io.reset := reset + rst := ~pll_lock + + val tmds = Wire(UInt(3.W)) + val tmds_clk = Wire(Bool()) + withClockAndReset(pixel_clk.asClock, rst) { + val tmds_channel1 = Wire(UInt(10.W)) + val tmds_channel2 = Wire(UInt(10.W)) + val tmds_channel0 = Wire(UInt(10.W)) + + val tmds_green = Module(new TMDS_encoder) + val tmds_red = Module(new TMDS_encoder) + val tmds_blue = Module(new TMDS_encoder) + + tmds_red.io.video_on := sync.io.video_on + tmds_blue.io.video_on := sync.io.video_on + tmds_green.io.video_on := sync.io.video_on + + tmds_blue.io.control_data := sync.io.vsync ## sync.io.hsync + tmds_green.io.control_data := 0.U + tmds_red.io.control_data := 0.U + + tmds_red.io.video_data := rgb(23, 16) + tmds_blue.io.video_data := rgb(7, 0) + tmds_green.io.video_data := rgb(15, 8) + + tmds_channel0 := tmds_blue.io.TMDS + tmds_channel1 := tmds_green.io.TMDS + tmds_channel2 := tmds_red.io.TMDS + + val serdesBlue = Module(new Oser10Module()) + serdesBlue.io.data := tmds_channel0 + serdesBlue.io.fclk := serial_clk + + val serdesGreen = Module(new Oser10Module()) + serdesGreen.io.data := tmds_channel1 + serdesGreen.io.fclk := serial_clk + + val serdesRed = Module(new Oser10Module()) + serdesRed.io.data := tmds_channel2 + serdesRed.io.fclk := serial_clk + + tmds := serdesRed.io.q ## serdesGreen.io.q ## serdesBlue.io.q + + //serdesCLk : 25Mhz ,Why not directly use p_tick? + //cause Duty Ratio of p_tick is 10% , while which of serdesCLk is 50% + val serdesClk = Module(new Oser10Module()) + serdesClk.io.data := "b1111100000".U(10.W) + serdesClk.io.fclk := serial_clk + + tmds_clk := serdesClk.io.q + + val buffDiffBlue = Module(new OBUFDS) + buffDiffBlue.io.I := tmds(0) + val buffDiffGreen = Module(new OBUFDS) + buffDiffGreen.io.I := tmds(1) + val buffDiffRed = Module(new OBUFDS) + buffDiffRed.io.I := tmds(2) + val buffDiffClk = Module(new OBUFDS) + buffDiffClk.io.I := tmds_clk + + io.TMDSclk_p := buffDiffClk.io.O + io.TMDSclk_n := buffDiffClk.io.OB + io.TMDSdata_p := buffDiffRed.io.O ## buffDiffGreen.io.O ## buffDiffBlue.io.O + io.TMDSdata_n := buffDiffRed.io.OB ## buffDiffGreen.io.OB ## buffDiffBlue.io.OB + } +} + +//---------------------------------------- +//PLL frequency multiplier using BlackBox +class TMDS_PLLVR extends BlackBox { + val io = IO(new Bundle { + val clkin = Input(Clock()) + val reset = Input(Reset()) + val clkout = Output(Clock()) + val clkoutd = Output(Clock()) + val lock = Output(Bool()) + }) +} + +/* OSER10 : serializer 10:1*/ +class OSER10 extends Module { + val io = IO(new Bundle { + val Q = Output(Bool()) // OSER10 data output signal + val D0 = Input(Bool()) + val D1 = Input(Bool()) + val D2 = Input(Bool()) + val D3 = Input(Bool()) + val D4 = Input(Bool()) + val D5 = Input(Bool()) + val D6 = Input(Bool()) + val D7 = Input(Bool()) + val D8 = Input(Bool()) + val D9 = Input(Bool()) // OSER10 data input signal + val PCLK = Input(Clock()) // Primary clock input signal + val FCLK = Input(Clock()) // High speed clock input signal + val RESET = Input(Reset()) // Asynchronous reset input signal, + //active-high. + }) + withClockAndReset(io.FCLK, io.RESET) { + val count = RegInit(0.U(4.W)) + val countnext = Wire(UInt(4.W)) + io.Q := MuxLookup(count, 0.U)( + IndexedSeq( + 0.U -> io.D0.asBool, + 1.U -> io.D1.asBool, + 2.U -> io.D2.asBool, + 3.U -> io.D3.asBool, + 4.U -> io.D4.asBool, + 5.U -> io.D5.asBool, + 6.U -> io.D6.asBool, + 7.U -> io.D7.asBool, + 8.U -> io.D8.asBool, + 9.U -> io.D9.asBool + ) + ) + countnext := Mux( + count === 9.U, 0.U, count + 1.U + ) + count := countnext + } +} + +class Oser10Module extends Module { + val io = IO(new Bundle { + val q = Output(Bool()) + val data = Input(UInt(10.W)) + val fclk = Input(Clock()) // Fast clock + }) + + val osr10 = Module(new OSER10()) + io.q := osr10.io.Q + osr10.io.D0 := io.data(0) + osr10.io.D1 := io.data(1) + osr10.io.D2 := io.data(2) + osr10.io.D3 := io.data(3) + osr10.io.D4 := io.data(4) + osr10.io.D5 := io.data(5) + osr10.io.D6 := io.data(6) + osr10.io.D7 := io.data(7) + osr10.io.D8 := io.data(8) + osr10.io.D9 := io.data(9) + osr10.io.PCLK := clock + osr10.io.FCLK := io.fclk + osr10.io.RESET := reset +} + +/* lvds output */ +class OBUFDS extends BlackBox { + val io = IO(new Bundle { + val O = Output(Bool()) + val OB = Output(Bool()) + val I = Input(Bool()) + }) +} +//----------------------------------------- + + diff --git a/mini-yatcpu/src/main/scala/peripheral/InstructionROM.scala b/mini-yatcpu/src/main/scala/peripheral/InstructionROM.scala new file mode 100644 index 0000000..f69ba41 --- /dev/null +++ b/mini-yatcpu/src/main/scala/peripheral/InstructionROM.scala @@ -0,0 +1,68 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package peripheral + +import chisel3._ +import chisel3.experimental.{ChiselAnnotation, annotate} +import chisel3.util.experimental.loadMemoryFromFileInline +import firrtl.annotations.MemorySynthInit +import riscv.Parameters + +import java.io.FileWriter +import java.nio.file.{Files, Paths} +import java.nio.{ByteBuffer, ByteOrder} + +class InstructionROM(instructionFilename: String) extends Module { + val io = IO(new Bundle { + val address = Input(UInt(Parameters.AddrWidth)) + val data = Output(UInt(Parameters.InstructionWidth)) + }) + + val (instructionsInitFile, capacity) = readAsmBinary(instructionFilename) + val mem = SyncReadMem(capacity, UInt(Parameters.InstructionWidth)) + annotate(new ChiselAnnotation { + override def toFirrtl = + MemorySynthInit + }) + loadMemoryFromFileInline(mem, instructionsInitFile.toString.replaceAll("\\\\", "/")) + io.data := mem.read(io.address, true.B) + + def readAsmBinary(filename: String) = { + val inputStream = if (Files.exists(Paths.get(filename))) { + Files.newInputStream(Paths.get(filename)) + } else { + getClass.getClassLoader.getResourceAsStream(filename) + } + var instructions = new Array[BigInt](0) + val arr = new Array[Byte](4) + while (inputStream.read(arr) == 4) { + val instBuf = ByteBuffer.wrap(arr) + instBuf.order(ByteOrder.LITTLE_ENDIAN) + val inst = BigInt(instBuf.getInt() & 0xFFFFFFFFL) + instructions = instructions :+ inst + } + instructions = instructions :+ BigInt(0x00000013L) + instructions = instructions :+ BigInt(0x00000013L) + instructions = instructions :+ BigInt(0x00000013L) + val currentDir = System.getProperty("user.dir") + val exeTxtPath = Paths.get(currentDir, "verilog", f"${instructionFilename}.txt") + val writer = new FileWriter(exeTxtPath.toString) + for (i <- instructions.indices) { + writer.write(f"@$i%x\n${instructions(i)}%08x\n") + } + writer.close() + (exeTxtPath, instructions.length) + } +} diff --git a/mini-yatcpu/src/main/scala/peripheral/InterruptController.scala b/mini-yatcpu/src/main/scala/peripheral/InterruptController.scala new file mode 100644 index 0000000..c26972e --- /dev/null +++ b/mini-yatcpu/src/main/scala/peripheral/InterruptController.scala @@ -0,0 +1,26 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package peripheral + +import chisel3._ +import riscv.Parameters + +// TODO(howard): implementation +class InterruptController extends Module { + val io = IO(new Bundle { + val interrupts = Vec(Parameters.SlaveDeviceCount, Bool()) + val cpu_interrupt_flag = Output(UInt(Parameters.InterruptFlagWidth)) + }) +} diff --git a/mini-yatcpu/src/main/scala/peripheral/Memory.scala b/mini-yatcpu/src/main/scala/peripheral/Memory.scala new file mode 100644 index 0000000..0ea2e52 --- /dev/null +++ b/mini-yatcpu/src/main/scala/peripheral/Memory.scala @@ -0,0 +1,72 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package peripheral + +import bus.{AXI4LiteChannels, AXI4LiteSlave} +import chisel3._ +import riscv.Parameters + +// The purpose of this module is to help the synthesis tool recognize +// our memory as a Block RAM template +class BlockRAM(capacity: Int) extends Module { + val io = IO(new Bundle { + val read_address = Input(UInt(Parameters.AddrWidth)) + val write_address = Input(UInt(Parameters.AddrWidth)) + val write_data = Input(UInt(Parameters.DataWidth)) + val write_enable = Input(Bool()) + val write_strobe = Input(Vec(Parameters.WordSize, Bool())) + + val debug_read_address = Input(UInt(Parameters.AddrWidth)) + + val read_data = Output(UInt(Parameters.DataWidth)) + val debug_read_data = Output(UInt(Parameters.DataWidth)) + }) + val mem = SyncReadMem(capacity, Vec(Parameters.WordSize, UInt(Parameters.ByteWidth))) + when(io.write_enable) { + val write_data_vec = Wire(Vec(Parameters.WordSize, UInt(Parameters.ByteWidth))) + for (i <- 0 until Parameters.WordSize) { + write_data_vec(i) := io.write_data((i + 1) * Parameters.ByteBits - 1, i * Parameters.ByteBits) + } + mem.write((io.write_address >> 2.U).asUInt, write_data_vec, io.write_strobe) + } + io.read_data := mem.read((io.read_address >> 2.U).asUInt, true.B).asUInt + io.debug_read_data := mem.read((io.debug_read_address >> 2.U).asUInt, true.B).asUInt +} + +// This module wraps the Block RAM with an AXI4-Lite interface +class Memory(capacity: Int) extends Module { + val io = IO(new Bundle { + val channels = Flipped(new AXI4LiteChannels(Parameters.AddrBits, Parameters.DataBits)) + + val debug_read_address = Input(UInt(Parameters.AddrWidth)) + val debug_read_data = Output(UInt(Parameters.DataWidth)) + }) + + val mem = Module(new BlockRAM(capacity)) + val slave = Module(new AXI4LiteSlave(Parameters.AddrBits, Parameters.DataBits)) + slave.io.channels <> io.channels + slave.io.bundle.read_valid := true.B + + mem.io.write_enable := slave.io.bundle.write + mem.io.write_data := slave.io.bundle.write_data + mem.io.write_address := slave.io.bundle.address + mem.io.write_strobe := slave.io.bundle.write_strobe + + mem.io.read_address := slave.io.bundle.address + slave.io.bundle.read_data := mem.io.read_data + + mem.io.debug_read_address := io.debug_read_address + io.debug_read_data := mem.io.debug_read_data +} diff --git a/mini-yatcpu/src/main/scala/peripheral/PixelDisplay.scala b/mini-yatcpu/src/main/scala/peripheral/PixelDisplay.scala new file mode 100644 index 0000000..531b0f3 --- /dev/null +++ b/mini-yatcpu/src/main/scala/peripheral/PixelDisplay.scala @@ -0,0 +1,55 @@ +// Copyright 2022 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package peripheral + +import bus.{AXI4LiteChannels, AXI4LiteSlave} +import chisel3._ +import riscv.Parameters + +class PixelDisplay extends Module { + val io = IO(new Bundle() { + val channels = Flipped(new AXI4LiteChannels(32, Parameters.DataBits)) + + val x = Input(UInt(16.W)) + val y = Input(UInt(16.W)) + val video_on = Input(Bool()) + + val rgb = Output(UInt(24.W)) + }) + val slave = Module(new AXI4LiteSlave(32, Parameters.DataBits)) + slave.io.channels <> io.channels + + // 320x240, RGB 565 + val mem = Module(new BlockRAM(320 * 240 / 2)) + slave.io.bundle.read_valid := true.B + mem.io.write_enable := slave.io.bundle.write + mem.io.write_data := slave.io.bundle.write_data + mem.io.write_address := slave.io.bundle.address + mem.io.write_strobe := slave.io.bundle.write_strobe + + mem.io.read_address := slave.io.bundle.address + slave.io.bundle.read_data := mem.io.read_data + + + val pixel_x = io.x(15, 1).asUInt + val pixel_y = io.y(15, 1).asUInt + mem.io.debug_read_address := (pixel_y * 320.U + pixel_x) << 1 + + val pixel = Mux(pixel_x(0), mem.io.debug_read_data(31, 16), mem.io.debug_read_data(15, 0)) + val r = pixel(15, 11) ## 0.U(3.W) + val g = pixel(10, 5) ## 0.U(2.W) + val b = pixel(4, 0) ## 0.U(3.W) + io.rgb := Mux(io.video_on, r ## g ## b, 0.U) +} diff --git a/mini-yatcpu/src/main/scala/peripheral/ROMLoader.scala b/mini-yatcpu/src/main/scala/peripheral/ROMLoader.scala new file mode 100644 index 0000000..4a7491b --- /dev/null +++ b/mini-yatcpu/src/main/scala/peripheral/ROMLoader.scala @@ -0,0 +1,79 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package peripheral + +import bus.{AXI4LiteChannels, AXI4LiteMaster} +import chisel3._ +import riscv.Parameters + +class ROMLoader(capacity: Int) extends Module { + val io = IO(new Bundle { + val channels = new AXI4LiteChannels(Parameters.AddrBits, Parameters.InstructionBits) + + val rom_address = Output(UInt(Parameters.AddrWidth)) + val rom_data = Input(UInt(Parameters.InstructionWidth)) + + val load_start = Input(Bool()) + val load_address = Input(UInt(Parameters.AddrWidth)) + val load_finished = Output(Bool()) + }) + val master = Module(new AXI4LiteMaster(Parameters.AddrBits, Parameters.InstructionBits)) + master.io.channels <> io.channels + + val address = RegInit(0.U(32.W)) + val valid = RegInit(false.B) + val loading = RegInit(false.B) + + master.io.bundle.read := false.B + io.load_finished := false.B + + when(io.load_start) { + valid := false.B + loading := true.B + address := 0.U + } + + master.io.bundle.write := false.B + master.io.bundle.write_data := 0.U + master.io.bundle.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B)) + master.io.bundle.address := 0.U + + when(!loading && !master.io.bundle.busy && address >= (capacity - 1).U) { + io.load_finished := true.B + } + when(loading) { + valid := true.B + when(!master.io.bundle.busy && !master.io.bundle.write_valid) { + when(valid) { + master.io.bundle.write := true.B + master.io.bundle.write_data := io.rom_data + master.io.bundle.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(true.B)) + master.io.bundle.address := (address << 2.U).asUInt + io.load_address + } + } + when(master.io.bundle.write_valid) { + when(address >= (capacity - 1).U) { + loading := false.B + }.otherwise { + loading := true.B + address := address + 1.U + valid := false.B + } + }.otherwise { + address := address + } + } + io.rom_address := address +} diff --git a/mini-yatcpu/src/main/scala/peripheral/SPI.scala b/mini-yatcpu/src/main/scala/peripheral/SPI.scala new file mode 100644 index 0000000..e8903ad --- /dev/null +++ b/mini-yatcpu/src/main/scala/peripheral/SPI.scala @@ -0,0 +1,23 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package peripheral + +import chisel3._ + +class SPI extends Module { + val io = IO(new Bundle { + + }) +} diff --git a/mini-yatcpu/src/main/scala/peripheral/Timer.scala b/mini-yatcpu/src/main/scala/peripheral/Timer.scala new file mode 100644 index 0000000..947f856 --- /dev/null +++ b/mini-yatcpu/src/main/scala/peripheral/Timer.scala @@ -0,0 +1,65 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package peripheral + +import bus.{AXI4LiteChannels, AXI4LiteSlave} +import chisel3._ +import chisel3.util._ +import riscv.Parameters + +class Timer extends Module { + val io = IO(new Bundle { + val channels = Flipped(new AXI4LiteChannels(8, Parameters.DataBits)) + val signal_interrupt = Output(Bool()) + + val debug_limit = Output(UInt(Parameters.DataWidth)) + val debug_enabled = Output(Bool()) + }) + val slave = Module(new AXI4LiteSlave(8, Parameters.DataBits)) + slave.io.channels <> io.channels + + val count = RegInit(0.U(32.W)) + val limit = RegInit(100000000.U(32.W)) + io.debug_limit := limit + val enabled = RegInit(true.B) + io.debug_enabled := enabled + + slave.io.bundle.read_data := 0.U + slave.io.bundle.read_valid := true.B + when(slave.io.bundle.read) { + slave.io.bundle.read_data := MuxLookup(slave.io.bundle.address, 0.U)( + IndexedSeq( + 0x4.U -> limit, + 0x8.U -> enabled.asUInt, + ) + ) + } + when(slave.io.bundle.write) { + when(slave.io.bundle.address === 0x4.U) { + limit := slave.io.bundle.write_data + count := 0.U + }.elsewhen(slave.io.bundle.address === 0x8.U) { + enabled := slave.io.bundle.write_data =/= 0.U + } + } + + io.signal_interrupt := enabled && (count >= (limit - 10.U)) + + when(count >= limit) { + count := 0.U + }.otherwise { + count := count + 1.U + } +} diff --git a/mini-yatcpu/src/main/scala/peripheral/UART.scala b/mini-yatcpu/src/main/scala/peripheral/UART.scala new file mode 100644 index 0000000..f21545c --- /dev/null +++ b/mini-yatcpu/src/main/scala/peripheral/UART.scala @@ -0,0 +1,211 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package peripheral + +import bus.{AXI4LiteChannels, AXI4LiteSlave} +import chisel3._ +import chisel3.util._ +import riscv.Parameters + +class UartIO extends DecoupledIO(UInt(8.W)) { +} + + +/** + * Transmit part of the UART. + * A minimal version without any additional buffering. + * Use a ready/valid handshaking. + */ +class Tx(frequency: Int, baudRate: Int) extends Module { + val io = IO(new Bundle { + val txd = Output(UInt(1.W)) + val channel = Flipped(new UartIO()) + + }) + + val BIT_CNT = ((frequency + baudRate / 2) / baudRate - 1).U + + val shiftReg = RegInit(0x7ff.U) + val cntReg = RegInit(0.U(20.W)) + val bitsReg = RegInit(0.U(4.W)) + + io.channel.ready := (cntReg === 0.U) && (bitsReg === 0.U) + io.txd := shiftReg(0) + + when(cntReg === 0.U) { + + cntReg := BIT_CNT + when(bitsReg =/= 0.U) { + val shift = shiftReg >> 1 + shiftReg := Cat(1.U, shift(9, 0)) + bitsReg := bitsReg - 1.U + }.otherwise { + when(io.channel.valid) { + shiftReg := Cat(Cat(3.U, io.channel.bits), 0.U) // two stop bits, data, one start bit + bitsReg := 11.U + }.otherwise { + shiftReg := 0x7ff.U + } + } + + }.otherwise { + cntReg := cntReg - 1.U + } +} + +/** + * Receive part of the UART. + * A minimal version without any additional buffering. + * Use a ready/valid handshaking. + * + * The following code is inspired by Tommy's receive code at: + * https://github.com/tommythorn/yarvi + */ +class Rx(frequency: Int, baudRate: Int) extends Module { + val io = IO(new Bundle { + val rxd = Input(UInt(1.W)) + val channel = new UartIO() + + }) + + val BIT_CNT = ((frequency + baudRate / 2) / baudRate - 1).U + val START_CNT = ((3 * frequency / 2 + baudRate / 2) / baudRate - 1).U + + // Sync in the asynchronous RX data, reset to 1 to not start reading after a reset + val rxReg = RegNext(RegNext(io.rxd, 1.U), 1.U) + + val shiftReg = RegInit(0.U(8.W)) + val cntReg = RegInit(0.U(20.W)) + val bitsReg = RegInit(0.U(4.W)) + val valReg = RegInit(false.B) + + when(cntReg =/= 0.U) { + cntReg := cntReg - 1.U + }.elsewhen(bitsReg =/= 0.U) { + cntReg := BIT_CNT + shiftReg := Cat(rxReg, shiftReg >> 1) + bitsReg := bitsReg - 1.U + // the last shifted in + when(bitsReg === 1.U) { + valReg := true.B + } + }.elsewhen(rxReg === 0.U) { // wait 1.5 bits after falling edge of start + cntReg := START_CNT + bitsReg := 8.U + } + + when(valReg && io.channel.ready) { + valReg := false.B + } + + io.channel.bits := shiftReg + io.channel.valid := valReg +} + +/** + * A single byte buffer with a ready/valid interface + */ +class Buffer extends Module { + val io = IO(new Bundle { + val in = Flipped(new UartIO()) + val out = new UartIO() + }) + + val empty :: full :: Nil = Enum(2) + val stateReg = RegInit(empty) + val dataReg = RegInit(0.U(8.W)) + + io.in.ready := stateReg === empty + io.out.valid := stateReg === full + + when(stateReg === empty) { + when(io.in.valid) { + dataReg := io.in.bits + stateReg := full + } + }.otherwise { // full + when(io.out.ready) { + stateReg := empty + } + } + io.out.bits := dataReg +} + +/** + * A transmitter with a single buffer. + */ +class BufferedTx(frequency: Int, baudRate: Int) extends Module { + val io = IO(new Bundle { + val txd = Output(UInt(1.W)) + val channel = Flipped(new UartIO()) + + }) + val tx = Module(new Tx(frequency, baudRate)) + val buf = Module(new Buffer) + + buf.io.in <> io.channel + tx.io.channel <> buf.io.out + io.txd <> tx.io.txd +} + +class Uart(frequency: Int, baudRate: Int) extends Module { + val io = IO(new Bundle { + val channels = Flipped(new AXI4LiteChannels(8, Parameters.DataBits)) + val rxd = Input(UInt(1.W)) + val txd = Output(UInt(1.W)) + + val signal_interrupt = Output(Bool()) + }) + val interrupt = RegInit(false.B) + val rxData = RegInit(0.U) + val slave = Module(new AXI4LiteSlave(8, Parameters.DataBits)) + slave.io.channels <> io.channels + + val tx = Module(new BufferedTx(frequency, baudRate)) + val rx = Module(new Rx(frequency, baudRate)) + + slave.io.bundle.read_data := 0.U + slave.io.bundle.read_valid := true.B + when(slave.io.bundle.read) { + when(slave.io.bundle.address === 0x4.U) { + slave.io.bundle.read_data := baudRate.U + }.elsewhen(slave.io.bundle.address === 0xC.U) { + slave.io.bundle.read_data := rxData + interrupt := false.B + } + } + + tx.io.channel.valid := false.B + tx.io.channel.bits := 0.U + when(slave.io.bundle.write) { + when(slave.io.bundle.address === 0x8.U) { + interrupt := slave.io.bundle.write_data =/= 0.U + }.elsewhen(slave.io.bundle.address === 0x10.U) { + tx.io.channel.valid := true.B + tx.io.channel.bits := slave.io.bundle.write_data + } + } + + io.txd := tx.io.txd + rx.io.rxd := io.rxd + + io.signal_interrupt := interrupt + rx.io.channel.ready := false.B + when(rx.io.channel.valid) { + rx.io.channel.ready := true.B + rxData := rx.io.channel.bits + interrupt := true.B + } +} diff --git a/mini-yatcpu/src/main/scala/peripheral/VGADisplay.scala b/mini-yatcpu/src/main/scala/peripheral/VGADisplay.scala new file mode 100644 index 0000000..644c595 --- /dev/null +++ b/mini-yatcpu/src/main/scala/peripheral/VGADisplay.scala @@ -0,0 +1,117 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package peripheral + +import chisel3._ + + +class VGASync extends Module { + val io = IO(new Bundle { + val hsync = Output(Bool()) + val vsync = Output(Bool()) + val video_on = Output(Bool()) + val p_tick = Output(Bool()) + val f_tick = Output(Bool()) + val x = Output(UInt(10.W)) + val y = Output(UInt(10.W)) + }) + + val DisplayHorizontal = ScreenInfo.DisplayHorizontal + val DisplayVertical = ScreenInfo.DisplayVertical + + val BorderLeft = 48 + val BorderRight = 16 + val BorderTop = 10 + val BorderBottom = 33 + + val RetraceHorizontal = 96 + val RetraceVertical = 2 + + val MaxHorizontal = DisplayHorizontal + BorderLeft + BorderRight + RetraceHorizontal - 1 + val MaxVertical = DisplayVertical + BorderTop + BorderBottom + RetraceVertical - 1 + + val RetraceHorizontalStart = DisplayHorizontal + BorderRight + val RetraceHorizontalEnd = RetraceHorizontalStart + RetraceHorizontal - 1 + + val RetraceVerticalStart = DisplayVertical + BorderBottom + val RetraceVerticalEnd = RetraceVerticalStart + RetraceVertical - 1 + + val pixel = RegInit(UInt(2.W), 0.U) + val pixel_next = Wire(UInt(2.W)) + val pixel_tick = Wire(Bool()) + + val v_count_reg = RegInit(UInt(10.W), 0.U) + val h_count_reg = RegInit(UInt(10.W), 0.U) + + val v_count_next = Wire(UInt(10.W)) + val h_count_next = Wire(UInt(10.W)) + + val vsync_reg = RegInit(Bool(), false.B) + val hsync_reg = RegInit(Bool(), false.B) + + val vsync_next = Wire(Bool()) + val hsync_next = Wire(Bool()) + + pixel_next := pixel + 1.U + pixel_tick := pixel === 0.U + + h_count_next := Mux( + pixel_tick, + Mux(h_count_reg === MaxHorizontal.U, 0.U, h_count_reg + 1.U), + h_count_reg + ) + + v_count_next := Mux( + pixel_tick && h_count_reg === MaxHorizontal.U, + Mux(v_count_reg === MaxVertical.U, 0.U, v_count_reg + 1.U), + v_count_reg + ) + + hsync_next := h_count_reg >= RetraceHorizontalStart.U && h_count_reg <= RetraceHorizontalEnd.U + vsync_next := v_count_reg >= RetraceVerticalStart.U && v_count_reg <= RetraceVerticalEnd.U + + pixel := pixel_next + hsync_reg := hsync_next + vsync_reg := vsync_next + v_count_reg := v_count_next + h_count_reg := h_count_next + + io.video_on := h_count_reg < DisplayHorizontal.U && v_count_reg < DisplayVertical.U + io.hsync := hsync_reg + io.vsync := vsync_reg + io.x := h_count_reg + io.y := v_count_reg + io.p_tick := pixel_tick + io.f_tick := io.x === 0.U && io.y === 0.U +} + +class VGADisplay extends Module { + val io = IO(new Bundle() { + val rgb = Input(UInt(24.W)) + val x = Output(UInt(16.W)) + val y = Output(UInt(16.W)) + val video_on = Output(Bool()) + + val hsync = Output(Bool()) + val vsync = Output(Bool()) + }) + + val sync = Module(new VGASync) + io.hsync := sync.io.hsync + io.vsync := sync.io.vsync + io.x := sync.io.x + io.y := sync.io.y + io.video_on := sync.io.y +} diff --git a/mini-yatcpu/src/main/scala/riscv/Parameters.scala b/mini-yatcpu/src/main/scala/riscv/Parameters.scala new file mode 100644 index 0000000..8d3d30d --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/Parameters.scala @@ -0,0 +1,68 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv + +import chisel3._ +import chisel3.util._ + +object ImplementationType { + val ThreeStage = 0 + val FiveStage = 1 +} + +object Parameters { + val AddrBits = 32 + val AddrWidth = AddrBits.W + + val InstructionBits = 32 + val InstructionWidth = InstructionBits.W + val DataBits = 32 + val DataWidth = DataBits.W + val ByteBits = 8 + val ByteWidth = ByteBits.W + val WordSize = Math.ceil(DataBits / ByteBits).toInt + + val PhysicalRegisters = 32 + val PhysicalRegisterAddrBits = log2Up(PhysicalRegisters) + val PhysicalRegisterAddrWidth = PhysicalRegisterAddrBits.W + + val CSRRegisterAddrBits = 12 + val CSRRegisterAddrWidth = CSRRegisterAddrBits.W + + val InterruptFlagBits = 32 + val InterruptFlagWidth = InterruptFlagBits.W + + val HoldStateBits = 3 + val StallStateWidth = HoldStateBits.W + + val MemorySizeInBytes = 32768 + val MemorySizeInWords = MemorySizeInBytes / 4 + + val EntryAddress = 0x1000.U(Parameters.AddrWidth) + + val MasterDeviceCount = 1 + val SlaveDeviceCount = 8 + val SlaveDeviceCountBits = log2Up(Parameters.SlaveDeviceCount) + // mmu + val PageSize = 4096 + val PageOffsetBits = log2Up(Parameters.PageSize) + val PageOffsetWidth = PageOffsetBits.W + + val PTESize = 32 + val PTEWidth = Parameters.PTESize.W + + + val PhysicalPageCount = Math.ceil(MemorySizeInBytes / PageSize).toInt +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/BusBundle.scala b/mini-yatcpu/src/main/scala/riscv/core/BusBundle.scala new file mode 100644 index 0000000..d8774bf --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/BusBundle.scala @@ -0,0 +1,32 @@ +// Copyright 2022 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core + +import chisel3._ +import riscv.Parameters + +class BusBundle extends Bundle { + val read = Output(Bool()) + val address = Output(UInt(Parameters.AddrWidth)) + val read_data = Input(UInt(Parameters.DataWidth)) + val read_valid = Input(Bool()) + val write = Output(Bool()) + val write_data = Output(UInt(Parameters.DataWidth)) + val write_strobe = Output(Vec(Parameters.WordSize, Bool())) + val write_valid = Input(Bool()) + val busy = Input(Bool()) + val request = Output(Bool()) + val granted = Input(Bool()) +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/CPU.scala b/mini-yatcpu/src/main/scala/riscv/core/CPU.scala new file mode 100644 index 0000000..d53936a --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/CPU.scala @@ -0,0 +1,32 @@ +// Copyright 2022 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core + +import chisel3._ +import riscv.ImplementationType +import riscv.core.fivestage.{CPU => FiveStageCPU} +import riscv.core.threestage.{CPU => ThreeStageCPU} + +class CPU(val implementation: Int = ImplementationType.FiveStage) extends Module { + val io = IO(new CPUBundle) + implementation match { + case ImplementationType.ThreeStage => + val cpu = Module(new ThreeStageCPU) + cpu.io <> io + case _ => + val cpu = Module(new FiveStageCPU) + cpu.io <> io + } +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/CPUBundle.scala b/mini-yatcpu/src/main/scala/riscv/core/CPUBundle.scala new file mode 100644 index 0000000..f18d398 --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/CPUBundle.scala @@ -0,0 +1,32 @@ +// Copyright 2022 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core + +import bus.AXI4LiteChannels +import chisel3._ +import riscv.Parameters + +class CPUBundle extends Bundle { + val axi4_channels = new AXI4LiteChannels(Parameters.AddrBits, Parameters.DataBits) + val bus_address = Output(UInt(Parameters.AddrWidth)) + val interrupt_flag = Input(UInt(Parameters.InterruptFlagWidth)) + val stall_flag_bus = Input(Bool()) + val debug_read_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth)) + val debug_read_data = Output(UInt(Parameters.DataWidth)) + + val instruction_valid = Input(Bool()) + val bus_busy = Output(Bool()) + val debug = Output(Vec(6, UInt(32.W))) +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/fivestage/ALU.scala b/mini-yatcpu/src/main/scala/riscv/core/fivestage/ALU.scala new file mode 100644 index 0000000..07584ff --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/fivestage/ALU.scala @@ -0,0 +1,69 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.fivestage + +import chisel3._ +import chisel3.util._ +import riscv.Parameters + +object ALUFunctions extends ChiselEnum { + val zero, add, sub, sll, slt, xor, or, and, srl, sra, sltu = Value +} + +class ALU extends Module { + val io = IO(new Bundle { + val func = Input(ALUFunctions()) + + val op1 = Input(UInt(Parameters.DataWidth)) + val op2 = Input(UInt(Parameters.DataWidth)) + + val result = Output(UInt(Parameters.DataWidth)) + }) + + io.result := 0.U + switch(io.func) { + is(ALUFunctions.add) { + io.result := io.op1 + io.op2 + } + is(ALUFunctions.sub) { + io.result := io.op1 - io.op2 + } + is(ALUFunctions.sll) { + io.result := io.op1 << io.op2(4, 0) + } + is(ALUFunctions.slt) { + io.result := io.op1.asSInt < io.op2.asSInt + } + is(ALUFunctions.xor) { + io.result := io.op1 ^ io.op2 + } + is(ALUFunctions.or) { + io.result := io.op1 | io.op2 + } + is(ALUFunctions.and) { + io.result := io.op1 & io.op2 + } + is(ALUFunctions.srl) { + io.result := io.op1 >> io.op2(4, 0) + } + is(ALUFunctions.sra) { + io.result := (io.op1.asSInt >> io.op2(4, 0)).asUInt + } + is(ALUFunctions.sltu) { + io.result := io.op1 < io.op2 + } + } + +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/fivestage/ALUControl.scala b/mini-yatcpu/src/main/scala/riscv/core/fivestage/ALUControl.scala new file mode 100644 index 0000000..142761f --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/fivestage/ALUControl.scala @@ -0,0 +1,82 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.fivestage + +import chisel3._ +import chisel3.util._ + +class ALUControl extends Module { + val io = IO(new Bundle { + val opcode = Input(UInt(7.W)) + val funct3 = Input(UInt(3.W)) + val funct7 = Input(UInt(7.W)) + + val alu_funct = Output(ALUFunctions()) + }) + + io.alu_funct := ALUFunctions.zero + + switch(io.opcode) { + is(InstructionTypes.I) { + io.alu_funct := MuxLookup(io.funct3, ALUFunctions.zero)( + IndexedSeq( + InstructionsTypeI.addi -> ALUFunctions.add, + InstructionsTypeI.slli -> ALUFunctions.sll, + InstructionsTypeI.slti -> ALUFunctions.slt, + InstructionsTypeI.sltiu -> ALUFunctions.sltu, + InstructionsTypeI.xori -> ALUFunctions.xor, + InstructionsTypeI.ori -> ALUFunctions.or, + InstructionsTypeI.andi -> ALUFunctions.and, + InstructionsTypeI.sri -> Mux(io.funct7(5), ALUFunctions.sra, ALUFunctions.srl) + ), + ) + } + is(InstructionTypes.RM) { + io.alu_funct := MuxLookup(io.funct3, ALUFunctions.zero)( + IndexedSeq( + InstructionsTypeR.add_sub -> Mux(io.funct7(5), ALUFunctions.sub, ALUFunctions.add), + InstructionsTypeR.sll -> ALUFunctions.sll, + InstructionsTypeR.slt -> ALUFunctions.slt, + InstructionsTypeR.sltu -> ALUFunctions.sltu, + InstructionsTypeR.xor -> ALUFunctions.xor, + InstructionsTypeR.or -> ALUFunctions.or, + InstructionsTypeR.and -> ALUFunctions.and, + InstructionsTypeR.sr -> Mux(io.funct7(5), ALUFunctions.sra, ALUFunctions.srl) + ), + ) + } + is(InstructionTypes.B) { + io.alu_funct := ALUFunctions.add + } + is(InstructionTypes.L) { + io.alu_funct := ALUFunctions.add + } + is(InstructionTypes.S) { + io.alu_funct := ALUFunctions.add + } + is(Instructions.jal) { + io.alu_funct := ALUFunctions.add + } + is(Instructions.jalr) { + io.alu_funct := ALUFunctions.add + } + is(Instructions.lui) { + io.alu_funct := ALUFunctions.add + } + is(Instructions.auipc) { + io.alu_funct := ALUFunctions.add + } + } +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/fivestage/CLINT.scala b/mini-yatcpu/src/main/scala/riscv/core/fivestage/CLINT.scala new file mode 100644 index 0000000..9c8bea2 --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/fivestage/CLINT.scala @@ -0,0 +1,225 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.fivestage + +import chisel3._ +import chisel3.util._ +import riscv.Parameters + +object InterruptStatus { + val None = 0x0.U(8.W) + val Timer0 = 0x1.U(8.W) + val Ret = 0xFF.U(8.W) +} + +object InterruptEntry { + val Timer0 = 0x4.U(8.W) +} + +object InterruptState { + val Idle = 0x0.U + val SyncAssert = 0x1.U + val AsyncAssert = 0x2.U + val MRET = 0x3.U +} + +object CSRState { + val Idle = 0x0.U + val MSTATUS = 0x1.U + val MEPC = 0x2.U + val MRET = 0x3.U + val MCAUSE = 0x4.U + val MTVAL = 0x5.U +} + +// Core Local Interrupt Controller +class CLINT extends Module { + val io = IO(new Bundle { + // Interrupt signals from peripherals + val interrupt_flag = Input(UInt(Parameters.InterruptFlagWidth)) + + // Current instruction from instruction decode + val instruction = Input(UInt(Parameters.InstructionWidth)) + val instruction_address_if = Input(UInt(Parameters.AddrWidth)) + + //exception signals from MMU etc. + val exception_signal = Input(Bool()) + + val instruction_address_cause_exception = Input(UInt(Parameters.AddrWidth)) + val exception_cause = Input(UInt(Parameters.DataWidth)) + val exception_val = Input(UInt(Parameters.AddrWidth)) + //trick for page-fault ,synchronous with mmu + val exception_token = Output(Bool()) + + val jump_flag = Input(Bool()) + val jump_address = Input(UInt(Parameters.AddrWidth)) + + val csr_mtvec = Input(UInt(Parameters.DataWidth)) + val csr_mepc = Input(UInt(Parameters.DataWidth)) + val csr_mstatus = Input(UInt(Parameters.DataWidth)) + + // Is global interrupt enabled (from MSTATUS)? + val interrupt_enable = Input(Bool()) + + val ctrl_stall_flag = Output(Bool()) + + val csr_reg_write_enable = Output(Bool()) + val csr_reg_write_address = Output(UInt(Parameters.CSRRegisterAddrWidth)) + val csr_reg_write_data = Output(UInt(Parameters.DataWidth)) + + val id_interrupt_handler_address = Output(UInt(Parameters.AddrWidth)) + val id_interrupt_assert = Output(Bool()) + }) + + val interrupt_state = WireInit(0.U) + val csr_state = RegInit(CSRState.Idle) + val instruction_address = RegInit(UInt(Parameters.AddrWidth), 0.U) + val cause = RegInit(UInt(Parameters.DataWidth), 0.U) + val trap_val = RegInit(UInt(Parameters.AddrWidth), 0.U) + val interrupt_assert = RegInit(Bool(), false.B) + val interrupt_handler_address = RegInit(UInt(Parameters.AddrWidth), 0.U) + val csr_reg_write_enable = RegInit(Bool(), false.B) + val csr_reg_write_address = RegInit(UInt(Parameters.CSRRegisterAddrWidth), 0.U) + val csr_reg_write_data = RegInit(UInt(Parameters.DataWidth), 0.U) + val exception_token = RegInit(false.B) + val exception_signal = RegInit(false.B) + io.ctrl_stall_flag := (interrupt_state =/= InterruptState.Idle || csr_state =/= CSRState.Idle) && !exception_token + io.exception_token := exception_token + + when(exception_signal && csr_state === CSRState.MCAUSE) { + exception_token := true.B + }.otherwise { + exception_token := false.B + } + + when(exception_token) { + exception_signal := false.B + }.elsewhen(exception_signal === false.B && io.exception_signal) { + exception_signal := true.B + } + + // Interrupt FSM + //exception cause SyncAssert + when(exception_signal || io.instruction === InstructionsEnv.ecall || io.instruction === InstructionsEnv.ebreak) { + interrupt_state := InterruptState.SyncAssert + }.elsewhen(io.interrupt_flag =/= InterruptStatus.None && io.interrupt_enable) { + interrupt_state := InterruptState.AsyncAssert + }.elsewhen(io.instruction === InstructionsRet.mret) { + interrupt_state := InterruptState.MRET + }.otherwise { + interrupt_state := InterruptState.Idle + } + + // CSR FSM + when(csr_state === CSRState.Idle) { + when(interrupt_state === InterruptState.SyncAssert) { + // Synchronous Interrupt + csr_state := CSRState.MEPC + //exception handling first then ecall and ebreak + instruction_address := Mux( + exception_signal, + io.instruction_address_cause_exception, + Mux( + io.jump_flag, + io.jump_address - 4.U, + io.instruction_address_if + ) + ) + + cause := Mux( + exception_signal, + io.exception_cause, + MuxLookup(io.instruction, 10.U)( + IndexedSeq( + InstructionsEnv.ecall -> 11.U, + InstructionsEnv.ebreak -> 3.U, + ) + ) + ) + // some trap will write mtval, otherwise set mtval to 0 + // todo: redesign CLINT to fully handle exception, like trap priority handling + // hint: currently we have only page_fault to write mtval + trap_val := Mux( + exception_signal, + io.exception_val, + 0.U + ) + }.elsewhen(interrupt_state === InterruptState.AsyncAssert) { // + // Asynchronous Interrupt + cause := 0x8000000BL.U // Interrupt from peripherals : Uart + when(io.interrupt_flag(0)) { + cause := 0x80000007L.U // Interrupt from timer + } + trap_val := 0.U + csr_state := CSRState.MEPC + instruction_address := Mux( + io.jump_flag, + io.jump_address, + io.instruction_address_if, + ) + }.elsewhen(interrupt_state === InterruptState.MRET) { + // Interrupt Return + csr_state := CSRState.MRET + } + }.elsewhen(csr_state === CSRState.MEPC) { + csr_state := CSRState.MSTATUS + }.elsewhen(csr_state === CSRState.MSTATUS) { + csr_state := CSRState.MTVAL + }.elsewhen(csr_state === CSRState.MTVAL) { + csr_state := CSRState.MCAUSE + }.elsewhen(csr_state === CSRState.MCAUSE) { + csr_state := CSRState.Idle + }.elsewhen(csr_state === CSRState.MRET) { + csr_state := CSRState.Idle + }.otherwise { + csr_state := CSRState.Idle + } + + csr_reg_write_enable := csr_state =/= CSRState.Idle + csr_reg_write_address := Cat(Fill(20, 0.U(1.W)), MuxLookup(csr_state, 0.U(Parameters.CSRRegisterAddrWidth))( + IndexedSeq( + CSRState.MEPC -> CSRRegister.MEPC, + CSRState.MCAUSE -> CSRRegister.MCAUSE, + CSRState.MSTATUS -> CSRRegister.MSTATUS, + CSRState.MRET -> CSRRegister.MSTATUS, + CSRState.MTVAL -> CSRRegister.MTVAL + ) + )) + + csr_reg_write_data := MuxLookup(csr_state, 0.U(Parameters.DataWidth))( + IndexedSeq( + CSRState.MEPC -> instruction_address, + CSRState.MCAUSE -> cause, + CSRState.MSTATUS -> Cat(io.csr_mstatus(31, 4), 0.U(1.W), io.csr_mstatus(2, 0)), + CSRState.MRET -> Cat(io.csr_mstatus(31, 4), io.csr_mstatus(7), io.csr_mstatus(2, 0)), + CSRState.MTVAL -> trap_val, + ) + ) + + io.csr_reg_write_enable := csr_reg_write_enable + io.csr_reg_write_address := csr_reg_write_address + io.csr_reg_write_data := csr_reg_write_data + + interrupt_assert := csr_state === CSRState.MCAUSE || csr_state === CSRState.MRET + interrupt_handler_address := MuxLookup(csr_state, 0.U(Parameters.AddrWidth))( + IndexedSeq( + CSRState.MCAUSE -> io.csr_mtvec, + CSRState.MRET -> io.csr_mepc, + ) + ) + + io.id_interrupt_assert := interrupt_assert + io.id_interrupt_handler_address := interrupt_handler_address +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/fivestage/CPU.scala b/mini-yatcpu/src/main/scala/riscv/core/fivestage/CPU.scala new file mode 100644 index 0000000..0906219 --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/fivestage/CPU.scala @@ -0,0 +1,385 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.fivestage + +import bus.AXI4LiteMaster +import chisel3._ +import riscv.Parameters +import riscv.core.CPUBundle + +object BUSGranted extends ChiselEnum { + val idle, if_granted, mem_granted, mmu_mem_granted, mmu_if_granted = Value +} + +object MEMAccessState extends ChiselEnum { + val idle, if_address_translate, mem_address_translate, mem_access, if_access = Value +} + +class CPU extends Module { + val io = IO(new CPUBundle) + + val ctrl = Module(new Control) + val regs = Module(new RegisterFile) + val inst_fetch = Module(new InstructionFetch) + val if2id = Module(new IF2ID) + val id = Module(new InstructionDecode) + val id2ex = Module(new ID2EX) + val ex = Module(new Execute) + val ex2mem = Module(new EX2MEM) + val mem = Module(new MemoryAccess) + val mem2wb = Module(new MEM2WB) + val wb = Module(new WriteBack) + val forwarding = Module(new Forwarding) + val clint = Module(new CLINT) + val csr_regs = Module(new CSR) + val axi4_master = Module(new AXI4LiteMaster(Parameters.AddrBits, Parameters.DataBits)) + val mmu = Module(new MMU) + axi4_master.io.channels <> io.axi4_channels + io.debug(0) := ex.io.reg1_data + io.debug(1) := ex.io.reg2_data + io.debug(2) := ex.io.instruction_address + io.debug(3) := ex.io.instruction + io.debug(4) := inst_fetch.io.jump_address_id + io.debug(5) := inst_fetch.io.jump_flag_id + io.bus_busy := axi4_master.io.bundle.busy + + val bus_granted = RegInit(BUSGranted.idle) + val mem_access_state = RegInit(MEMAccessState.idle) + val virtual_address = RegInit(UInt(Parameters.AddrWidth), 0.U) + val physical_address = RegInit(UInt(Parameters.AddrWidth), 0.U) + val mmu_restart = RegInit(false.B) + val pending = RegInit(false.B) //play the same role as pending_jump in Inst_fetch + + //bus arbitration + when(mem_access_state === MEMAccessState.idle) { + bus_granted := BUSGranted.idle + when(!axi4_master.io.bundle.busy && !axi4_master.io.bundle.read_valid) { + when(csr_regs.io.mmu_enable) { + when(mem.io.bus.request) { + mem_access_state := MEMAccessState.mem_address_translate + bus_granted := BUSGranted.mmu_mem_granted + virtual_address := ex2mem.io.output_alu_result + }.elsewhen(inst_fetch.io.bus.request && io.instruction_valid && inst_fetch.io.pc_valid) { + mem_access_state := MEMAccessState.if_address_translate + bus_granted := BUSGranted.mmu_if_granted + virtual_address := inst_fetch.io.id_instruction_address + } + }.otherwise { + when(mem.io.bus.request) { + mem_access_state := MEMAccessState.mem_access + physical_address := ex2mem.io.output_alu_result + bus_granted := BUSGranted.mem_granted + }.elsewhen(inst_fetch.io.bus.request && io.instruction_valid && inst_fetch.io.pc_valid) { + mem_access_state := MEMAccessState.if_access + bus_granted := BUSGranted.if_granted + physical_address := inst_fetch.io.id_instruction_address + } + } + } + }.elsewhen(mem_access_state === MEMAccessState.mem_address_translate) { + when(clint.io.exception_token) { + mem_access_state := MEMAccessState.if_address_translate + bus_granted := BUSGranted.mmu_if_granted + virtual_address := id.io.if_jump_address + }.elsewhen(mmu.io.pa_valid) { + mem_access_state := MEMAccessState.mem_access + bus_granted := BUSGranted.mem_granted + physical_address := mmu.io.pa + } + }.elsewhen(mem_access_state === MEMAccessState.if_address_translate) { + //"Interrupt" the IF address translation, turn to mem address translation + when(mem.io.bus.request) { + mmu_restart := true.B + when(mmu.io.restart_done) { + mmu_restart := false.B + mem_access_state := MEMAccessState.mem_address_translate + bus_granted := BUSGranted.mmu_mem_granted + virtual_address := ex2mem.io.output_alu_result + } + }.otherwise { + when(pending) { + when(mmu.io.restart_done) { + mmu_restart := false.B + pending := false.B + mem_access_state := MEMAccessState.if_address_translate + bus_granted := BUSGranted.mmu_if_granted + virtual_address := inst_fetch.io.id_instruction_address + } + }.otherwise { + when(!id.io.if_jump_flag && mmu.io.pa_valid) { + mem_access_state := MEMAccessState.if_access + bus_granted := BUSGranted.if_granted + physical_address := mmu.io.pa + } + } + + when(id.io.if_jump_flag) { + mmu_restart := true.B + pending := true.B + } + } + }.elsewhen(mem_access_state === MEMAccessState.mem_access) { + when(mem.io.bus.read_valid || mem.io.bus.write_valid) { + mem_access_state := MEMAccessState.idle + bus_granted := BUSGranted.idle + } + }.elsewhen(mem_access_state === MEMAccessState.if_access) { + when(inst_fetch.io.bus.read_valid) { + bus_granted := BUSGranted.idle + mem_access_state := MEMAccessState.idle + } + } + + when(bus_granted === BUSGranted.mmu_if_granted || bus_granted === BUSGranted.mmu_mem_granted) { + io.bus_address := mmu.io.bus.address + axi4_master.io.bundle.read := mmu.io.bus.read + axi4_master.io.bundle.address := mmu.io.bus.address + axi4_master.io.bundle.write := mmu.io.bus.write + axi4_master.io.bundle.write_data := mmu.io.bus.write_data + axi4_master.io.bundle.write_strobe := mmu.io.bus.write_strobe + }.elsewhen(bus_granted === BUSGranted.mem_granted) { + io.bus_address := mem.io.bus.address + axi4_master.io.bundle.read := mem.io.bus.read + axi4_master.io.bundle.address := mem.io.bus.address + axi4_master.io.bundle.write := mem.io.bus.write + axi4_master.io.bundle.write_data := mem.io.bus.write_data + axi4_master.io.bundle.write_strobe := mem.io.bus.write_strobe + }.otherwise { + io.bus_address := inst_fetch.io.bus.address + axi4_master.io.bundle.read := inst_fetch.io.bus.read + axi4_master.io.bundle.address := inst_fetch.io.bus.address + axi4_master.io.bundle.write := inst_fetch.io.bus.write + axi4_master.io.bundle.write_data := inst_fetch.io.bus.write_data + axi4_master.io.bundle.write_strobe := inst_fetch.io.bus.write_strobe + } + + inst_fetch.io.bus.read_valid := Mux( + bus_granted === BUSGranted.if_granted && io.instruction_valid, + axi4_master.io.bundle.read_valid, + false.B + ) + inst_fetch.io.bus.read_data := Mux( + bus_granted === BUSGranted.if_granted && io.instruction_valid, + axi4_master.io.bundle.read_data, + 0.U + ) + inst_fetch.io.bus.write_valid := false.B + inst_fetch.io.bus.busy := Mux( + bus_granted === BUSGranted.if_granted && io.instruction_valid, + axi4_master.io.bundle.busy, + false.B + ) + mem.io.bus.read_valid := Mux( + bus_granted === BUSGranted.mem_granted, + axi4_master.io.bundle.read_valid, + false.B + ) + mem.io.bus.read_data := Mux( + bus_granted === BUSGranted.mem_granted, + axi4_master.io.bundle.read_data, + 0.U + ) + mem.io.bus.write_valid := Mux( + bus_granted === BUSGranted.mem_granted, + axi4_master.io.bundle.write_valid, + false.B + ) + mem.io.bus.busy := Mux( + bus_granted === BUSGranted.mem_granted, + axi4_master.io.bundle.busy, + false.B + ) + mmu.io.bus.read_valid := Mux( + bus_granted === BUSGranted.mmu_if_granted || bus_granted === BUSGranted.mmu_mem_granted, + axi4_master.io.bundle.read_valid, + false.B + ) + mmu.io.bus.read_data := Mux( + bus_granted === BUSGranted.mmu_if_granted || bus_granted === BUSGranted.mmu_mem_granted, + axi4_master.io.bundle.read_data, + 0.U + ) + mmu.io.bus.write_valid := Mux( + bus_granted === BUSGranted.mmu_if_granted || bus_granted === BUSGranted.mmu_mem_granted, + axi4_master.io.bundle.write_valid, + false.B + ) + mmu.io.bus.busy := Mux( + bus_granted === BUSGranted.mmu_if_granted || bus_granted === BUSGranted.mmu_mem_granted, + axi4_master.io.bundle.busy, + false.B + ) + + mmu.io.instructions := ex2mem.io.output_instruction + mmu.io.instructions_address := ex2mem.io.output_instruction_address + mmu.io.virtual_address := virtual_address + mmu.io.bus.granted := bus_granted === BUSGranted.mmu_mem_granted || bus_granted === BUSGranted.mmu_if_granted + mmu.io.page_fault_responed := false.B + mmu.io.ppn_from_satp := csr_regs.io.mmu_csr_satp(21, 0) + mmu.io.page_fault_responed := clint.io.exception_token + mmu.io.mmu_occupied_by_mem := bus_granted === BUSGranted.mmu_mem_granted + mmu.io.restart := mmu_restart + + inst_fetch.io.bus.granted := bus_granted === BUSGranted.if_granted + inst_fetch.io.physical_address := physical_address + + mem.io.bus.granted := bus_granted === BUSGranted.mem_granted + mem.io.physical_address := physical_address + + ctrl.io.jump_flag := id.io.if_jump_flag + ctrl.io.jump_instruction_id := id.io.ctrl_jump_instruction + ctrl.io.stall_flag_if := inst_fetch.io.ctrl_stall_flag + ctrl.io.stall_flag_mem := mem.io.ctrl_stall_flag + ctrl.io.stall_flag_clint := clint.io.ctrl_stall_flag + ctrl.io.stall_flag_bus := io.stall_flag_bus + ctrl.io.rs1_id := id.io.regs_reg1_read_address + ctrl.io.rs2_id := id.io.regs_reg2_read_address + ctrl.io.memory_read_enable_ex := id2ex.io.output_memory_read_enable + ctrl.io.rd_ex := id2ex.io.output_regs_write_address + ctrl.io.memory_read_enable_mem := ex2mem.io.output_memory_read_enable + ctrl.io.rd_mem := ex2mem.io.output_regs_write_address + ctrl.io.csr_start_paging := csr_regs.io.start_paging + + regs.io.write_enable := mem2wb.io.output_regs_write_enable + regs.io.write_address := mem2wb.io.output_regs_write_address + regs.io.write_data := wb.io.regs_write_data + regs.io.read_address1 := id.io.regs_reg1_read_address + regs.io.read_address2 := id.io.regs_reg2_read_address + + regs.io.debug_read_address := io.debug_read_address + io.debug_read_data := regs.io.debug_read_data + + inst_fetch.io.stall_flag_ctrl := ctrl.io.pc_stall + inst_fetch.io.jump_flag_id := id.io.if_jump_flag + inst_fetch.io.jump_address_id := id.io.if_jump_address + + if2id.io.stall_flag := ctrl.io.if_stall + if2id.io.flush_enable := ctrl.io.if_flush + if2id.io.instruction := inst_fetch.io.id_instruction + if2id.io.instruction_address := inst_fetch.io.id_instruction_address + if2id.io.interrupt_flag := io.interrupt_flag + + id.io.instruction := if2id.io.output_instruction + id.io.instruction_address := if2id.io.output_instruction_address + id.io.reg1_data := regs.io.read_data1 + id.io.reg2_data := regs.io.read_data2 + id.io.forward_from_mem := mem.io.forward_data + id.io.forward_from_wb := wb.io.regs_write_data + id.io.reg1_forward := forwarding.io.reg1_forward_id + id.io.reg2_forward := forwarding.io.reg2_forward_id + id.io.interrupt_assert := clint.io.id_interrupt_assert + id.io.interrupt_handler_address := clint.io.id_interrupt_handler_address + + id2ex.io.stall_flag := ctrl.io.id_stall + id2ex.io.flush_enable := ctrl.io.id_flush + id2ex.io.instruction := if2id.io.output_instruction + id2ex.io.instruction_address := if2id.io.output_instruction_address + id2ex.io.regs_write_enable := id.io.ex_reg_write_enable + id2ex.io.regs_write_address := id.io.ex_reg_write_address + id2ex.io.regs_write_source := id.io.ex_reg_write_source + id2ex.io.reg1_data := regs.io.read_data1 + id2ex.io.reg2_data := regs.io.read_data2 + id2ex.io.immediate := id.io.ex_immediate + id2ex.io.aluop1_source := id.io.ex_aluop1_source + id2ex.io.aluop2_source := id.io.ex_aluop2_source + id2ex.io.csr_write_enable := id.io.ex_csr_write_enable + id2ex.io.csr_address := id.io.ex_csr_address + id2ex.io.memory_read_enable := id.io.ex_memory_read_enable + id2ex.io.memory_write_enable := id.io.ex_memory_write_enable + id2ex.io.csr_read_data := csr_regs.io.id_reg_data + + ex.io.instruction := id2ex.io.output_instruction + ex.io.instruction_address := id2ex.io.output_instruction_address + ex.io.reg1_data := id2ex.io.output_reg1_data + ex.io.reg2_data := id2ex.io.output_reg2_data + ex.io.immediate := id2ex.io.output_immediate + ex.io.aluop1_source := id2ex.io.output_aluop1_source + ex.io.aluop2_source := id2ex.io.output_aluop2_source + ex.io.csr_read_data := id2ex.io.output_csr_read_data + ex.io.forward_from_mem := mem.io.forward_data + ex.io.forward_from_wb := wb.io.regs_write_data + ex.io.reg1_forward := forwarding.io.reg1_forward_ex + ex.io.reg2_forward := forwarding.io.reg2_forward_ex + + ex2mem.io.stall_flag := ctrl.io.ex_stall + ex2mem.io.flush_enable := false.B + ex2mem.io.regs_write_enable := id2ex.io.output_regs_write_enable + ex2mem.io.regs_write_source := id2ex.io.output_regs_write_source + ex2mem.io.regs_write_address := id2ex.io.output_regs_write_address + ex2mem.io.instruction_address := id2ex.io.output_instruction_address + ex2mem.io.instruction := id2ex.io.output_instruction + ex2mem.io.reg1_data := id2ex.io.output_reg1_data + ex2mem.io.reg2_data := id2ex.io.output_reg2_data + ex2mem.io.memory_read_enable := id2ex.io.output_memory_read_enable + ex2mem.io.memory_write_enable := id2ex.io.output_memory_write_enable + ex2mem.io.alu_result := ex.io.mem_alu_result + ex2mem.io.csr_read_data := id2ex.io.output_csr_read_data + + mem.io.alu_result := ex2mem.io.output_alu_result + mem.io.reg2_data := ex2mem.io.output_reg2_data + mem.io.memory_read_enable := ex2mem.io.output_memory_read_enable + mem.io.memory_write_enable := ex2mem.io.output_memory_write_enable + mem.io.funct3 := ex2mem.io.output_instruction(14, 12) + mem.io.regs_write_source := ex2mem.io.output_regs_write_source + mem.io.csr_read_data := ex2mem.io.output_csr_read_data + mem.io.clint_exception_token := clint.io.exception_token + + mem2wb.io.instruction_address := ex2mem.io.output_instruction_address + mem2wb.io.alu_result := ex2mem.io.output_alu_result + mem2wb.io.regs_write_enable := ex2mem.io.output_regs_write_enable + mem2wb.io.regs_write_source := ex2mem.io.output_regs_write_source + mem2wb.io.regs_write_address := ex2mem.io.output_regs_write_address + mem2wb.io.memory_read_data := mem.io.wb_memory_read_data + mem2wb.io.csr_read_data := ex2mem.io.output_csr_read_data + + wb.io.instruction_address := mem2wb.io.output_instruction_address + wb.io.alu_result := mem2wb.io.output_alu_result + wb.io.memory_read_data := mem2wb.io.output_memory_read_data + wb.io.regs_write_source := mem2wb.io.output_regs_write_source + wb.io.csr_read_data := mem2wb.io.output_csr_read_data + + forwarding.io.rs1_id := id.io.regs_reg1_read_address + forwarding.io.rs2_id := id.io.regs_reg2_read_address + forwarding.io.rs1_ex := id2ex.io.output_instruction(19, 15) + forwarding.io.rs2_ex := id2ex.io.output_instruction(24, 20) + forwarding.io.rd_mem := ex2mem.io.output_regs_write_address + forwarding.io.reg_write_enable_mem := ex2mem.io.output_regs_write_enable + forwarding.io.rd_wb := mem2wb.io.output_regs_write_address + forwarding.io.reg_write_enable_wb := mem2wb.io.output_regs_write_enable + + clint.io.instruction := if2id.io.output_instruction + clint.io.instruction_address_if := inst_fetch.io.id_instruction_address + clint.io.jump_flag := id.io.if_jump_flag + clint.io.jump_address := id.io.clint_jump_address + clint.io.csr_mepc := csr_regs.io.clint_csr_mepc + clint.io.csr_mtvec := csr_regs.io.clint_csr_mtvec + clint.io.csr_mstatus := csr_regs.io.clint_csr_mstatus + clint.io.interrupt_enable := csr_regs.io.interrupt_enable + clint.io.interrupt_flag := if2id.io.output_interrupt_flag + //todo: change it for handling more exceptions + clint.io.exception_signal := mmu.io.page_fault_signals + clint.io.instruction_address_cause_exception := mmu.io.epc + clint.io.exception_val := mmu.io.va_cause_page_fault + clint.io.exception_cause := mmu.io.ecause + + csr_regs.io.reg_write_enable_ex := id2ex.io.output_csr_write_enable + csr_regs.io.reg_write_address_ex := id2ex.io.output_csr_address + csr_regs.io.reg_write_data_ex := ex.io.csr_write_data + csr_regs.io.reg_read_address_id := id.io.ex_csr_address + csr_regs.io.reg_write_enable_clint := clint.io.csr_reg_write_enable + csr_regs.io.reg_write_address_clint := clint.io.csr_reg_write_address + csr_regs.io.reg_write_data_clint := clint.io.csr_reg_write_data + csr_regs.io.reg_read_address_clint := 0.U +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/fivestage/CSR.scala b/mini-yatcpu/src/main/scala/riscv/core/fivestage/CSR.scala new file mode 100644 index 0000000..7f72a3d --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/fivestage/CSR.scala @@ -0,0 +1,141 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.fivestage + +import chisel3._ +import chisel3.util._ +import riscv.Parameters + + +object CSRRegister { + // Refer to Spec. Vol.II Page 8-10 + val CycleL = 0xc00.U(Parameters.CSRRegisterAddrWidth) + val CycleH = 0xc80.U(Parameters.CSRRegisterAddrWidth) + val MTVEC = 0x305.U(Parameters.CSRRegisterAddrWidth) + val MCAUSE = 0x342.U(Parameters.CSRRegisterAddrWidth) + val MEPC = 0x341.U(Parameters.CSRRegisterAddrWidth) + val MIE = 0x304.U(Parameters.CSRRegisterAddrWidth) + val MSTATUS = 0x300.U(Parameters.CSRRegisterAddrWidth) + val MSCRATCH = 0x340.U(Parameters.CSRRegisterAddrWidth) + val MTVAL = 0x343.U(Parameters.CSRRegisterAddrWidth) + val SATP = 0x180.U(Parameters.CSRRegisterAddrWidth) +} + +class CSR extends Module { + val io = IO(new Bundle { + val reg_write_enable_ex = Input(Bool()) + val reg_read_address_id = Input(UInt(Parameters.CSRRegisterAddrWidth)) + val reg_write_address_ex = Input(UInt(Parameters.CSRRegisterAddrWidth)) + val reg_write_data_ex = Input(UInt(Parameters.DataWidth)) + + val reg_write_enable_clint = Input(Bool()) + val reg_read_address_clint = Input(UInt(Parameters.CSRRegisterAddrWidth)) + val reg_write_address_clint = Input(UInt(Parameters.CSRRegisterAddrWidth)) + val reg_write_data_clint = Input(UInt(Parameters.DataWidth)) + + val interrupt_enable = Output(Bool()) + val mmu_enable = Output(Bool()) + val id_reg_data = Output(UInt(Parameters.DataWidth)) + + val start_paging = Output(Bool()) + + val clint_reg_data = Output(UInt(Parameters.DataWidth)) + val clint_csr_mtvec = Output(UInt(Parameters.DataWidth)) + val clint_csr_mepc = Output(UInt(Parameters.DataWidth)) + val clint_csr_mstatus = Output(UInt(Parameters.DataWidth)) + val mmu_csr_satp = Output(UInt(Parameters.DataWidth)) + }) + + + val cycles = RegInit(UInt(64.W), 0.U) + val mtvec = RegInit(UInt(Parameters.DataWidth), 0.U) + val mcause = RegInit(UInt(Parameters.DataWidth), 0.U) + val mepc = RegInit(UInt(Parameters.DataWidth), 0.U) + val mie = RegInit(UInt(Parameters.DataWidth), 0.U) + val mstatus = RegInit(UInt(Parameters.DataWidth), 0.U) + val mscratch = RegInit(UInt(Parameters.DataWidth), 0.U) + val mtval = RegInit(UInt(Parameters.DataWidth), 0.U) + val satp = RegInit(UInt(Parameters.DataWidth), 0.U) + + cycles := cycles + 1.U + io.clint_csr_mtvec := mtvec + io.clint_csr_mepc := mepc + io.clint_csr_mstatus := mstatus + io.interrupt_enable := mstatus(3) === 1.U + io.mmu_csr_satp := satp + io.mmu_enable := satp(31) === 1.U + io.start_paging := false.B + + val reg_write_address = Wire(UInt(Parameters.CSRRegisterAddrWidth)) + val reg_write_data = Wire(UInt(Parameters.DataWidth)) + reg_write_address := 0.U + reg_write_data := 0.U + + val reg_read_address = Wire(UInt(Parameters.CSRRegisterAddrWidth)) + val reg_read_data = Wire(UInt(Parameters.DataWidth)) + reg_read_address := 0.U + reg_read_data := 0.U + + when(io.reg_write_enable_ex) { + reg_write_address := io.reg_write_address_ex(11, 0) + reg_write_data := io.reg_write_data_ex + }.elsewhen(io.reg_write_enable_clint) { + reg_write_address := io.reg_write_address_clint(11, 0) + reg_write_data := io.reg_write_data_clint + } + + when(reg_write_address === CSRRegister.MTVEC) { + mtvec := reg_write_data + }.elsewhen(reg_write_address === CSRRegister.MCAUSE) { + mcause := reg_write_data + }.elsewhen(reg_write_address === CSRRegister.MEPC) { + mepc := reg_write_data + }.elsewhen(reg_write_address === CSRRegister.MIE) { + mie := reg_write_data + }.elsewhen(reg_write_address === CSRRegister.MSTATUS) { + mstatus := reg_write_data + }.elsewhen(reg_write_address === CSRRegister.MSCRATCH) { + mscratch := reg_write_data + }.elsewhen(reg_write_address === CSRRegister.MTVAL) { + mtval := reg_write_data + }.elsewhen(reg_write_address === CSRRegister.SATP) { + satp := reg_write_data + when(reg_write_data(31) === 1.U && satp(31) === 0.U) { + io.start_paging := true.B + } + } + + val regLUT = + IndexedSeq( + CSRRegister.CycleL -> cycles(31, 0), + CSRRegister.CycleH -> cycles(63, 32), + CSRRegister.MTVEC -> mtvec, + CSRRegister.MCAUSE -> mcause, + CSRRegister.MEPC -> mepc, + CSRRegister.MIE -> mie, + CSRRegister.MSTATUS -> mstatus, + CSRRegister.MSCRATCH -> mscratch, + CSRRegister.MTVAL -> mtval, + CSRRegister.SATP -> satp, + ) + + io.id_reg_data := MuxLookup(io.reg_read_address_id, 0.U)( + regLUT + ) + + io.clint_reg_data := MuxLookup(io.reg_read_address_clint, 0.U)( + regLUT + ) +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/fivestage/Cache.scala b/mini-yatcpu/src/main/scala/riscv/core/fivestage/Cache.scala new file mode 100644 index 0000000..4b75d4a --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/fivestage/Cache.scala @@ -0,0 +1,23 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.fivestage + +import chisel3._ + +class Cache(cacheLineBytes: Int, associativity: Int, cacheLines: Int) extends Module { + val io = IO(new Bundle { + + }) +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/fivestage/Control.scala b/mini-yatcpu/src/main/scala/riscv/core/fivestage/Control.scala new file mode 100644 index 0000000..3700dcc --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/fivestage/Control.scala @@ -0,0 +1,55 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.fivestage + +import chisel3._ +import riscv.Parameters + +class Control extends Module { + val io = IO(new Bundle { + val jump_flag = Input(Bool()) + val jump_instruction_id = Input(Bool()) + val stall_flag_if = Input(Bool()) + val stall_flag_mem = Input(Bool()) + val stall_flag_clint = Input(Bool()) + val stall_flag_bus = Input(Bool()) + val rs1_id = Input(UInt(Parameters.PhysicalRegisterAddrWidth)) + val rs2_id = Input(UInt(Parameters.PhysicalRegisterAddrWidth)) + val memory_read_enable_ex = Input(Bool()) + val rd_ex = Input(UInt(Parameters.PhysicalRegisterAddrWidth)) + val memory_read_enable_mem = Input(Bool()) + val rd_mem = Input(UInt(Parameters.PhysicalRegisterAddrWidth)) + val csr_start_paging = Input(Bool()) + + val if_flush = Output(Bool()) + val id_flush = Output(Bool()) + val pc_stall = Output(Bool()) + val if_stall = Output(Bool()) + val id_stall = Output(Bool()) + val ex_stall = Output(Bool()) + }) + + val id_hazard = (io.memory_read_enable_ex || io.jump_instruction_id) && io.rd_ex =/= 0.U && (io.rd_ex === io.rs1_id + || io.rd_ex === io.rs2_id) || + io.jump_instruction_id && io.memory_read_enable_mem && io.rd_mem =/= 0.U && (io.rd_mem === io.rs1_id || io.rd_mem + === io.rs2_id) + io.if_flush := io.jump_flag && !id_hazard || io.csr_start_paging + io.id_flush := id_hazard || io.csr_start_paging + + io.pc_stall := io.stall_flag_mem || io.stall_flag_clint || id_hazard || io.stall_flag_bus || io.stall_flag_if + io.if_stall := io.stall_flag_mem || io.stall_flag_clint || id_hazard + io.id_stall := io.stall_flag_mem || io.stall_flag_clint + io.ex_stall := io.stall_flag_mem || io.stall_flag_clint +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/fivestage/EX2MEM.scala b/mini-yatcpu/src/main/scala/riscv/core/fivestage/EX2MEM.scala new file mode 100644 index 0000000..c18c962 --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/fivestage/EX2MEM.scala @@ -0,0 +1,115 @@ +// Copyright 2022 Canbin Huang +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.fivestage + +import chisel3._ +import riscv.Parameters + +class EX2MEM extends Module { + val io = IO(new Bundle() { + val stall_flag = Input(Bool()) + val flush_enable = Input(Bool()) + val regs_write_enable = Input(Bool()) + val regs_write_source = Input(UInt(2.W)) + val regs_write_address = Input(UInt(Parameters.AddrWidth)) + val instruction_address = Input(UInt(Parameters.AddrWidth)) + val instruction = Input(UInt(Parameters.DataWidth)) + val reg1_data = Input(UInt(Parameters.DataWidth)) + val reg2_data = Input(UInt(Parameters.DataWidth)) + val memory_read_enable = Input(Bool()) + val memory_write_enable = Input(Bool()) + val alu_result = Input(UInt(Parameters.DataWidth)) + val csr_read_data = Input(UInt(Parameters.DataWidth)) + + val output_regs_write_enable = Output(Bool()) + val output_regs_write_source = Output(UInt(2.W)) + val output_regs_write_address = Output(UInt(Parameters.AddrWidth)) + val output_instruction_address = Output(UInt(Parameters.AddrWidth)) + val output_instruction = Output(UInt(Parameters.DataWidth)) + val output_reg1_data = Output(UInt(Parameters.DataWidth)) + val output_reg2_data = Output(UInt(Parameters.DataWidth)) + val output_memory_read_enable = Output(Bool()) + val output_memory_write_enable = Output(Bool()) + val output_alu_result = Output(UInt(Parameters.DataWidth)) + val output_csr_read_data = Output(UInt(Parameters.DataWidth)) + }) + val write_enable = !io.stall_flag + + val regs_write_enable = Module(new PipelineRegister(1)) + regs_write_enable.io.in := io.regs_write_enable + regs_write_enable.io.write_enable := write_enable + regs_write_enable.io.flush_enable := io.flush_enable + io.output_regs_write_enable := regs_write_enable.io.out + + val regs_write_source = Module(new PipelineRegister(2)) + regs_write_source.io.in := io.regs_write_source + regs_write_source.io.write_enable := write_enable + regs_write_source.io.flush_enable := io.flush_enable + io.output_regs_write_source := regs_write_source.io.out + + val regs_write_address = Module(new PipelineRegister(Parameters.PhysicalRegisterAddrBits)) + regs_write_address.io.in := io.regs_write_address + regs_write_address.io.write_enable := write_enable + regs_write_address.io.flush_enable := io.flush_enable + io.output_regs_write_address := regs_write_address.io.out + + val instruction_address = Module(new PipelineRegister(Parameters.AddrBits)) + instruction_address.io.in := io.instruction_address + instruction_address.io.write_enable := write_enable + instruction_address.io.flush_enable := io.flush_enable + io.output_instruction_address := instruction_address.io.out + + val instruction = Module(new PipelineRegister(Parameters.InstructionBits)) + instruction.io.in := io.instruction + instruction.io.write_enable := write_enable + instruction.io.flush_enable := io.flush_enable + io.output_instruction := instruction.io.out + + val reg1_data = Module(new PipelineRegister()) + reg1_data.io.in := io.reg1_data + reg1_data.io.write_enable := write_enable + reg1_data.io.flush_enable := io.flush_enable + io.output_reg1_data := reg1_data.io.out + + val reg2_data = Module(new PipelineRegister()) + reg2_data.io.in := io.reg2_data + reg2_data.io.write_enable := write_enable + reg2_data.io.flush_enable := io.flush_enable + io.output_reg2_data := reg2_data.io.out + + val alu_result = Module(new PipelineRegister()) + alu_result.io.in := io.alu_result + alu_result.io.write_enable := write_enable + alu_result.io.flush_enable := io.flush_enable + io.output_alu_result := alu_result.io.out + + val memory_read_enable = Module(new PipelineRegister(1)) + memory_read_enable.io.in := io.memory_read_enable + memory_read_enable.io.write_enable := write_enable + memory_read_enable.io.flush_enable := io.flush_enable + io.output_memory_read_enable := memory_read_enable.io.out + + val memory_write_enable = Module(new PipelineRegister(1)) + memory_write_enable.io.in := io.memory_write_enable + memory_write_enable.io.write_enable := write_enable + memory_write_enable.io.flush_enable := io.flush_enable + io.output_memory_write_enable := memory_write_enable.io.out + + val csr_read_data = Module(new PipelineRegister()) + csr_read_data.io.in := io.csr_read_data + csr_read_data.io.write_enable := write_enable + csr_read_data.io.flush_enable := io.flush_enable + io.output_csr_read_data := csr_read_data.io.out +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/fivestage/Execute.scala b/mini-yatcpu/src/main/scala/riscv/core/fivestage/Execute.scala new file mode 100644 index 0000000..6d79207 --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/fivestage/Execute.scala @@ -0,0 +1,86 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.fivestage + +import chisel3._ +import chisel3.util._ +import riscv.Parameters + +object MemoryAccessStates extends ChiselEnum { + val Idle, Read, Write, ReadWrite = Value +} + +class Execute extends Module { + val io = IO(new Bundle { + val instruction = Input(UInt(Parameters.InstructionWidth)) + val instruction_address = Input(UInt(Parameters.AddrWidth)) + val reg1_data = Input(UInt(Parameters.DataWidth)) + val reg2_data = Input(UInt(Parameters.DataWidth)) + val immediate = Input(UInt(Parameters.DataWidth)) + val aluop1_source = Input(UInt(1.W)) + val aluop2_source = Input(UInt(1.W)) + val csr_read_data = Input(UInt(Parameters.DataWidth)) + val forward_from_mem = Input(UInt(Parameters.DataWidth)) + val forward_from_wb = Input(UInt(Parameters.DataWidth)) + val reg1_forward = Input(UInt(2.W)) + val reg2_forward = Input(UInt(2.W)) + + val mem_alu_result = Output(UInt(Parameters.DataWidth)) + val csr_write_data = Output(UInt(Parameters.DataWidth)) + }) + + val opcode = io.instruction(6, 0) + val funct3 = io.instruction(14, 12) + val funct7 = io.instruction(31, 25) + val rd = io.instruction(11, 7) + val uimm = io.instruction(19, 15) + + val alu = Module(new ALU) + val alu_ctrl = Module(new ALUControl) + + alu_ctrl.io.opcode := opcode + alu_ctrl.io.funct3 := funct3 + alu_ctrl.io.funct7 := funct7 + alu.io.func := alu_ctrl.io.alu_funct + alu.io.op1 := Mux( + io.aluop1_source === ALUOp1Source.InstructionAddress, + io.instruction_address, + MuxLookup(io.reg1_forward, io.reg1_data)( + IndexedSeq( + ForwardingType.ForwardFromMEM -> io.forward_from_mem, + ForwardingType.ForwardFromWB -> io.forward_from_wb + ) + ) + ) + alu.io.op2 := Mux( + io.aluop2_source === ALUOp2Source.Immediate, + io.immediate, + MuxLookup(io.reg2_forward, io.reg2_data)( + IndexedSeq( + ForwardingType.ForwardFromMEM -> io.forward_from_mem, + ForwardingType.ForwardFromWB -> io.forward_from_wb + ) + ) + ) + io.mem_alu_result := alu.io.result + io.csr_write_data := MuxLookup(funct3, 0.U)(IndexedSeq( + InstructionsTypeCSR.csrrw -> io.reg1_data, + InstructionsTypeCSR.csrrc -> io.csr_read_data.&((~io.reg1_data).asUInt), + InstructionsTypeCSR.csrrs -> io.csr_read_data.|(io.reg1_data), + InstructionsTypeCSR.csrrwi -> Cat(0.U(27.W), uimm), + InstructionsTypeCSR.csrrci -> io.csr_read_data.&((~Cat(0.U(27.W), uimm)).asUInt), + InstructionsTypeCSR.csrrsi -> io.csr_read_data.|(Cat(0.U(27.W), uimm)), + )) +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/fivestage/Forwarding.scala b/mini-yatcpu/src/main/scala/riscv/core/fivestage/Forwarding.scala new file mode 100644 index 0000000..4f066bb --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/fivestage/Forwarding.scala @@ -0,0 +1,74 @@ +// Copyright 2022 Canbin Huang +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.fivestage + +import chisel3._ +import riscv.Parameters + +object ForwardingType { + val NoForward = 0.U(2.W) + val ForwardFromMEM = 1.U(2.W) + val ForwardFromWB = 2.U(2.W) +} + +class Forwarding extends Module { + val io = IO(new Bundle() { + val rs1_id = Input(UInt(Parameters.PhysicalRegisterAddrWidth)) + val rs2_id = Input(UInt(Parameters.PhysicalRegisterAddrWidth)) + val rs1_ex = Input(UInt(Parameters.PhysicalRegisterAddrWidth)) + val rs2_ex = Input(UInt(Parameters.PhysicalRegisterAddrWidth)) + val rd_mem = Input(UInt(Parameters.PhysicalRegisterAddrWidth)) + val reg_write_enable_mem = Input(Bool()) + val rd_wb = Input(UInt(Parameters.PhysicalRegisterAddrWidth)) + val reg_write_enable_wb = Input(Bool()) + + val reg1_forward_id = Output(UInt(2.W)) + val reg2_forward_id = Output(UInt(2.W)) + val reg1_forward_ex = Output(UInt(2.W)) + val reg2_forward_ex = Output(UInt(2.W)) + }) + + when(io.reg_write_enable_mem && io.rd_mem =/= 0.U && io.rd_mem === io.rs1_id) { + io.reg1_forward_id := ForwardingType.ForwardFromMEM + }.elsewhen(io.reg_write_enable_wb && io.rd_wb =/= 0.U && io.rd_wb === io.rs1_id) { + io.reg1_forward_id := ForwardingType.ForwardFromWB + }.otherwise { + io.reg1_forward_id := ForwardingType.NoForward + } + + when(io.reg_write_enable_mem && io.rd_mem =/= 0.U && io.rd_mem === io.rs2_id) { + io.reg2_forward_id := ForwardingType.ForwardFromMEM + }.elsewhen(io.reg_write_enable_wb && io.rd_wb =/= 0.U && io.rd_wb === io.rs2_id) { + io.reg2_forward_id := ForwardingType.ForwardFromWB + }.otherwise { + io.reg2_forward_id := ForwardingType.NoForward + } + + when(io.reg_write_enable_mem && io.rd_mem =/= 0.U && io.rd_mem === io.rs1_ex) { + io.reg1_forward_ex := ForwardingType.ForwardFromMEM + }.elsewhen(io.reg_write_enable_wb && io.rd_wb =/= 0.U && io.rd_wb === io.rs1_ex) { + io.reg1_forward_ex := ForwardingType.ForwardFromWB + }.otherwise { + io.reg1_forward_ex := ForwardingType.NoForward + } + + when(io.reg_write_enable_mem && io.rd_mem =/= 0.U && io.rd_mem === io.rs2_ex) { + io.reg2_forward_ex := ForwardingType.ForwardFromMEM + }.elsewhen(io.reg_write_enable_wb && io.rd_wb =/= 0.U && io.rd_wb === io.rs2_ex) { + io.reg2_forward_ex := ForwardingType.ForwardFromWB + }.otherwise { + io.reg2_forward_ex := ForwardingType.NoForward + } +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/fivestage/ID2EX.scala b/mini-yatcpu/src/main/scala/riscv/core/fivestage/ID2EX.scala new file mode 100644 index 0000000..8b71c01 --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/fivestage/ID2EX.scala @@ -0,0 +1,147 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.fivestage + +import chisel3._ +import riscv.Parameters + +class ID2EX extends Module { + val io = IO(new Bundle { + val stall_flag = Input(Bool()) + val flush_enable = Input(Bool()) + val instruction = Input(UInt(Parameters.InstructionWidth)) + val instruction_address = Input(UInt(Parameters.AddrWidth)) + val regs_write_enable = Input(Bool()) + val regs_write_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth)) + val regs_write_source = Input(UInt(2.W)) + val reg1_data = Input(UInt(Parameters.DataWidth)) + val reg2_data = Input(UInt(Parameters.DataWidth)) + val immediate = Input(UInt(Parameters.DataWidth)) + val aluop1_source = Input(UInt(1.W)) + val aluop2_source = Input(UInt(1.W)) + val csr_write_enable = Input(Bool()) + val csr_address = Input(UInt(Parameters.CSRRegisterAddrWidth)) + val memory_read_enable = Input(Bool()) + val memory_write_enable = Input(Bool()) + val csr_read_data = Input(UInt(Parameters.DataWidth)) + + val output_instruction = Output(UInt(Parameters.DataWidth)) + val output_instruction_address = Output(UInt(Parameters.AddrWidth)) + val output_regs_write_enable = Output(Bool()) + val output_regs_write_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth)) + val output_regs_write_source = Output(UInt(2.W)) + val output_reg1_data = Output(UInt(Parameters.DataWidth)) + val output_reg2_data = Output(UInt(Parameters.DataWidth)) + val output_immediate = Output(UInt(Parameters.DataWidth)) + val output_aluop1_source = Output(UInt(1.W)) + val output_aluop2_source = Output(UInt(1.W)) + val output_csr_write_enable = Output(Bool()) + val output_csr_address = Output(UInt(Parameters.CSRRegisterAddrWidth)) + val output_memory_read_enable = Output(Bool()) + val output_memory_write_enable = Output(Bool()) + val output_csr_read_data = Output(UInt(Parameters.DataWidth)) + }) + val write_enable = !io.stall_flag + + val instruction = Module(new PipelineRegister(defaultValue = InstructionsNop.nop)) + instruction.io.in := io.instruction + instruction.io.write_enable := write_enable + instruction.io.flush_enable := io.flush_enable + io.output_instruction := instruction.io.out + + val instruction_address = Module(new PipelineRegister(defaultValue = ProgramCounter.EntryAddress)) + instruction_address.io.in := io.instruction_address + instruction_address.io.write_enable := write_enable + instruction_address.io.flush_enable := io.flush_enable + io.output_instruction_address := instruction_address.io.out + + val regs_write_enable = Module(new PipelineRegister(1)) + regs_write_enable.io.in := io.regs_write_enable + regs_write_enable.io.write_enable := write_enable + regs_write_enable.io.flush_enable := io.flush_enable + io.output_regs_write_enable := regs_write_enable.io.out + + val regs_write_address = Module(new PipelineRegister(Parameters.PhysicalRegisterAddrBits)) + regs_write_address.io.in := io.regs_write_address + regs_write_address.io.write_enable := write_enable + regs_write_address.io.flush_enable := io.flush_enable + io.output_regs_write_address := regs_write_address.io.out + + val regs_write_source = Module(new PipelineRegister(2)) + regs_write_source.io.in := io.regs_write_source + regs_write_source.io.write_enable := write_enable + regs_write_source.io.flush_enable := io.flush_enable + io.output_regs_write_source := regs_write_source.io.out + + val reg1_data = Module(new PipelineRegister()) + reg1_data.io.in := io.reg1_data + reg1_data.io.write_enable := write_enable + reg1_data.io.flush_enable := io.flush_enable + io.output_reg1_data := reg1_data.io.out + + val reg2_data = Module(new PipelineRegister()) + reg2_data.io.in := io.reg2_data + reg2_data.io.write_enable := write_enable + reg2_data.io.flush_enable := io.flush_enable + io.output_reg2_data := reg2_data.io.out + + val immediate = Module(new PipelineRegister()) + immediate.io.in := io.immediate + immediate.io.write_enable := write_enable + immediate.io.flush_enable := io.flush_enable + io.output_immediate := immediate.io.out + + val aluop1_source = Module(new PipelineRegister(1)) + aluop1_source.io.in := io.aluop1_source + aluop1_source.io.write_enable := write_enable + aluop1_source.io.flush_enable := io.flush_enable + io.output_aluop1_source := aluop1_source.io.out + + val aluop2_source = Module(new PipelineRegister(1)) + aluop2_source.io.in := io.aluop2_source + aluop2_source.io.write_enable := write_enable + aluop2_source.io.flush_enable := io.flush_enable + io.output_aluop2_source := aluop2_source.io.out + + val csr_write_enable = Module(new PipelineRegister(1)) + csr_write_enable.io.in := io.csr_write_enable + csr_write_enable.io.write_enable := write_enable + csr_write_enable.io.flush_enable := io.flush_enable + io.output_csr_write_enable := csr_write_enable.io.out + + val csr_address = Module(new PipelineRegister(Parameters.CSRRegisterAddrBits)) + csr_address.io.in := io.csr_address + csr_address.io.write_enable := write_enable + csr_address.io.flush_enable := io.flush_enable + io.output_csr_address := csr_address.io.out + + val memory_read_enable = Module(new PipelineRegister(1)) + memory_read_enable.io.in := io.memory_read_enable + memory_read_enable.io.write_enable := write_enable + memory_read_enable.io.flush_enable := io.flush_enable + io.output_memory_read_enable := memory_read_enable.io.out + + val memory_write_enable = Module(new PipelineRegister(1)) + memory_write_enable.io.in := io.memory_write_enable + memory_write_enable.io.write_enable := write_enable + memory_write_enable.io.flush_enable := io.flush_enable + io.output_memory_write_enable := memory_write_enable.io.out + + val csr_read_data = Module(new PipelineRegister()) + csr_read_data.io.in := io.csr_read_data + csr_read_data.io.write_enable := write_enable + csr_read_data.io.flush_enable := io.flush_enable + io.output_csr_read_data := csr_read_data.io.out +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/fivestage/IF2ID.scala b/mini-yatcpu/src/main/scala/riscv/core/fivestage/IF2ID.scala new file mode 100644 index 0000000..0413654 --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/fivestage/IF2ID.scala @@ -0,0 +1,52 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.fivestage + +import chisel3._ +import riscv.Parameters + +class IF2ID extends Module { + val io = IO(new Bundle { + val stall_flag = Input(Bool()) + val flush_enable = Input(Bool()) + val instruction = Input(UInt(Parameters.InstructionWidth)) + val instruction_address = Input(UInt(Parameters.AddrWidth)) + val interrupt_flag = Input(UInt(Parameters.InterruptFlagWidth)) + + val output_instruction = Output(UInt(Parameters.DataWidth)) + val output_instruction_address = Output(UInt(Parameters.AddrWidth)) + val output_interrupt_flag = Output(UInt(Parameters.InterruptFlagWidth)) + }) + + val write_enable = !io.stall_flag + + val instruction = Module(new PipelineRegister(defaultValue = InstructionsNop.nop)) + instruction.io.in := io.instruction + instruction.io.write_enable := write_enable + instruction.io.flush_enable := io.flush_enable + io.output_instruction := instruction.io.out + + val instruction_address = Module(new PipelineRegister(defaultValue = ProgramCounter.EntryAddress)) + instruction_address.io.in := io.instruction_address + instruction_address.io.write_enable := write_enable + instruction_address.io.flush_enable := io.flush_enable + io.output_instruction_address := instruction_address.io.out + + val interrupt_flag = Module(new PipelineRegister(Parameters.InterruptFlagBits)) + interrupt_flag.io.in := io.interrupt_flag + interrupt_flag.io.write_enable := write_enable + interrupt_flag.io.flush_enable := io.flush_enable + io.output_interrupt_flag := interrupt_flag.io.out +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/fivestage/InstructionDecode.scala b/mini-yatcpu/src/main/scala/riscv/core/fivestage/InstructionDecode.scala new file mode 100644 index 0000000..60657bf --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/fivestage/InstructionDecode.scala @@ -0,0 +1,258 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.fivestage + +import chisel3._ +import chisel3.util._ +import riscv.Parameters + +object InstructionTypes { + val L = "b0000011".U + val I = "b0010011".U + val S = "b0100011".U + val RM = "b0110011".U + val B = "b1100011".U +} + +object Instructions { + val lui = "b0110111".U + val nop = "b0000001".U + val jal = "b1101111".U + val jalr = "b1100111".U + val auipc = "b0010111".U + val csr = "b1110011".U + val fence = "b0001111".U +} + +object InstructionsTypeL { + val lb = "b000".U + val lh = "b001".U + val lw = "b010".U + val lbu = "b100".U + val lhu = "b101".U +} + +object InstructionsTypeI { + val addi = 0.U + val slli = 1.U + val slti = 2.U + val sltiu = 3.U + val xori = 4.U + val sri = 5.U + val ori = 6.U + val andi = 7.U +} + +object InstructionsTypeS { + val sb = "b000".U + val sh = "b001".U + val sw = "b010".U +} + +object InstructionsTypeR { + val add_sub = 0.U + val sll = 1.U + val slt = 2.U + val sltu = 3.U + val xor = 4.U + val sr = 5.U + val or = 6.U + val and = 7.U +} + +object InstructionsTypeM { + val mul = 0.U + val mulh = 1.U + val mulhsu = 2.U + val mulhum = 3.U + val div = 4.U + val divu = 5.U + val rem = 6.U + val remu = 7.U +} + +object InstructionsTypeB { + val beq = "b000".U + val bne = "b001".U + val blt = "b100".U + val bge = "b101".U + val bltu = "b110".U + val bgeu = "b111".U +} + +object InstructionsTypeCSR { + val csrrw = "b001".U + val csrrs = "b010".U + val csrrc = "b011".U + val csrrwi = "b101".U + val csrrsi = "b110".U + val csrrci = "b111".U +} + +object InstructionsNop { + val nop = 0x00000013L.U(Parameters.DataWidth) +} + +object InstructionsRet { + val mret = 0x30200073L.U(Parameters.DataWidth) + val ret = 0x00008067L.U(Parameters.DataWidth) +} + +object InstructionsEnv { + val ecall = 0x00000073L.U(Parameters.DataWidth) + val ebreak = 0x00100073L.U(Parameters.DataWidth) +} + +object ALUOp1Source { + val Register = 0.U(1.W) + val InstructionAddress = 1.U(1.W) +} + +object ALUOp2Source { + val Register = 0.U(1.W) + val Immediate = 1.U(1.W) +} + +object RegWriteSource { + val ALUResult = 0.U(2.W) + val Memory = 1.U(2.W) + val CSR = 2.U(2.W) + val NextInstructionAddress = 3.U(2.W) +} + +class InstructionDecode extends Module { + val io = IO(new Bundle { + val instruction = Input(UInt(Parameters.InstructionWidth)) + val instruction_address = Input(UInt(Parameters.AddrWidth)) + val reg1_data = Input(UInt(Parameters.DataWidth)) + val reg2_data = Input(UInt(Parameters.DataWidth)) + val forward_from_mem = Input(UInt(Parameters.DataWidth)) + val forward_from_wb = Input(UInt(Parameters.DataWidth)) + val reg1_forward = Input(UInt(2.W)) + val reg2_forward = Input(UInt(2.W)) + val interrupt_assert = Input(Bool()) + val interrupt_handler_address = Input(UInt(Parameters.AddrWidth)) + + val regs_reg1_read_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth)) + val regs_reg2_read_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth)) + val ex_reg1_data = Output(UInt(Parameters.DataWidth)) + val ex_reg2_data = Output(UInt(Parameters.DataWidth)) + val ex_immediate = Output(UInt(Parameters.DataWidth)) + val ex_aluop1_source = Output(UInt(1.W)) + val ex_aluop2_source = Output(UInt(1.W)) + val ex_memory_read_enable = Output(Bool()) + val ex_memory_write_enable = Output(Bool()) + val ex_reg_write_source = Output(UInt(2.W)) + val ex_reg_write_enable = Output(Bool()) + val ex_reg_write_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth)) + val ex_csr_address = Output(UInt(Parameters.CSRRegisterAddrWidth)) + val ex_csr_write_enable = Output(Bool()) + val ctrl_jump_instruction = Output(Bool()) + val clint_jump_flag = Output(Bool()) + val clint_jump_address = Output(UInt(Parameters.AddrWidth)) + val if_jump_flag = Output(Bool()) + val if_jump_address = Output(UInt(Parameters.AddrWidth)) + }) + val opcode = io.instruction(6, 0) + val funct3 = io.instruction(14, 12) + val funct7 = io.instruction(31, 25) + val rd = io.instruction(11, 7) + val rs1 = io.instruction(19, 15) + val rs2 = io.instruction(24, 20) + + io.regs_reg1_read_address := Mux(opcode === Instructions.lui, 0.U(Parameters.PhysicalRegisterAddrWidth), rs1) + io.regs_reg2_read_address := rs2 + io.ex_reg1_data := io.reg1_data + io.ex_reg2_data := io.reg2_data + io.ex_immediate := MuxLookup(opcode, Cat(Fill(20, io.instruction(31)), io.instruction(31, 20)))( + IndexedSeq( + InstructionTypes.I -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 20)), + InstructionTypes.L -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 20)), + Instructions.jalr -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 20)), + InstructionTypes.S -> Cat(Fill(21, io.instruction(31)), io.instruction(30, 25), io.instruction(11, 7)), + InstructionTypes.B -> Cat(Fill(20, io.instruction(31)), io.instruction(7), io.instruction(30, 25), io + .instruction(11, 8), 0.U(1.W)), + Instructions.lui -> Cat(io.instruction(31, 12), 0.U(12.W)), + Instructions.auipc -> Cat(io.instruction(31, 12), 0.U(12.W)), + Instructions.jal -> Cat(Fill(12, io.instruction(31)), io.instruction(19, 12), io.instruction(20), io + .instruction(30, 21), 0.U(1.W)) + ) + ) + io.ex_aluop1_source := Mux( + opcode === Instructions.auipc || opcode === InstructionTypes.B || opcode === Instructions.jal, + ALUOp1Source.InstructionAddress, + ALUOp1Source.Register + ) + io.ex_aluop2_source := Mux( + opcode === InstructionTypes.RM, + ALUOp2Source.Register, + ALUOp2Source.Immediate + ) + io.ex_memory_read_enable := opcode === InstructionTypes.L + io.ex_memory_write_enable := opcode === InstructionTypes.S + io.ex_reg_write_source := MuxLookup(opcode, RegWriteSource.ALUResult)( + IndexedSeq( + InstructionTypes.L -> RegWriteSource.Memory, + Instructions.csr -> RegWriteSource.CSR, + Instructions.jal -> RegWriteSource.NextInstructionAddress, + Instructions.jalr -> RegWriteSource.NextInstructionAddress + ) + ) + io.ex_reg_write_enable := (opcode === InstructionTypes.RM) || (opcode === InstructionTypes.I) || + (opcode === InstructionTypes.L) || (opcode === Instructions.auipc) || (opcode === Instructions.lui) || + (opcode === Instructions.jal) || (opcode === Instructions.jalr) || (opcode === Instructions.csr) + io.ex_reg_write_address := io.instruction(11, 7) + io.ex_csr_address := io.instruction(31, 20) + io.ex_csr_write_enable := (opcode === Instructions.csr) && ( + funct3 === InstructionsTypeCSR.csrrw || funct3 === InstructionsTypeCSR.csrrwi || + funct3 === InstructionsTypeCSR.csrrs || funct3 === InstructionsTypeCSR.csrrsi || + funct3 === InstructionsTypeCSR.csrrc || funct3 === InstructionsTypeCSR.csrrci + ) + + val reg1_data = MuxLookup(io.reg1_forward, io.reg1_data)( + IndexedSeq( + ForwardingType.ForwardFromMEM -> io.forward_from_mem, + ForwardingType.ForwardFromWB -> io.forward_from_wb + ) + ) + val reg2_data = MuxLookup(io.reg2_forward, io.reg2_data)( + IndexedSeq( + ForwardingType.ForwardFromMEM -> io.forward_from_mem, + ForwardingType.ForwardFromWB -> io.forward_from_wb + ) + ) + io.ctrl_jump_instruction := (opcode === Instructions.jal) || + (opcode === Instructions.jalr) || (opcode === InstructionTypes.B) + val instruction_jump_flag = (opcode === Instructions.jal) || + (opcode === Instructions.jalr) || + (opcode === InstructionTypes.B) && MuxLookup(funct3, false.B)( + IndexedSeq( + InstructionsTypeB.beq -> (reg1_data === reg2_data), + InstructionsTypeB.bne -> (reg1_data =/= reg2_data), + InstructionsTypeB.blt -> (reg1_data.asSInt < reg2_data.asSInt), + InstructionsTypeB.bge -> (reg1_data.asSInt >= reg2_data.asSInt), + InstructionsTypeB.bltu -> (reg1_data.asUInt < reg2_data.asUInt), + InstructionsTypeB.bgeu -> (reg1_data.asUInt >= reg2_data.asUInt) + ) + ) + val instruction_jump_address = io.ex_immediate + Mux(opcode === Instructions.jalr, reg1_data, io.instruction_address) + io.clint_jump_flag := instruction_jump_flag + io.clint_jump_address := instruction_jump_address + io.if_jump_flag := io.interrupt_assert || instruction_jump_flag + io.if_jump_address := Mux(io.interrupt_assert, + io.interrupt_handler_address, + instruction_jump_address + ) +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/fivestage/InstructionFetch.scala b/mini-yatcpu/src/main/scala/riscv/core/fivestage/InstructionFetch.scala new file mode 100644 index 0000000..bb0e590 --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/fivestage/InstructionFetch.scala @@ -0,0 +1,104 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.fivestage + +import chisel3._ +import chisel3.util.MuxCase +import riscv.Parameters +import riscv.core.BusBundle + +object ProgramCounter { + val EntryAddress = Parameters.EntryAddress +} + +object IFAccessStates extends ChiselEnum { + val idle, read = Value +} + +class InstructionFetch extends Module { + val io = IO(new Bundle { + val stall_flag_ctrl = Input(Bool()) + val jump_flag_id = Input(Bool()) + val jump_address_id = Input(UInt(Parameters.AddrWidth)) + + val physical_address = Input(UInt(Parameters.AddrWidth)) + + val ctrl_stall_flag = Output(Bool()) + val id_instruction_address = Output(UInt(Parameters.AddrWidth)) + val id_instruction = Output(UInt(Parameters.InstructionWidth)) + val pc_valid = Output(Bool()) + + val bus = new BusBundle + }) + val pending_jump = RegInit(false.B) + val pc = RegInit(ProgramCounter.EntryAddress) + val state = RegInit(IFAccessStates.idle) + val pc_valid = RegInit(false.B) //because the romloader of verilator(sim_main.cpp) need no time cycle + //it prevent fetching instruction from 0x0, when pc haven't been initailized + + io.bus.read := false.B + io.bus.request := true.B + io.bus.write := false.B + io.bus.write_data := 0.U + io.bus.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B)) + io.pc_valid := pc_valid + + when(!pc_valid && pc === ProgramCounter.EntryAddress) { + pc_valid := true.B + } + + pc := MuxCase( + pc + 4.U, + IndexedSeq( + io.jump_flag_id -> io.jump_address_id, + io.stall_flag_ctrl -> pc + ) + ) + + when(!io.bus.read_valid) { + when(io.jump_flag_id) { + pending_jump := true.B + } + } + + when(io.bus.read_valid) { + when(pending_jump) { + pending_jump := false.B + } + } + + when(io.bus.granted) { + when(state === IFAccessStates.idle) { + io.bus.request := true.B + io.bus.read := true.B + state := IFAccessStates.read + }.elsewhen(state === IFAccessStates.read) { + io.bus.read := false.B + io.bus.request := true.B + when(io.bus.read_valid) { + state := IFAccessStates.idle + } + } + } + + io.id_instruction := Mux( + io.bus.read_valid && !pending_jump && !io.jump_flag_id, + io.bus.read_data, + InstructionsNop.nop + ) + io.ctrl_stall_flag := !io.bus.read_valid || pending_jump + io.id_instruction_address := pc + io.bus.address := io.physical_address +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/fivestage/MEM2WB.scala b/mini-yatcpu/src/main/scala/riscv/core/fivestage/MEM2WB.scala new file mode 100644 index 0000000..eba0938 --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/fivestage/MEM2WB.scala @@ -0,0 +1,82 @@ +// Copyright 2022 Canbin Huang +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.fivestage + +import chisel3._ +import riscv.Parameters + +class MEM2WB extends Module { + val io = IO(new Bundle() { + val instruction_address = Input(UInt(Parameters.AddrWidth)) + val alu_result = Input(UInt(Parameters.DataWidth)) + val regs_write_enable = Input(Bool()) + val regs_write_source = Input(UInt(2.W)) + val regs_write_address = Input(UInt(Parameters.AddrWidth)) + val memory_read_data = Input(UInt(Parameters.DataWidth)) + val csr_read_data = Input(UInt(Parameters.DataWidth)) + + val output_instruction_address = Output(UInt(Parameters.AddrWidth)) + val output_alu_result = Output(UInt(Parameters.DataWidth)) + val output_regs_write_enable = Output(Bool()) + val output_regs_write_source = Output(UInt(2.W)) + val output_regs_write_address = Output(UInt(Parameters.AddrWidth)) + val output_memory_read_data = Output(UInt(Parameters.DataWidth)) + val output_csr_read_data = Output(UInt(Parameters.DataWidth)) + }) + val flush_enable = false.B + val write_enable = true.B + + val alu_result = Module(new PipelineRegister()) + alu_result.io.in := io.alu_result + alu_result.io.write_enable := write_enable + alu_result.io.flush_enable := flush_enable + io.output_alu_result := alu_result.io.out + + val memory_read_data = Module(new PipelineRegister()) + memory_read_data.io.in := io.memory_read_data + memory_read_data.io.write_enable := write_enable + memory_read_data.io.flush_enable := flush_enable + io.output_memory_read_data := memory_read_data.io.out + + val regs_write_enable = Module(new PipelineRegister(1)) + regs_write_enable.io.in := io.regs_write_enable + regs_write_enable.io.write_enable := write_enable + regs_write_enable.io.flush_enable := flush_enable + io.output_regs_write_enable := regs_write_enable.io.out + + val regs_write_source = Module(new PipelineRegister(2)) + regs_write_source.io.in := io.regs_write_source + regs_write_source.io.write_enable := write_enable + regs_write_source.io.flush_enable := flush_enable + io.output_regs_write_source := regs_write_source.io.out + + val regs_write_address = Module(new PipelineRegister(Parameters.PhysicalRegisterAddrBits)) + regs_write_address.io.in := io.regs_write_address + regs_write_address.io.write_enable := write_enable + regs_write_address.io.flush_enable := flush_enable + io.output_regs_write_address := regs_write_address.io.out + + val instruction_address = Module(new PipelineRegister(Parameters.InstructionBits)) + instruction_address.io.in := io.instruction_address + instruction_address.io.write_enable := write_enable + instruction_address.io.flush_enable := flush_enable + io.output_instruction_address := instruction_address.io.out + + val csr_read_data = Module(new PipelineRegister()) + csr_read_data.io.in := io.csr_read_data + csr_read_data.io.write_enable := write_enable + csr_read_data.io.flush_enable := flush_enable + io.output_csr_read_data := csr_read_data.io.out +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/fivestage/MMU.scala b/mini-yatcpu/src/main/scala/riscv/core/fivestage/MMU.scala new file mode 100644 index 0000000..e817981 --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/fivestage/MMU.scala @@ -0,0 +1,198 @@ +package riscv.core.fivestage + +import chisel3.util._ +import chisel3.{when, _} +import riscv.Parameters +import riscv.core.BusBundle + + +object MMUStates extends ChiselEnum { + val idle, level1, checkpte1, level0, checkpte0, setADbit, gotPhyicalAddress = Value +} + +class MMU extends Module { + val io = IO(new Bundle() { + val instructions = Input(UInt(Parameters.InstructionWidth)) + val instructions_address = Input(UInt(Parameters.AddrWidth)) + + //from satp + val ppn_from_satp = Input(UInt(20.W)) + + val virtual_address = Input(UInt(Parameters.AddrWidth)) + val mmu_occupied_by_mem = Input(Bool()) + val restart = Input(Bool()) + val restart_done = Output(Bool()) + + val pa_valid = Output(Bool()) + val pa = Output(UInt(Parameters.AddrWidth)) + + val page_fault_signals = Output(Bool()) + val va_cause_page_fault = Output(UInt(Parameters.AddrWidth)) + val ecause = Output(UInt(Parameters.DataWidth)) + val epc = Output(UInt(Parameters.AddrWidth)) + val page_fault_responed = Input(Bool()) + + val bus = new BusBundle() + }) + val opcode = io.instructions(6, 0) + + val state = RegInit(MMUStates.idle) + + val pa = RegInit(UInt(Parameters.AddrWidth), 0.U) + val va = io.virtual_address + val vpn1 = va(31, 22) + + val vpn0 = va(21, 12) + val pageoffset = va(11, 0) + + val pte1 = Reg(UInt(Parameters.PTEWidth)) + val pte0 = Reg(UInt(Parameters.PTEWidth)) + //add a reg to avoid Combination loop + val page_fault_signals = RegInit(false.B) + + def raise_page_fault(): Unit = { + io.ecause := Mux( + io.mmu_occupied_by_mem, + MuxLookup(io.instructions, 10.U)( + IndexedSeq( + InstructionTypes.S -> 15.U, + InstructionTypes.L -> 13.U, + ) + ), + 12.U // Instruction page fault + ) + io.va_cause_page_fault := va //for mtval + page_fault_signals := true.B + io.epc := Mux( //info stored before the exception handler, will start again from this pc + io.mmu_occupied_by_mem, + io.instructions_address, //mem_access + va, //IF + ) + when(io.page_fault_responed) { + page_fault_signals := false.B + state := MMUStates.idle + } + } + + io.pa_valid := false.B + io.bus.request := false.B + io.bus.read := false.B + io.bus.address := 0.U + io.bus.write_data := 0.U + io.bus.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B)) + io.bus.write := false.B + io.page_fault_signals := page_fault_signals + + io.ecause := 0.U + io.pa := 0.U + io.restart_done := false.B + io.va_cause_page_fault := 0.U + io.epc := 0.U + + //MMU FSM + //our physical address bits is 32 + when(io.bus.granted) { + when(state === MMUStates.idle) { + //read pte from mem when the bus is free and someone needs the translation + //mem request take precedence of IF + io.pa_valid := false.B + io.bus.read := true.B + io.restart_done := false.B + io.bus.address := ((io.ppn_from_satp << Parameters.PageOffsetBits.U).asUInt & (vpn1 << 2).asUInt) //address of + // level 1 pte + state := MMUStates.level1 + }.elsewhen(state === MMUStates.level1) { //don't support the huge page + //already access the bus,wait for the pte + io.bus.read := false.B + when(io.bus.read_valid) { + pte1 := io.bus.read_data + when(io.restart) { + io.restart_done := true.B + state := MMUStates.idle + }.otherwise { + state := MMUStates.checkpte1 + } + } + }.elsewhen(state === MMUStates.checkpte1) { + //todo: hrpccs :no PMA or PMP check + when(io.restart) { + io.restart_done := true.B + state := MMUStates.idle + }.elsewhen(pte1(0) === 0.U || (pte1(2, 1) === "b10".U) || (pte1(9, 8) =/= "b00".U)) { + //raise a page-fault exception corresponding to the original access type + raise_page_fault() + }.otherwise { + io.bus.read := true.B + io.bus.address := ((pte1(29, 10) << Parameters.PageOffsetBits.U).asUInt & (vpn0 << 2).asUInt) //address of + // level 0 pte + when(io.bus.granted) { + state := MMUStates.level0 + } + } + }.elsewhen(state === MMUStates.level0) { + io.bus.read := false.B + when(io.bus.read_valid) { + pte0 := io.bus.read_data + when(io.restart) { + io.restart_done := true.B + state := MMUStates.idle + }.otherwise { + state := MMUStates.checkpte0 + } + } + }.elsewhen(state === MMUStates.checkpte0) { + when(io.restart) { + io.restart_done := true.B + state := MMUStates.idle + }.elsewhen(pte0(0) === 0.U || (pte0(2, 1) === "b10".U) || (pte0(9, 8) =/= "b00".U) || (pte0(3, 1) === "b000".U)) { + //raise a page-fault exception corresponding to the original access type + raise_page_fault() + }.elsewhen(pte0(1) === 1.U || pte0(3) === 1.U) { + //we found a leaf pte + val instructionInvalid = io.mmu_occupied_by_mem === false.B && pte0(3) === 0.U + val storeInvalid = io.instructions(6, 0) === InstructionTypes.S && pte0(2) === 0.U + val loadInvalid = io.instructions(6, 0) === InstructionTypes.L && pte0(1) === 0.U + when(instructionInvalid || storeInvalid || loadInvalid) { + //todo:hrpccs :when the privillege switch is done,please add the privillege check + raise_page_fault() + }.elsewhen(pte0(6) === 0.U || (pte0(7) === 0.U && io.instructions(6, 0) === InstructionTypes.S)) { + //set the access bit and the dirty bit if the instruction is store type + //as we currently support single core CPU,so we can ignore the concurrent pte change + //todo:hrpccs :when someone want to have a multicore support \ + // please modify this part acording to riscv-privilege + val setAbit = io.instructions(6, 0) === InstructionTypes.S + io.bus.write_data := Cat(pte0(31, 8), setAbit, 1.U(1.W), pte0(5, 0)) + io.bus.write := true.B + io.bus.address := ((pte1(29, 10) << Parameters.PageOffsetBits.U).asUInt + (vpn0 << 2).asUInt) + for (i <- 0 until Parameters.WordSize) { + io.bus.write_strobe(i) := true.B + } + state := MMUStates.setADbit + }.otherwise { + state := MMUStates.gotPhyicalAddress + } + } + }.elsewhen(state === MMUStates.setADbit) { + io.bus.write := false.B + when(io.bus.write_valid) { + when(io.restart) { + io.restart_done := true.B + state := MMUStates.idle + }.otherwise { + state := MMUStates.gotPhyicalAddress + } + } + }.elsewhen(state === MMUStates.gotPhyicalAddress) { + when(io.restart) { + io.restart_done := true.B + state := MMUStates.idle + }.otherwise { + io.pa := Cat(pte0(29, 10), pageoffset) + io.pa_valid := true.B + state := MMUStates.idle + } + } + } + + +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/fivestage/MemoryAccess.scala b/mini-yatcpu/src/main/scala/riscv/core/fivestage/MemoryAccess.scala new file mode 100644 index 0000000..9dd0f8e --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/fivestage/MemoryAccess.scala @@ -0,0 +1,154 @@ +// Copyright 2022 Canbin Huang +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.fivestage + +import chisel3._ +import chisel3.util._ +import riscv.Parameters +import riscv.core.BusBundle + +class MemoryAccess extends Module { + val io = IO(new Bundle() { + val alu_result = Input(UInt(Parameters.DataWidth)) + val reg2_data = Input(UInt(Parameters.DataWidth)) + val memory_read_enable = Input(Bool()) + val memory_write_enable = Input(Bool()) + val funct3 = Input(UInt(3.W)) + val regs_write_source = Input(UInt(2.W)) + val csr_read_data = Input(UInt(Parameters.DataWidth)) + val clint_exception_token = Input(Bool()) + + val wb_memory_read_data = Output(UInt(Parameters.DataWidth)) + val ctrl_stall_flag = Output(Bool()) + val forward_data = Output(UInt(Parameters.DataWidth)) + + val physical_address = Input(UInt(Parameters.AddrWidth)) + + val bus = new BusBundle + }) + val mem_address_index = io.physical_address(log2Up(Parameters.WordSize) - 1, 0) + val mem_access_state = RegInit(MemoryAccessStates.Idle) + + def on_bus_transaction_finished() = { + mem_access_state := MemoryAccessStates.Idle + io.ctrl_stall_flag := false.B + } + + io.bus.request := false.B + io.bus.read := false.B + io.bus.address := io.physical_address + io.bus.write_data := 0.U + io.bus.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B)) + io.bus.write := false.B + io.wb_memory_read_data := 0.U + io.ctrl_stall_flag := false.B + + when(io.clint_exception_token) { + io.bus.request := false.B + io.ctrl_stall_flag := false.B + }.elsewhen(io.memory_read_enable) { + when(mem_access_state === MemoryAccessStates.Idle) { + // Start the read transaction when the bus is available + io.ctrl_stall_flag := true.B + io.bus.read := true.B + io.bus.request := true.B + when(io.bus.granted) { + io.bus.address := io.physical_address + io.bus.read := true.B + mem_access_state := MemoryAccessStates.Read + } + }.elsewhen(mem_access_state === MemoryAccessStates.Read) { + io.bus.request := true.B + io.bus.read := false.B + io.ctrl_stall_flag := true.B + when(io.bus.read_valid) { + val data = io.bus.read_data + io.wb_memory_read_data := MuxLookup(io.funct3, 0.U)( + IndexedSeq( + InstructionsTypeL.lb -> MuxLookup(mem_address_index, Cat(Fill(24, data(31)), data(31, 24)))( + IndexedSeq( + 0.U -> Cat(Fill(24, data(7)), data(7, 0)), + 1.U -> Cat(Fill(24, data(15)), data(15, 8)), + 2.U -> Cat(Fill(24, data(23)), data(23, 16)) + ) + ), + InstructionsTypeL.lbu -> MuxLookup(mem_address_index, Cat(Fill(24, 0.U), data(31, 24)))( + IndexedSeq( + 0.U -> Cat(Fill(24, 0.U), data(7, 0)), + 1.U -> Cat(Fill(24, 0.U), data(15, 8)), + 2.U -> Cat(Fill(24, 0.U), data(23, 16)) + ) + ), + InstructionsTypeL.lh -> Mux( + mem_address_index === 0.U, + Cat(Fill(16, data(15)), data(15, 0)), + Cat(Fill(16, data(31)), data(31, 16)) + ), + InstructionsTypeL.lhu -> Mux( + mem_address_index === 0.U, + Cat(Fill(16, 0.U), data(15, 0)), + Cat(Fill(16, 0.U), data(31, 16)) + ), + InstructionsTypeL.lw -> data + ) + ) + on_bus_transaction_finished() + } + } + }.elsewhen(io.memory_write_enable) { + when(mem_access_state === MemoryAccessStates.Idle) { + // Start the write transaction when there the bus is available + io.ctrl_stall_flag := true.B + io.bus.write_data := io.reg2_data + io.bus.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B)) + when(io.funct3 === InstructionsTypeS.sb) { + io.bus.write_strobe(mem_address_index) := true.B + io.bus.write_data := io.reg2_data(Parameters.ByteBits, 0) << (mem_address_index << log2Up(Parameters + .ByteBits).U) + }.elsewhen(io.funct3 === InstructionsTypeS.sh) { + when(mem_address_index === 0.U) { + for (i <- 0 until Parameters.WordSize / 2) { + io.bus.write_strobe(i) := true.B + } + io.bus.write_data := io.reg2_data(Parameters.WordSize / 2 * Parameters.ByteBits, 0) + }.otherwise { + for (i <- Parameters.WordSize / 2 until Parameters.WordSize) { + io.bus.write_strobe(i) := true.B + } + io.bus.write_data := io.reg2_data(Parameters.WordSize / 2 * Parameters.ByteBits, 0) << (Parameters + .WordSize / 2 * Parameters.ByteBits) + } + }.elsewhen(io.funct3 === InstructionsTypeS.sw) { + for (i <- 0 until Parameters.WordSize) { + io.bus.write_strobe(i) := true.B + } + } + io.bus.request := true.B + when(io.bus.granted) { + io.bus.write := true.B + mem_access_state := MemoryAccessStates.Write + } + }.elsewhen(mem_access_state === MemoryAccessStates.Write) { + io.bus.request := true.B + io.ctrl_stall_flag := true.B + io.bus.write := false.B + when(io.bus.write_valid) { + on_bus_transaction_finished() + } + } + } + + io.forward_data := Mux(io.regs_write_source === RegWriteSource.CSR, io.csr_read_data, io.alu_result) +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/fivestage/PipelineRegister.scala b/mini-yatcpu/src/main/scala/riscv/core/fivestage/PipelineRegister.scala new file mode 100644 index 0000000..2dd5142 --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/fivestage/PipelineRegister.scala @@ -0,0 +1,35 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.fivestage + +import chisel3._ +import riscv.Parameters + +class PipelineRegister(width: Int = Parameters.DataBits, defaultValue: UInt = 0.U) extends Module { + val io = IO(new Bundle { + val write_enable = Input(Bool()) + val flush_enable = Input(Bool()) + val in = Input(UInt(width.W)) + val out = Output(UInt(width.W)) + }) + + val reg = RegInit(UInt(width.W), defaultValue) + when(io.write_enable) { + reg := io.in + }.elsewhen(io.flush_enable) { + reg := defaultValue + } + io.out := reg +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/fivestage/RegisterFile.scala b/mini-yatcpu/src/main/scala/riscv/core/fivestage/RegisterFile.scala new file mode 100644 index 0000000..e21d395 --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/fivestage/RegisterFile.scala @@ -0,0 +1,78 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.fivestage + +import chisel3._ +import chisel3.util._ +import riscv.Parameters + +object Registers extends Enumeration { + type Register = Value + val zero, + ra, sp, gp, tp, + t0, t1, t2, fp, + s1, + a0, a1, a2, a3, a4, a5, a6, a7, + s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, + t3, t4, t5, t6 = Value +} + +class RegisterFile extends Module { + val io = IO(new Bundle { + val write_enable = Input(Bool()) + val write_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth)) + val write_data = Input(UInt(Parameters.DataWidth)) + + val read_address1 = Input(UInt(Parameters.PhysicalRegisterAddrWidth)) + val read_address2 = Input(UInt(Parameters.PhysicalRegisterAddrWidth)) + val read_data1 = Output(UInt(Parameters.DataWidth)) + val read_data2 = Output(UInt(Parameters.DataWidth)) + + val debug_read_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth)) + val debug_read_data = Output(UInt(Parameters.DataWidth)) + }) + val registers = Reg(Vec(Parameters.PhysicalRegisters, UInt(Parameters.DataWidth))) + + when(!reset.asBool) { + when(io.write_enable && io.write_address =/= 0.U) { + registers(io.write_address) := io.write_data + } + } + + io.read_data1 := MuxCase( + registers(io.read_address1), + IndexedSeq( + (io.read_address1 === 0.U) -> 0.U, + (io.read_address1 === io.write_address && io.write_enable) -> io.write_data + ) + ) + + io.read_data2 := MuxCase( + registers(io.read_address2), + IndexedSeq( + (io.read_address2 === 0.U) -> 0.U, + (io.read_address2 === io.write_address && io.write_enable) -> io.write_data + ) + ) + + io.debug_read_data := MuxCase( + registers(io.debug_read_address), + IndexedSeq( + (io.debug_read_address === 0.U) -> 0.U, + (io.debug_read_address === io.write_address && io.write_enable) -> io.write_data + ) + ) + +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/fivestage/WriteBack.scala b/mini-yatcpu/src/main/scala/riscv/core/fivestage/WriteBack.scala new file mode 100644 index 0000000..5bf25fb --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/fivestage/WriteBack.scala @@ -0,0 +1,38 @@ +// Copyright 2022 Canbin Huang +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.fivestage + +import chisel3._ +import chisel3.util._ +import riscv.Parameters + +class WriteBack extends Module { + val io = IO(new Bundle() { + val instruction_address = Input(UInt(Parameters.AddrWidth)) + val alu_result = Input(UInt(Parameters.DataWidth)) + val memory_read_data = Input(UInt(Parameters.DataWidth)) + val regs_write_source = Input(UInt(2.W)) + val csr_read_data = Input(UInt(Parameters.DataWidth)) + + val regs_write_data = Output(UInt(Parameters.DataWidth)) + }) + io.regs_write_data := MuxLookup(io.regs_write_source, io.alu_result)( + IndexedSeq( + RegWriteSource.Memory -> io.memory_read_data, + RegWriteSource.CSR -> io.csr_read_data, + RegWriteSource.NextInstructionAddress -> (io.instruction_address + 4.U) + ) + ) +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/threestage/ALU.scala b/mini-yatcpu/src/main/scala/riscv/core/threestage/ALU.scala new file mode 100644 index 0000000..ffecc74 --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/threestage/ALU.scala @@ -0,0 +1,66 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.threestage + +import chisel3._ +import chisel3.util._ +import riscv.Parameters + +object ALUFunctions extends ChiselEnum { + val zero, add, sub, sll, slt, xor, or, and, sr, sltu = Value +} + +class ALU extends Module { + val io = IO(new Bundle { + val func = Input(ALUFunctions()) + + val op1 = Input(UInt(Parameters.DataWidth)) + val op2 = Input(UInt(Parameters.DataWidth)) + + val result = Output(UInt(Parameters.DataWidth)) + }) + + io.result := 0.U + switch(io.func) { + is(ALUFunctions.add) { + io.result := io.op1 + io.op2 + } + is(ALUFunctions.sub) { + io.result := io.op1 - io.op2 + } + is(ALUFunctions.sll) { + io.result := io.op1 << io.op2(4, 0) + } + is(ALUFunctions.slt) { + io.result := io.op1.asSInt < io.op2.asSInt + } + is(ALUFunctions.xor) { + io.result := io.op1 ^ io.op2 + } + is(ALUFunctions.or) { + io.result := io.op1 | io.op2 + } + is(ALUFunctions.and) { + io.result := io.op1 & io.op2 + } + is(ALUFunctions.sr) { + io.result := io.op1 >> io.op2(4, 0) + } + is(ALUFunctions.sltu) { + io.result := io.op1 < io.op2 + } + } + +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/threestage/ALUControl.scala b/mini-yatcpu/src/main/scala/riscv/core/threestage/ALUControl.scala new file mode 100644 index 0000000..f763f41 --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/threestage/ALUControl.scala @@ -0,0 +1,73 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.threestage + +import chisel3._ +import chisel3.util._ + +class ALUControl extends Module { + val io = IO(new Bundle { + val opcode = Input(UInt(7.W)) + val funct3 = Input(UInt(3.W)) + val funct7 = Input(UInt(7.W)) + + val alu_funct = Output(ALUFunctions()) + }) + + io.alu_funct := ALUFunctions.zero + + switch(io.opcode) { + is(InstructionTypes.I) { + io.alu_funct := MuxLookup(io.funct3, ALUFunctions.zero)( + IndexedSeq( + InstructionsTypeI.addi -> ALUFunctions.add, + InstructionsTypeI.slli -> ALUFunctions.sll, + InstructionsTypeI.slti -> ALUFunctions.slt, + InstructionsTypeI.sltiu -> ALUFunctions.sltu, + InstructionsTypeI.xori -> ALUFunctions.xor, + InstructionsTypeI.ori -> ALUFunctions.or, + InstructionsTypeI.andi -> ALUFunctions.and, + InstructionsTypeI.sri -> ALUFunctions.sr, + ), + ) + } + is(InstructionTypes.RM) { + io.alu_funct := MuxLookup(io.funct3, ALUFunctions.zero)( + IndexedSeq( + InstructionsTypeR.add_sub -> Mux(io.funct7(5), ALUFunctions.sub, ALUFunctions.add), + InstructionsTypeR.sll -> ALUFunctions.sll, + InstructionsTypeR.slt -> ALUFunctions.slt, + InstructionsTypeR.sltu -> ALUFunctions.sltu, + InstructionsTypeR.xor -> ALUFunctions.xor, + InstructionsTypeR.or -> ALUFunctions.or, + InstructionsTypeR.and -> ALUFunctions.and, + InstructionsTypeR.sr -> ALUFunctions.sr, + ), + ) + } + is(Instructions.jal) { + io.alu_funct := ALUFunctions.add + } + is(Instructions.jalr) { + io.alu_funct := ALUFunctions.add + } + is(Instructions.lui) { + io.alu_funct := ALUFunctions.add + } + is(Instructions.auipc) { + io.alu_funct := ALUFunctions.add + } + } +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/threestage/CLINT.scala b/mini-yatcpu/src/main/scala/riscv/core/threestage/CLINT.scala new file mode 100644 index 0000000..49bc2c0 --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/threestage/CLINT.scala @@ -0,0 +1,175 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.threestage + +import chisel3._ +import chisel3.util._ +import riscv.Parameters + +object InterruptStatus { + val None = 0x0.U(8.W) + val Timer0 = 0x1.U(8.W) + val Ret = 0xFF.U(8.W) +} + +object InterruptEntry { + val Timer0 = 0x4.U(8.W) +} + +object InterruptState { + val Idle = 0x0.U + val SyncAssert = 0x1.U + val AsyncAssert = 0x2.U + val MRET = 0x3.U +} + +object CSRState { + val Idle = 0x0.U + val MSTATUS = 0x1.U + val MEPC = 0x2.U + val MRET = 0x3.U + val MCAUSE = 0x4.U +} + +// Core Local Interrupt Controller +class CLINT extends Module { + val io = IO(new Bundle { + // Interrupt signals from peripherals + val interrupt_flag = Input(UInt(Parameters.InterruptFlagWidth)) + + // Current instruction from instruction decode + val instruction = Input(UInt(Parameters.InstructionWidth)) + val instruction_address_id = Input(UInt(Parameters.AddrWidth)) + + val jump_flag = Input(Bool()) + val jump_address = Input(UInt(Parameters.AddrWidth)) + + val csr_mtvec = Input(UInt(Parameters.DataWidth)) + val csr_mepc = Input(UInt(Parameters.DataWidth)) + val csr_mstatus = Input(UInt(Parameters.DataWidth)) + + // Is global interrupt enabled (from MSTATUS)? + val interrupt_enable = Input(Bool()) + + val ctrl_stall_flag = Output(Bool()) + + val csr_reg_write_enable = Output(Bool()) + val csr_reg_write_address = Output(UInt(Parameters.CSRRegisterAddrWidth)) + val csr_reg_write_data = Output(UInt(Parameters.DataWidth)) + + val ex_interrupt_handler_address = Output(UInt(Parameters.AddrWidth)) + val ex_interrupt_assert = Output(Bool()) + }) + + val interrupt_state = WireInit(0.U) + val csr_state = RegInit(CSRState.Idle) + val instruction_address = RegInit(UInt(Parameters.AddrWidth), 0.U) + val cause = RegInit(UInt(Parameters.DataWidth), 0.U) + val interrupt_assert = RegInit(Bool(), false.B) + val interrupt_handler_address = RegInit(UInt(Parameters.AddrWidth), 0.U) + val csr_reg_write_enable = RegInit(Bool(), false.B) + val csr_reg_write_address = RegInit(UInt(Parameters.CSRRegisterAddrWidth), 0.U) + val csr_reg_write_data = RegInit(UInt(Parameters.DataWidth), 0.U) + + io.ctrl_stall_flag := interrupt_state =/= InterruptState.Idle || csr_state =/= CSRState.Idle + + // Interrupt FSM + when(io.instruction === InstructionsEnv.ecall || io.instruction === InstructionsEnv.ebreak) { + interrupt_state := InterruptState.SyncAssert + }.elsewhen(io.interrupt_flag =/= InterruptStatus.None && io.interrupt_enable) { + interrupt_state := InterruptState.AsyncAssert + }.elsewhen(io.instruction === InstructionsRet.mret) { + interrupt_state := InterruptState.MRET + }.otherwise { + interrupt_state := InterruptState.Idle + } + + // CSR FSM + when(csr_state === CSRState.Idle) { + when(interrupt_state === InterruptState.SyncAssert) { + // Synchronous Interrupt + csr_state := CSRState.MEPC + instruction_address := Mux( + io.jump_flag, + io.jump_address - 4.U, + io.instruction_address_id + ) + + cause := MuxLookup(io.instruction, 10.U)( + IndexedSeq( + InstructionsEnv.ecall -> 11.U, + InstructionsEnv.ebreak -> 3.U, + ) + ) + }.elsewhen(interrupt_state === InterruptState.AsyncAssert) { + // Asynchronous Interrupt + cause := 0x8000000BL.U + when(io.interrupt_flag(0)) { + cause := 0x80000007L.U + } + csr_state := CSRState.MEPC + instruction_address := Mux( + io.jump_flag, + io.jump_address, + io.instruction_address_id, + ) + }.elsewhen(interrupt_state === InterruptState.MRET) { + // Interrupt Return + csr_state := CSRState.MRET + } + }.elsewhen(csr_state === CSRState.MEPC) { + csr_state := CSRState.MSTATUS + }.elsewhen(csr_state === CSRState.MSTATUS) { + csr_state := CSRState.MCAUSE + }.elsewhen(csr_state === CSRState.MCAUSE) { + csr_state := CSRState.Idle + }.elsewhen(csr_state === CSRState.MRET) { + csr_state := CSRState.Idle + }.otherwise { + csr_state := CSRState.Idle + } + + csr_reg_write_enable := csr_state =/= CSRState.Idle + csr_reg_write_address := Cat(Fill(20, 0.U(1.W)), MuxLookup(csr_state, 0.U(Parameters.CSRRegisterAddrWidth))( + IndexedSeq( + CSRState.MEPC -> CSRRegister.MEPC, + CSRState.MCAUSE -> CSRRegister.MCAUSE, + CSRState.MSTATUS -> CSRRegister.MSTATUS, + CSRState.MRET -> CSRRegister.MSTATUS, + ) + )) + csr_reg_write_data := MuxLookup(csr_state, 0.U(Parameters.DataWidth))( + IndexedSeq( + CSRState.MEPC -> instruction_address, + CSRState.MCAUSE -> cause, + CSRState.MSTATUS -> Cat(io.csr_mstatus(31, 4), 0.U(1.W), io.csr_mstatus(2, 0)), + CSRState.MRET -> Cat(io.csr_mstatus(31, 4), io.csr_mstatus(7), io.csr_mstatus(2, 0)), + ) + ) + io.csr_reg_write_enable := csr_reg_write_enable + io.csr_reg_write_address := csr_reg_write_address + io.csr_reg_write_data := csr_reg_write_data + + interrupt_assert := csr_state === CSRState.MCAUSE || csr_state === CSRState.MRET + interrupt_handler_address := MuxLookup(csr_state, 0.U(Parameters.AddrWidth))( + IndexedSeq( + CSRState.MCAUSE -> io.csr_mtvec, + CSRState.MRET -> io.csr_mepc, + ) + ) + + io.ex_interrupt_assert := interrupt_assert + io.ex_interrupt_handler_address := interrupt_handler_address +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/threestage/CPU.scala b/mini-yatcpu/src/main/scala/riscv/core/threestage/CPU.scala new file mode 100644 index 0000000..e23feab --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/threestage/CPU.scala @@ -0,0 +1,167 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.threestage + +import bus.AXI4LiteMaster +import chisel3._ +import riscv.Parameters +import riscv.core.CPUBundle + +class CPU extends Module { + val io = IO(new CPUBundle) + + val ctrl = Module(new Control) + val regs = Module(new RegisterFile) + val inst_fetch = Module(new InstructionFetch) + val if2id = Module(new IF2ID) + val id = Module(new InstructionDecode) + val id2ex = Module(new ID2EX) + val ex = Module(new Execute) + val clint = Module(new CLINT) + val csr_regs = Module(new CSR) + val axi4_master = Module(new AXI4LiteMaster(Parameters.AddrBits, Parameters.DataBits)) + + axi4_master.io.channels <> io.axi4_channels + io.debug(0) := ex.io.reg1_data + io.debug(1) := ex.io.reg2_data + io.debug(2) := ex.io.instruction_address + io.debug(3) := ex.io.instruction + io.debug(4) := ex.io.ctrl_jump_flag + io.debug(5) := ex.io.ctrl_jump_address + io.bus_busy := axi4_master.io.bundle.busy + + // The EX module takes precedence over IF (but let the previous fetch finish) + val ex_granted = RegInit(false.B) + when(ex_granted) { + inst_fetch.io.instruction_valid := false.B + io.bus_address := ex.io.bus.address + axi4_master.io.bundle.read := ex.io.bus.read + axi4_master.io.bundle.address := ex.io.bus.address + axi4_master.io.bundle.write := ex.io.bus.write + axi4_master.io.bundle.write_data := ex.io.bus.write_data + axi4_master.io.bundle.write_strobe := ex.io.bus.write_strobe + when(!ex.io.bus.request) { + ex_granted := false.B + } + }.otherwise { + // Default to fetch instructions from main memory + ex_granted := false.B + axi4_master.io.bundle.read := !axi4_master.io.bundle.busy && !axi4_master.io.bundle.read_valid && !ex.io.bus.request + axi4_master.io.bundle.address := inst_fetch.io.bus_address + io.bus_address := inst_fetch.io.bus_address + axi4_master.io.bundle.write := false.B + axi4_master.io.bundle.write_data := 0.U + axi4_master.io.bundle.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B)) + } + + when(ex.io.bus.request) { + when(!axi4_master.io.bundle.busy && !axi4_master.io.bundle.read_valid) { + ex_granted := true.B + } + } + + inst_fetch.io.instruction_valid := io.instruction_valid && axi4_master.io.bundle.read_valid && !ex_granted + inst_fetch.io.bus_data := axi4_master.io.bundle.read_data + + ex.io.bus.read_data := axi4_master.io.bundle.read_data + ex.io.bus.read_valid := axi4_master.io.bundle.read_valid + ex.io.bus.write_valid := axi4_master.io.bundle.write_valid + ex.io.bus.busy := axi4_master.io.bundle.busy + ex.io.bus.granted := ex_granted + + ctrl.io.jump_flag := ex.io.ctrl_jump_flag + ctrl.io.jump_address := ex.io.ctrl_jump_address + ctrl.io.stall_flag_if := inst_fetch.io.ctrl_stall_flag + ctrl.io.stall_flag_ex := ex.io.ctrl_stall_flag + ctrl.io.stall_flag_id := id.io.ctrl_stall_flag + ctrl.io.stall_flag_clint := clint.io.ctrl_stall_flag + ctrl.io.stall_flag_bus := io.stall_flag_bus + + regs.io.write_enable := ex.io.regs_write_enable + regs.io.write_address := ex.io.regs_write_address + regs.io.write_data := ex.io.regs_write_data + regs.io.read_address1 := id.io.regs_reg1_read_address + regs.io.read_address2 := id.io.regs_reg2_read_address + + regs.io.debug_read_address := io.debug_read_address + io.debug_read_data := regs.io.debug_read_data + + inst_fetch.io.jump_flag_ctrl := ctrl.io.pc_jump_flag + inst_fetch.io.jump_address_ctrl := ctrl.io.pc_jump_address + inst_fetch.io.stall_flag_ctrl := ctrl.io.output_stall_flag + + if2id.io.instruction := inst_fetch.io.id_instruction + if2id.io.instruction_address := inst_fetch.io.id_instruction_address + if2id.io.stall_flag := ctrl.io.output_stall_flag + if2id.io.jump_flag := ctrl.io.pc_jump_flag + if2id.io.interrupt_flag := io.interrupt_flag + + id.io.reg1_data := regs.io.read_data1 + id.io.reg2_data := regs.io.read_data2 + id.io.instruction := if2id.io.output_instruction + id.io.instruction_address := if2id.io.output_instruction_address + id.io.csr_read_data := csr_regs.io.id_reg_data + + id2ex.io.instruction := id.io.ex_instruction + id2ex.io.instruction_address := id.io.ex_instruction_address + id2ex.io.csr_read_data := id.io.ex_csr_read_data + id2ex.io.csr_write_enable := id.io.ex_csr_write_enable + id2ex.io.csr_write_address := id.io.ex_csr_write_address + id2ex.io.op1 := id.io.ex_op1 + id2ex.io.op2 := id.io.ex_op2 + id2ex.io.op1_jump := id.io.ex_op1_jump + id2ex.io.op2_jump := id.io.ex_op2_jump + id2ex.io.reg1_data := id.io.ex_reg1_data + id2ex.io.reg2_data := id.io.ex_reg2_data + id2ex.io.regs_write_enable := id.io.ex_reg_write_enable + id2ex.io.regs_write_address := id.io.ex_reg_write_address + id2ex.io.stall_flag := ctrl.io.output_stall_flag + id2ex.io.jump_flag := ctrl.io.pc_jump_flag + + ex.io.instruction := id2ex.io.output_instruction + ex.io.instruction_address := id2ex.io.output_instruction_address + ex.io.csr_reg_data_id := id2ex.io.output_csr_read_data + ex.io.csr_reg_write_enable_id := id2ex.io.output_csr_write_enable + ex.io.csr_reg_write_address_id := id2ex.io.output_csr_write_address + ex.io.op1 := id2ex.io.output_op1 + ex.io.op2 := id2ex.io.output_op2 + ex.io.op1_jump := id2ex.io.output_op1_jump + ex.io.op2_jump := id2ex.io.output_op2_jump + ex.io.reg1_data := id2ex.io.output_reg1_data + ex.io.reg2_data := id2ex.io.output_reg2_data + ex.io.regs_write_enable_id := id2ex.io.output_regs_write_enable + ex.io.regs_write_address_id := id2ex.io.output_regs_write_address + ex.io.interrupt_assert := clint.io.ex_interrupt_assert + ex.io.interrupt_handler_address := clint.io.ex_interrupt_handler_address + + clint.io.instruction := id.io.ex_instruction + clint.io.instruction_address_id := id.io.instruction_address + clint.io.jump_flag := ex.io.ctrl_jump_flag + clint.io.jump_address := ex.io.ctrl_jump_address + clint.io.csr_mepc := csr_regs.io.clint_csr_mepc + clint.io.csr_mtvec := csr_regs.io.clint_csr_mtvec + clint.io.csr_mstatus := csr_regs.io.clint_csr_mstatus + clint.io.interrupt_enable := csr_regs.io.interrupt_enable + clint.io.interrupt_flag := if2id.io.output_interrupt_flag + + csr_regs.io.reg_write_enable_ex := ex.io.csr_reg_write_enable + csr_regs.io.reg_write_address_ex := ex.io.csr_reg_write_address + csr_regs.io.reg_write_data_ex := ex.io.csr_reg_write_data + csr_regs.io.reg_read_address_id := id.io.csr_read_address + csr_regs.io.reg_write_enable_clint := clint.io.csr_reg_write_enable + csr_regs.io.reg_write_address_clint := clint.io.csr_reg_write_address + csr_regs.io.reg_write_data_clint := clint.io.csr_reg_write_data + csr_regs.io.reg_read_address_clint := 0.U +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/threestage/CSR.scala b/mini-yatcpu/src/main/scala/riscv/core/threestage/CSR.scala new file mode 100644 index 0000000..4266df2 --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/threestage/CSR.scala @@ -0,0 +1,122 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.threestage + +import chisel3._ +import chisel3.util._ +import riscv.Parameters + + +object CSRRegister { + // Refer to Spec. Vol.II Page 8-10 + val CycleL = 0xc00.U(Parameters.CSRRegisterAddrWidth) + val CycleH = 0xc80.U(Parameters.CSRRegisterAddrWidth) + val MTVEC = 0x305.U(Parameters.CSRRegisterAddrWidth) + val MCAUSE = 0x342.U(Parameters.CSRRegisterAddrWidth) + val MEPC = 0x341.U(Parameters.CSRRegisterAddrWidth) + val MIE = 0x304.U(Parameters.CSRRegisterAddrWidth) + val MSTATUS = 0x300.U(Parameters.CSRRegisterAddrWidth) + val MSCRATCH = 0x340.U(Parameters.CSRRegisterAddrWidth) +} + +class CSR extends Module { + val io = IO(new Bundle { + val reg_write_enable_ex = Input(Bool()) + val reg_read_address_id = Input(UInt(Parameters.CSRRegisterAddrWidth)) + val reg_write_address_ex = Input(UInt(Parameters.CSRRegisterAddrWidth)) + val reg_write_data_ex = Input(UInt(Parameters.DataWidth)) + + val reg_write_enable_clint = Input(Bool()) + val reg_read_address_clint = Input(UInt(Parameters.CSRRegisterAddrWidth)) + val reg_write_address_clint = Input(UInt(Parameters.CSRRegisterAddrWidth)) + val reg_write_data_clint = Input(UInt(Parameters.DataWidth)) + + val interrupt_enable = Output(Bool()) + + val id_reg_data = Output(UInt(Parameters.DataWidth)) + + val clint_reg_data = Output(UInt(Parameters.DataWidth)) + val clint_csr_mtvec = Output(UInt(Parameters.DataWidth)) + val clint_csr_mepc = Output(UInt(Parameters.DataWidth)) + val clint_csr_mstatus = Output(UInt(Parameters.DataWidth)) + }) + + + val cycles = RegInit(UInt(64.W), 0.U) + val mtvec = RegInit(UInt(Parameters.DataWidth), 0.U) + val mcause = RegInit(UInt(Parameters.DataWidth), 0.U) + val mepc = RegInit(UInt(Parameters.DataWidth), 0.U) + val mie = RegInit(UInt(Parameters.DataWidth), 0.U) + val mstatus = RegInit(UInt(Parameters.DataWidth), 0.U) + val mscratch = RegInit(UInt(Parameters.DataWidth), 0.U) + + cycles := cycles + 1.U + io.clint_csr_mtvec := mtvec + io.clint_csr_mepc := mepc + io.clint_csr_mstatus := mstatus + io.interrupt_enable := mstatus(3) === 1.U + + val reg_write_address = Wire(UInt(Parameters.CSRRegisterAddrWidth)) + val reg_write_data = Wire(UInt(Parameters.DataWidth)) + reg_write_address := 0.U + reg_write_data := 0.U + + val reg_read_address = Wire(UInt(Parameters.CSRRegisterAddrWidth)) + val reg_read_data = Wire(UInt(Parameters.DataWidth)) + reg_read_address := 0.U + reg_read_data := 0.U + + when(io.reg_write_enable_ex) { + reg_write_address := io.reg_write_address_ex(11, 0) + reg_write_data := io.reg_write_data_ex + }.elsewhen(io.reg_write_enable_clint) { + reg_write_address := io.reg_write_address_clint(11, 0) + reg_write_data := io.reg_write_data_clint + } + + when(reg_write_address === CSRRegister.MTVEC) { + mtvec := reg_write_data + }.elsewhen(reg_write_address === CSRRegister.MCAUSE) { + mcause := reg_write_data + }.elsewhen(reg_write_address === CSRRegister.MEPC) { + mepc := reg_write_data + }.elsewhen(reg_write_address === CSRRegister.MIE) { + mie := reg_write_data + }.elsewhen(reg_write_address === CSRRegister.MSTATUS) { + mstatus := reg_write_data + }.elsewhen(reg_write_address === CSRRegister.MSCRATCH) { + mscratch := reg_write_data + } + + val regLUT = + IndexedSeq( + CSRRegister.CycleL -> cycles(31, 0), + CSRRegister.CycleH -> cycles(63, 32), + CSRRegister.MTVEC -> mtvec, + CSRRegister.MCAUSE -> mcause, + CSRRegister.MEPC -> mepc, + CSRRegister.MIE -> mie, + CSRRegister.MSTATUS -> mstatus, + CSRRegister.MSCRATCH -> mscratch, + ) + + io.id_reg_data := MuxLookup(io.reg_read_address_id, 0.U)( + regLUT + ) + + io.clint_reg_data := MuxLookup(io.reg_read_address_clint, 0.U)( + regLUT + ) +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/threestage/Cache.scala b/mini-yatcpu/src/main/scala/riscv/core/threestage/Cache.scala new file mode 100644 index 0000000..4e52315 --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/threestage/Cache.scala @@ -0,0 +1,23 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.threestage + +import chisel3._ + +class Cache(cacheLineBytes: Int, associativity: Int, cacheLines: Int) extends Module { + val io = IO(new Bundle { + + }) +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/threestage/Control.scala b/mini-yatcpu/src/main/scala/riscv/core/threestage/Control.scala new file mode 100644 index 0000000..6790492 --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/threestage/Control.scala @@ -0,0 +1,55 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.threestage + +import chisel3._ +import chisel3.util._ +import riscv.Parameters + +object StallStates { + val None = 0.U + val PC = 1.U + val IF = 2.U + val ID = 3.U +} + +class Control extends Module { + val io = IO(new Bundle { + val jump_flag = Input(Bool()) + val stall_flag_if = Input(Bool()) + val stall_flag_id = Input(Bool()) + val stall_flag_ex = Input(Bool()) + val stall_flag_clint = Input(Bool()) + val stall_flag_bus = Input(Bool()) + val jump_address = Input(UInt(Parameters.AddrWidth)) + + val output_stall_flag = Output(UInt(Parameters.StallStateWidth)) + + val pc_jump_flag = Output(Bool()) + val pc_jump_address = Output(UInt(Parameters.AddrWidth)) + }) + + io.pc_jump_flag := io.jump_flag + io.pc_jump_address := io.jump_address + + io.output_stall_flag := MuxCase( + StallStates.None, + IndexedSeq( + (io.jump_flag || io.stall_flag_ex || io.stall_flag_clint) -> StallStates.ID, + io.stall_flag_id -> StallStates.IF, + (io.stall_flag_bus || io.stall_flag_if) -> StallStates.PC, + ) + ) +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/threestage/Execute.scala b/mini-yatcpu/src/main/scala/riscv/core/threestage/Execute.scala new file mode 100644 index 0000000..41a363d --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/threestage/Execute.scala @@ -0,0 +1,310 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.threestage + +import chisel3._ +import chisel3.util._ +import riscv.Parameters +import riscv.core.BusBundle + +object MemoryAccessStates extends ChiselEnum { + val Idle, Read, Write, ReadWrite = Value +} + +class Execute extends Module { + val io = IO(new Bundle { + val instruction = Input(UInt(Parameters.InstructionWidth)) + val instruction_address = Input(UInt(Parameters.AddrWidth)) + val interrupt_assert = Input(Bool()) + val interrupt_handler_address = Input(UInt(Parameters.AddrWidth)) + val regs_write_enable_id = Input(Bool()) + val regs_write_address_id = Input(UInt(Parameters.PhysicalRegisterAddrWidth)) + val csr_reg_write_enable_id = Input(Bool()) + val csr_reg_write_address_id = Input(UInt(Parameters.CSRRegisterAddrWidth)) + val csr_reg_data_id = Input(UInt(Parameters.DataWidth)) + val reg1_data = Input(UInt(Parameters.DataWidth)) + val reg2_data = Input(UInt(Parameters.DataWidth)) + val op1 = Input(UInt(Parameters.DataWidth)) + val op2 = Input(UInt(Parameters.DataWidth)) + val op1_jump = Input(UInt(Parameters.DataWidth)) + val op2_jump = Input(UInt(Parameters.DataWidth)) + + val bus = new BusBundle + + val regs_write_enable = Output(Bool()) + val regs_write_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth)) + val regs_write_data = Output(UInt(Parameters.DataWidth)) + + val ctrl_stall_flag = Output(Bool()) + val ctrl_jump_flag = Output(Bool()) + val ctrl_jump_address = Output(UInt(Parameters.AddrWidth)) + + val csr_reg_write_enable = Output(Bool()) + val csr_reg_write_address = Output(UInt(Parameters.CSRRegisterAddrWidth)) + val csr_reg_write_data = Output(UInt(Parameters.DataWidth)) + }) + + val opcode = io.instruction(6, 0) + val funct3 = io.instruction(14, 12) + val funct7 = io.instruction(31, 25) + val rd = io.instruction(11, 7) + val uimm = io.instruction(19, 15) + + val alu = Module(new ALU) + val alu_ctrl = Module(new ALUControl) + + alu_ctrl.io.opcode := opcode + alu_ctrl.io.funct3 := funct3 + alu_ctrl.io.funct7 := funct7 + alu.io.func := alu_ctrl.io.alu_funct + alu.io.op1 := io.op1 + alu.io.op2 := io.op2 + + + val mem_read_address_index = (io.op1 + io.op2)(log2Up(Parameters.WordSize) - 1, 0).asUInt + val mem_write_address_index = (io.op1 + io.op2)(log2Up(Parameters.WordSize) - 1, 0).asUInt + val mem_access_state = RegInit(MemoryAccessStates.Idle) + val pending_interrupt = RegInit(false.B) + val pending_interrupt_handler_address = RegInit(Parameters.EntryAddress) + + val jump_flag = Wire(Bool()) + val jump_address = Wire(UInt(Parameters.AddrWidth)) + + io.ctrl_jump_flag := jump_flag || io.interrupt_assert + io.ctrl_jump_address := Mux(io.interrupt_assert, io.interrupt_handler_address, jump_address) + + io.bus.read := false.B + io.bus.address := 0.U + io.bus.write_data := 0.U + io.bus.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B)) + io.bus.write := false.B + io.regs_write_enable := io.regs_write_enable_id && !io.interrupt_assert + io.regs_write_address := io.regs_write_address_id + io.regs_write_data := 0.U + io.csr_reg_write_enable := io.csr_reg_write_enable_id && !io.interrupt_assert + io.csr_reg_write_address := io.csr_reg_write_address_id + io.csr_reg_write_data := 0.U + io.bus.request := false.B + + def disable_control() = { + disable_stall() + disable_jump() + } + + def disable_stall() = { + io.ctrl_stall_flag := false.B + } + + def disable_jump() = { + jump_address := 0.U + jump_flag := false.B + } + + def check_interrupt_during_bus_transaction() = { + // Store the interrupt and process later + when(io.interrupt_assert) { + pending_interrupt := true.B + pending_interrupt_handler_address := io.interrupt_handler_address + io.ctrl_jump_flag := false.B + } + } + + def on_bus_transaction_finished() = { + mem_access_state := MemoryAccessStates.Idle + io.ctrl_stall_flag := false.B + when(pending_interrupt) { + pending_interrupt := false.B + io.ctrl_jump_flag := true.B + io.ctrl_jump_address := pending_interrupt_handler_address + } + } + + when(opcode === InstructionTypes.I) { + disable_control() + val mask = (0xFFFFFFFFL.U >> io.instruction(24, 20)).asUInt + io.regs_write_data := alu.io.result + when(funct3 === InstructionsTypeI.sri) { + when(funct7(5).asBool) { + io.regs_write_data := alu.io.result & mask | + (Fill(32, io.op1(31)) & (~mask).asUInt).asUInt + } + } + }.elsewhen(opcode === InstructionTypes.RM) { + disable_control() + // TODO(howard): support mul and div + when(funct7 === 0.U || funct7 === 0x20.U) { + val mask = (0xFFFFFFFFL.U >> io.reg2_data(4, 0)).asUInt + io.regs_write_data := alu.io.result + when(funct3 === InstructionsTypeR.sr) { + when(funct7(5).asBool) { + io.regs_write_data := alu.io.result & mask | + (Fill(32, io.op1(31)) & (~mask).asUInt).asUInt + } + } + } + }.elsewhen(opcode === InstructionTypes.L) { + disable_control() + + when(mem_access_state === MemoryAccessStates.Idle) { + // Start the read transaction when there is no interrupt asserted + // and the bus is available + when(!io.interrupt_assert) { + io.ctrl_stall_flag := true.B + io.regs_write_enable := false.B + io.bus.read := true.B + io.bus.address := io.op1 + io.op2 + io.bus.request := true.B + when(io.bus.granted) { + mem_access_state := MemoryAccessStates.Read + } + } + }.elsewhen(mem_access_state === MemoryAccessStates.Read) { + check_interrupt_during_bus_transaction() + io.bus.request := true.B + io.bus.read := false.B + io.ctrl_stall_flag := true.B + io.bus.address := io.op1 + io.op2 + when(io.bus.read_valid) { + io.regs_write_enable := true.B + val data = io.bus.read_data + io.regs_write_data := MuxLookup(funct3, 0.U)( + IndexedSeq( + InstructionsTypeL.lb -> MuxLookup( + mem_read_address_index, + Cat(Fill(24, data(31)), data(31, 24)))( + IndexedSeq( + 0.U -> Cat(Fill(24, data(7)), data(7, 0)), + 1.U -> Cat(Fill(24, data(15)), data(15, 8)), + 2.U -> Cat(Fill(24, data(23)), data(23, 16)) + ) + ), + InstructionsTypeL.lbu -> MuxLookup( + mem_read_address_index, + Cat(Fill(24, 0.U), data(31, 24)))( + IndexedSeq( + 0.U -> Cat(Fill(24, 0.U), data(7, 0)), + 1.U -> Cat(Fill(24, 0.U), data(15, 8)), + 2.U -> Cat(Fill(24, 0.U), data(23, 16)) + ) + ), + InstructionsTypeL.lh -> Mux( + mem_read_address_index === 0.U, + Cat(Fill(16, data(15)), data(15, 0)), + Cat(Fill(16, data(31)), data(31, 16)) + ), + InstructionsTypeL.lhu -> Mux( + mem_read_address_index === 0.U, + Cat(Fill(16, 0.U), data(15, 0)), + Cat(Fill(16, 0.U), data(31, 16)) + ), + InstructionsTypeL.lw -> data + ) + ) + on_bus_transaction_finished() + } + } + }.elsewhen(opcode === InstructionTypes.S) { + disable_control() + + when(mem_access_state === MemoryAccessStates.Idle) { + // Start the write transaction when there is no interrupt asserted + // and the bus is available + when(!io.interrupt_assert) { + io.ctrl_stall_flag := true.B + io.bus.address := io.op1 + io.op2 + io.bus.write_data := io.reg2_data + io.bus.write := true.B + io.bus.write_strobe := VecInit(Seq.fill(Parameters.WordSize)(false.B)) + when(funct3 === InstructionsTypeS.sb) { + io.bus.write_strobe(mem_write_address_index) := true.B + io.bus.write_data := io.reg2_data(Parameters.ByteBits, 0) << (mem_write_address_index << log2Up(Parameters + .ByteBits).U) + }.elsewhen(funct3 === InstructionsTypeS.sh) { + when(mem_write_address_index === 0.U) { + for (i <- 0 until Parameters.WordSize / 2) { + io.bus.write_strobe(i) := true.B + } + io.bus.write_data := io.reg2_data(Parameters.WordSize / 2 * Parameters.ByteBits, 0) + }.otherwise { + for (i <- Parameters.WordSize / 2 until Parameters.WordSize) { + io.bus.write_strobe(i) := true.B + } + io.bus.write_data := io.reg2_data(Parameters.WordSize / 2 * Parameters.ByteBits, 0) << (Parameters + .WordSize / 2 * Parameters.ByteBits) + } + }.elsewhen(funct3 === InstructionsTypeS.sw) { + for (i <- 0 until Parameters.WordSize) { + io.bus.write_strobe(i) := true.B + } + } + io.bus.request := true.B + when(io.bus.granted) { + mem_access_state := MemoryAccessStates.Write + } + } + }.elsewhen(mem_access_state === MemoryAccessStates.Write) { + check_interrupt_during_bus_transaction() + io.bus.request := true.B + io.ctrl_stall_flag := true.B + io.bus.write := false.B + io.bus.address := io.op1 + io.op2 + when(io.bus.write_valid) { + on_bus_transaction_finished() + } + } + }.elsewhen(opcode === InstructionTypes.B) { + disable_control() + jump_flag := MuxLookup(funct3, 0.U)( + IndexedSeq( + InstructionsTypeB.beq -> (io.op1 === io.op2), + InstructionsTypeB.bne -> (io.op1 =/= io.op2), + InstructionsTypeB.bltu -> (io.op1 < io.op2), + InstructionsTypeB.bgeu -> (io.op1 >= io.op2), + InstructionsTypeB.blt -> (io.op1.asSInt < io.op2.asSInt), + InstructionsTypeB.bge -> (io.op1.asSInt >= io.op2.asSInt) + ) + ) + jump_address := Fill(32, io.ctrl_jump_flag) & (io.op1_jump + io.op2_jump) + }.elsewhen(opcode === Instructions.jal || opcode === Instructions.jalr) { + disable_stall() + jump_flag := true.B + jump_address := io.op1_jump + io.op2_jump + io.regs_write_data := io.op1 + io.op2 + }.elsewhen(opcode === Instructions.lui || opcode === Instructions.auipc) { + disable_control() + io.regs_write_data := io.op1 + io.op2 + }.elsewhen(opcode === Instructions.csr) { + disable_control() + io.csr_reg_write_data := MuxLookup(funct3, 0.U)(IndexedSeq( + InstructionsTypeCSR.csrrw -> io.reg1_data, + InstructionsTypeCSR.csrrc -> io.csr_reg_data_id.&((~io.reg1_data).asUInt), + InstructionsTypeCSR.csrrs -> io.csr_reg_data_id.|(io.reg1_data), + InstructionsTypeCSR.csrrwi -> Cat(0.U(27.W), uimm), + InstructionsTypeCSR.csrrci -> io.csr_reg_data_id.&((~Cat(0.U(27.W), uimm)).asUInt), + InstructionsTypeCSR.csrrsi -> io.csr_reg_data_id.|(Cat(0.U(27.W), uimm)), + )) + io.regs_write_data := MuxLookup(funct3, 0.U)(IndexedSeq( + InstructionsTypeCSR.csrrw -> io.csr_reg_data_id, + InstructionsTypeCSR.csrrc -> io.csr_reg_data_id, + InstructionsTypeCSR.csrrs -> io.csr_reg_data_id, + InstructionsTypeCSR.csrrwi -> io.csr_reg_data_id, + InstructionsTypeCSR.csrrci -> io.csr_reg_data_id, + InstructionsTypeCSR.csrrsi -> io.csr_reg_data_id, + )) + }.otherwise { + disable_control() + io.regs_write_data := 0.U + } +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/threestage/ID2EX.scala b/mini-yatcpu/src/main/scala/riscv/core/threestage/ID2EX.scala new file mode 100644 index 0000000..fedd882 --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/threestage/ID2EX.scala @@ -0,0 +1,132 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.threestage + +import chisel3._ +import riscv.Parameters + +class ID2EX extends Module { + val io = IO(new Bundle { + val instruction = Input(UInt(Parameters.InstructionWidth)) + val instruction_address = Input(UInt(Parameters.AddrWidth)) + val regs_write_enable = Input(Bool()) + val regs_write_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth)) + val reg1_data = Input(UInt(Parameters.DataWidth)) + val reg2_data = Input(UInt(Parameters.DataWidth)) + val op1 = Input(UInt(Parameters.DataWidth)) + val op2 = Input(UInt(Parameters.DataWidth)) + val op1_jump = Input(UInt(Parameters.DataWidth)) + val op2_jump = Input(UInt(Parameters.DataWidth)) + val csr_write_enable = Input(Bool()) + val csr_write_address = Input(UInt(Parameters.CSRRegisterAddrWidth)) + val csr_read_data = Input(UInt(Parameters.DataWidth)) + val stall_flag = Input(UInt(Parameters.StallStateWidth)) + val jump_flag = Input(Bool()) + + val output_instruction = Output(UInt(Parameters.DataWidth)) + val output_instruction_address = Output(UInt(Parameters.AddrWidth)) + val output_regs_write_enable = Output(Bool()) + val output_regs_write_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth)) + val output_reg1_data = Output(UInt(Parameters.DataWidth)) + val output_reg2_data = Output(UInt(Parameters.DataWidth)) + val output_op1 = Output(UInt(Parameters.DataWidth)) + val output_op2 = Output(UInt(Parameters.DataWidth)) + val output_op1_jump = Output(UInt(Parameters.DataWidth)) + val output_op2_jump = Output(UInt(Parameters.DataWidth)) + val output_csr_write_enable = Output(Bool()) + val output_csr_write_address = Output(UInt(Parameters.CSRRegisterAddrWidth)) + val output_csr_read_data = Output(UInt(Parameters.DataWidth)) + }) + val write_enable = io.stall_flag < StallStates.ID + val flush_enable = io.jump_flag + + val instruction = Module(new PipelineRegister(defaultValue = InstructionsNop.nop)) + instruction.io.in := io.instruction + instruction.io.write_enable := write_enable + instruction.io.flush_enable := flush_enable + io.output_instruction := instruction.io.out + + val instruction_address = Module(new PipelineRegister(defaultValue = ProgramCounter.EntryAddress)) + instruction_address.io.in := io.instruction_address + instruction_address.io.write_enable := write_enable + instruction_address.io.flush_enable := flush_enable + io.output_instruction_address := instruction_address.io.out + + val regs_write_enable = Module(new PipelineRegister(1)) + regs_write_enable.io.in := io.regs_write_enable + regs_write_enable.io.write_enable := write_enable + regs_write_enable.io.flush_enable := flush_enable + io.output_regs_write_enable := regs_write_enable.io.out + + val regs_write_address = Module(new PipelineRegister(Parameters.PhysicalRegisterAddrBits)) + regs_write_address.io.in := io.regs_write_address + regs_write_address.io.write_enable := write_enable + regs_write_address.io.flush_enable := flush_enable + io.output_regs_write_address := regs_write_address.io.out + + val reg1_data = Module(new PipelineRegister()) + reg1_data.io.in := io.reg1_data + reg1_data.io.write_enable := write_enable + reg1_data.io.flush_enable := flush_enable + io.output_reg1_data := reg1_data.io.out + + val reg2_data = Module(new PipelineRegister()) + reg2_data.io.in := io.reg2_data + reg2_data.io.write_enable := write_enable + reg2_data.io.flush_enable := flush_enable + io.output_reg2_data := reg2_data.io.out + + val op1 = Module(new PipelineRegister()) + op1.io.in := io.op1 + op1.io.write_enable := write_enable + op1.io.flush_enable := flush_enable + io.output_op1 := op1.io.out + + val op2 = Module(new PipelineRegister()) + op2.io.in := io.op2 + op2.io.write_enable := write_enable + op2.io.flush_enable := flush_enable + io.output_op2 := op2.io.out + + val op1_jump = Module(new PipelineRegister()) + op1_jump.io.in := io.op1_jump + op1_jump.io.write_enable := write_enable + op1_jump.io.flush_enable := flush_enable + io.output_op1_jump := op1_jump.io.out + + val op2_jump = Module(new PipelineRegister()) + op2_jump.io.in := io.op2_jump + op2_jump.io.write_enable := write_enable + op2_jump.io.flush_enable := flush_enable + io.output_op2_jump := op2_jump.io.out + + val csr_write_enable = Module(new PipelineRegister()) + csr_write_enable.io.in := io.csr_write_enable + csr_write_enable.io.write_enable := write_enable + csr_write_enable.io.flush_enable := flush_enable + io.output_csr_write_enable := csr_write_enable.io.out + + val csr_write_address = Module(new PipelineRegister()) + csr_write_address.io.in := io.csr_write_address + csr_write_address.io.write_enable := write_enable + csr_write_address.io.flush_enable := flush_enable + io.output_csr_write_address := csr_write_address.io.out + + val csr_read_data = Module(new PipelineRegister()) + csr_read_data.io.in := io.csr_read_data + csr_read_data.io.write_enable := write_enable + csr_read_data.io.flush_enable := flush_enable + io.output_csr_read_data := csr_read_data.io.out +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/threestage/IF2ID.scala b/mini-yatcpu/src/main/scala/riscv/core/threestage/IF2ID.scala new file mode 100644 index 0000000..b0f6c27 --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/threestage/IF2ID.scala @@ -0,0 +1,53 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.threestage + +import chisel3._ +import riscv.Parameters + +class IF2ID extends Module { + val io = IO(new Bundle { + val instruction = Input(UInt(Parameters.InstructionWidth)) + val instruction_address = Input(UInt(Parameters.AddrWidth)) + val stall_flag = Input(UInt(Parameters.StallStateWidth)) + val interrupt_flag = Input(UInt(Parameters.InterruptFlagWidth)) + val jump_flag = Input(Bool()) + + val output_instruction = Output(UInt(Parameters.DataWidth)) + val output_instruction_address = Output(UInt(Parameters.AddrWidth)) + val output_interrupt_flag = Output(UInt(Parameters.InterruptFlagWidth)) + }) + + val write_enable = io.stall_flag < StallStates.IF + val flush_enable = io.jump_flag + + val instruction = Module(new PipelineRegister(defaultValue = InstructionsNop.nop)) + instruction.io.in := io.instruction + instruction.io.write_enable := write_enable + instruction.io.flush_enable := flush_enable + io.output_instruction := instruction.io.out + + val instruction_address = Module(new PipelineRegister(defaultValue = ProgramCounter.EntryAddress)) + instruction_address.io.in := io.instruction_address + instruction_address.io.write_enable := write_enable + instruction_address.io.flush_enable := flush_enable + io.output_instruction_address := instruction_address.io.out + + val interrupt_flag = Module(new PipelineRegister()) + interrupt_flag.io.in := io.interrupt_flag + interrupt_flag.io.write_enable := write_enable + interrupt_flag.io.flush_enable := flush_enable + io.output_interrupt_flag := interrupt_flag.io.out +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/threestage/InstructionDecode.scala b/mini-yatcpu/src/main/scala/riscv/core/threestage/InstructionDecode.scala new file mode 100644 index 0000000..7cd8b35 --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/threestage/InstructionDecode.scala @@ -0,0 +1,317 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.threestage + +import chisel3._ +import chisel3.util._ +import riscv.Parameters + + +object InstructionTypes { + val L = "b0000011".U + val I = "b0010011".U + val S = "b0100011".U + val RM = "b0110011".U + val B = "b1100011".U +} + +object Instructions { + val lui = "b0110111".U + val nop = "b0000001".U + val jal = "b1101111".U + val jalr = "b1100111".U + val auipc = "b0010111".U + val csr = "b1110011".U + val fence = "b0001111".U +} + +object InstructionsTypeL { + val lb = "b000".U + val lh = "b001".U + val lw = "b010".U + val lbu = "b100".U + val lhu = "b101".U +} + +object InstructionsTypeI { + val addi = 0.U + val slli = 1.U + val slti = 2.U + val sltiu = 3.U + val xori = 4.U + val sri = 5.U + val ori = 6.U + val andi = 7.U +} + +object InstructionsTypeS { + val sb = "b000".U + val sh = "b001".U + val sw = "b010".U +} + +object InstructionsTypeR { + val add_sub = 0.U + val sll = 1.U + val slt = 2.U + val sltu = 3.U + val xor = 4.U + val sr = 5.U + val or = 6.U + val and = 7.U +} + +object InstructionsTypeM { + val mul = 0.U + val mulh = 1.U + val mulhsu = 2.U + val mulhum = 3.U + val div = 4.U + val divu = 5.U + val rem = 6.U + val remu = 7.U +} + +object InstructionsTypeB { + val beq = "b000".U + val bne = "b001".U + val blt = "b100".U + val bge = "b101".U + val bltu = "b110".U + val bgeu = "b111".U +} + +object InstructionsTypeCSR { + val csrrw = "b001".U + val csrrs = "b010".U + val csrrc = "b011".U + val csrrwi = "b101".U + val csrrsi = "b110".U + val csrrci = "b111".U +} + +object InstructionsNop { + val nop = 0x00000013L.U(Parameters.DataWidth) +} + +object InstructionsRet { + val mret = 0x30200073L.U(Parameters.DataWidth) + val ret = 0x00008067L.U(Parameters.DataWidth) +} + +object InstructionsEnv { + val ecall = 0x00000073L.U(Parameters.DataWidth) + val ebreak = 0x00100073L.U(Parameters.DataWidth) +} + +class InstructionDecode extends Module { + val io = IO(new Bundle { + val instruction = Input(UInt(Parameters.InstructionWidth)) + val instruction_address = Input(UInt(Parameters.AddrWidth)) + val reg1_data = Input(UInt(Parameters.DataWidth)) + val reg2_data = Input(UInt(Parameters.DataWidth)) + + val csr_read_data = Input(UInt(Parameters.DataWidth)) + + val regs_reg1_read_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth)) + val regs_reg2_read_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth)) + + val ctrl_stall_flag = Output(UInt(Parameters.StallStateWidth)) + + val ex_op1 = Output(UInt(Parameters.DataWidth)) + val ex_op2 = Output(UInt(Parameters.DataWidth)) + val ex_op1_jump = Output(UInt(Parameters.DataWidth)) + val ex_op2_jump = Output(UInt(Parameters.DataWidth)) + val ex_instruction = Output(UInt(Parameters.DataWidth)) + val ex_instruction_address = Output(UInt(Parameters.AddrWidth)) + val ex_reg1_data = Output(UInt(Parameters.DataWidth)) + val ex_reg2_data = Output(UInt(Parameters.DataWidth)) + val ex_reg_write_enable = Output(Bool()) + val ex_reg_write_address = Output(UInt(Parameters.PhysicalRegisterAddrWidth)) + + val csr_read_address = Output(UInt(Parameters.CSRRegisterAddrWidth)) + val ex_csr_write_enable = Output(Bool()) + val ex_csr_write_address = Output(UInt(Parameters.CSRRegisterAddrWidth)) + val ex_csr_write_data = Output(UInt(Parameters.DataWidth)) + val ex_csr_read_data = Output(UInt(Parameters.DataWidth)) + }) + val opcode = io.instruction(6, 0) + val funct3 = io.instruction(14, 12) + val funct7 = io.instruction(31, 25) + val rd = io.instruction(11, 7) + val rs1 = io.instruction(19, 15) + val rs2 = io.instruction(24, 20) + + def disable_regs() = { + disable_write() + io.regs_reg1_read_address := 0.U + io.regs_reg2_read_address := 0.U + } + + def disable_write() = { + io.ex_reg_write_enable := false.B + io.ex_reg_write_address := 0.U + } + + def enable_write(addr: UInt) = { + io.ex_reg_write_enable := true.B + io.ex_reg_write_address := addr + } + + io.ex_instruction := io.instruction + io.ex_instruction_address := io.instruction_address + io.ex_reg1_data := io.reg1_data + io.ex_reg2_data := io.reg2_data + io.ex_op1 := 0.U + io.ex_op2 := 0.U + io.ex_op1_jump := 0.U + io.ex_op2_jump := 0.U + io.ctrl_stall_flag := false.B + io.csr_read_address := 0.U + io.ex_csr_read_data := io.csr_read_data + io.ex_csr_write_enable := false.B + io.ex_csr_write_data := 0.U + io.ex_csr_write_address := 0.U + + when(opcode === InstructionTypes.L) { + when( + funct3 === InstructionsTypeL.lb || + funct3 === InstructionsTypeL.lh || + funct3 === InstructionsTypeL.lw || + funct3 === InstructionsTypeL.lbu || + funct3 === InstructionsTypeL.lhu + ) { + enable_write(rd) + io.regs_reg1_read_address := rs1 + io.regs_reg2_read_address := 0.U + io.ex_op1 := io.reg1_data + io.ex_op2 := Cat(Fill(20, io.instruction(31)), io.instruction(31, 20)) + }.otherwise { + disable_regs() + } + }.elsewhen(opcode === InstructionTypes.I) { + enable_write(rd) + io.regs_reg1_read_address := rs1 + io.regs_reg2_read_address := 0.U + io.ex_op1 := io.reg1_data + io.ex_op2 := Cat(Fill(20, io.instruction(31)), io.instruction(31, 20)) + }.elsewhen(opcode === InstructionTypes.S) { + when(funct3 === InstructionsTypeS.sb || + funct3 === InstructionsTypeS.sh || + funct3 === InstructionsTypeS.sw) { + disable_write() + io.regs_reg1_read_address := rs1 + io.regs_reg2_read_address := rs2 + io.ex_op1 := io.reg1_data + io.ex_op2 := Cat(Fill(20, io.instruction(31)), io.instruction(31, 25), io.instruction(11, 7)) + }.otherwise { + disable_regs() + } + }.elsewhen(opcode === InstructionTypes.RM) { + when(funct7 === 0.U || funct7 === 0x20.U) { + enable_write(rd) + io.regs_reg1_read_address := rs1 + io.regs_reg2_read_address := rs2 + io.ex_op1 := io.reg1_data + io.ex_op2 := io.reg2_data + }.otherwise { + // TODO(howard): implement mul and div + disable_regs() + } + }.elsewhen(opcode === InstructionTypes.B) { + when( + funct3 === InstructionsTypeB.beq || + funct3 === InstructionsTypeB.bne || + funct3 === InstructionsTypeB.blt || + funct3 === InstructionsTypeB.bge || + funct3 === InstructionsTypeB.bltu || + funct3 === InstructionsTypeB.bgeu + ) { + disable_write() + io.regs_reg1_read_address := rs1 + io.regs_reg2_read_address := rs2 + io.ex_op1 := io.reg1_data + io.ex_op2 := io.reg2_data + io.ex_op1_jump := io.instruction_address + io.ex_op2_jump := Cat(Fill(20, io.instruction(31)), io.instruction(7), io.instruction(30, 25), io.instruction + (11, 8), 0.U(1.W)) + }.otherwise { + disable_regs() + } + }.elsewhen(opcode === Instructions.jal) { + enable_write(rd) + io.regs_reg1_read_address := 0.U + io.regs_reg2_read_address := 0.U + io.ex_op1 := io.instruction_address + io.ex_op2 := 4.U + io.ex_op1_jump := io.instruction_address + io.ex_op2_jump := Cat(Fill(12, io.instruction(31)), io.instruction(19, 12), io.instruction(20), io.instruction + (30, 21), 0.U(1.W)) + }.elsewhen(opcode === Instructions.jalr) { + enable_write(rd) + io.regs_reg1_read_address := rs1 + io.regs_reg2_read_address := 0.U + io.ex_op1 := io.instruction_address + io.ex_op2 := 4.U + io.ex_op1_jump := io.reg1_data + io.ex_op2_jump := Cat(Fill(20, io.instruction(31)), io.instruction(31, 20)) + }.elsewhen(opcode === Instructions.lui) { + enable_write(rd) + io.regs_reg1_read_address := 0.U + io.regs_reg2_read_address := 0.U + io.ex_op1 := Cat(io.instruction(31, 12), Fill(12, 0.U(1.W))) + io.ex_op2 := 0.U + }.elsewhen(opcode === Instructions.auipc) { + enable_write(rd) + io.regs_reg1_read_address := 0.U + io.regs_reg2_read_address := 0.U + io.ex_op1 := io.instruction_address + io.ex_op2 := Cat(io.instruction(31, 12), Fill(12, 0.U(1.W))) + }.elsewhen(opcode === Instructions.csr) { + disable_regs() + io.csr_read_address := Cat(0.U(20.W), io.instruction(31, 20)) + io.ex_csr_write_address := Cat(0.U(20.W), io.instruction(31, 20)) + when( + funct3 === InstructionsTypeCSR.csrrc || + funct3 === InstructionsTypeCSR.csrrs || + funct3 === InstructionsTypeCSR.csrrw + ) { + io.regs_reg1_read_address := rs1 + io.regs_reg2_read_address := 0.U + io.ex_reg_write_enable := true.B + io.ex_reg_write_address := rd + io.ex_csr_write_enable := true.B + }.elsewhen( + funct3 === InstructionsTypeCSR.csrrci || + funct3 === InstructionsTypeCSR.csrrsi || + funct3 === InstructionsTypeCSR.csrrwi + ) { + io.regs_reg1_read_address := 0.U + io.regs_reg2_read_address := 0.U + io.ex_reg_write_enable := true.B + io.ex_reg_write_address := rd + io.ex_csr_write_enable := true.B + }.otherwise { + io.ex_csr_write_enable := false.B + io.ex_csr_write_data := 0.U + io.ex_csr_write_address := 0.U + } + }.elsewhen(opcode === Instructions.nop) { + disable_regs() + }.otherwise { + disable_regs() + } + +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/threestage/InstructionFetch.scala b/mini-yatcpu/src/main/scala/riscv/core/threestage/InstructionFetch.scala new file mode 100644 index 0000000..63d80b5 --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/threestage/InstructionFetch.scala @@ -0,0 +1,69 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.threestage + +import chisel3._ +import chisel3.util.MuxCase +import riscv.Parameters + +object ProgramCounter { + val EntryAddress = Parameters.EntryAddress +} + +class InstructionFetch extends Module { + val io = IO(new Bundle { + val stall_flag_ctrl = Input(Bool()) + val jump_flag_ctrl = Input(Bool()) + val jump_address_ctrl = Input(UInt(Parameters.AddrWidth)) + val instruction_valid = Input(Bool()) + + val bus_request = Output(Bool()) + val bus_address = Output(UInt(Parameters.AddrWidth)) + val bus_data = Input(UInt(Parameters.InstructionWidth)) + val bus_read = Output(Bool()) + + val ctrl_stall_flag = Output(Bool()) + val id_instruction_address = Output(UInt(Parameters.AddrWidth)) + val id_instruction = Output(UInt(Parameters.InstructionWidth)) + }) + val instruction_address = RegInit(ProgramCounter.EntryAddress) + val pending_jump = RegInit(false.B) + val pc = RegInit(ProgramCounter.EntryAddress) + io.bus_read := true.B + io.bus_request := true.B + + pc := MuxCase( + pc + 4.U, + IndexedSeq( + io.jump_flag_ctrl -> io.jump_address_ctrl, + (io.stall_flag_ctrl >= StallStates.PC) -> pc + ) + ) + when(!io.instruction_valid) { + when(io.jump_flag_ctrl) { + pending_jump := true.B + } + } + when(io.instruction_valid) { + when(pending_jump) { + pending_jump := false.B + } + } + io.id_instruction := Mux(io.instruction_valid && !io.jump_flag_ctrl && !pending_jump, io.bus_data, + InstructionsNop.nop) + io.ctrl_stall_flag := !io.instruction_valid || pending_jump + io.id_instruction_address := pc + io.bus_address := pc +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/threestage/PipelineRegister.scala b/mini-yatcpu/src/main/scala/riscv/core/threestage/PipelineRegister.scala new file mode 100644 index 0000000..1d54282 --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/threestage/PipelineRegister.scala @@ -0,0 +1,35 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.threestage + +import chisel3._ +import riscv.Parameters + +class PipelineRegister(width: Int = Parameters.DataBits, defaultValue: UInt = 0.U) extends Module { + val io = IO(new Bundle { + val write_enable = Input(Bool()) + val flush_enable = Input(Bool()) + val in = Input(UInt(width.W)) + val out = Output(UInt(width.W)) + }) + + val reg = RegInit(UInt(width.W), defaultValue) + when(io.write_enable) { + reg := io.in + }.elsewhen(io.flush_enable) { + reg := defaultValue + } + io.out := reg +} diff --git a/mini-yatcpu/src/main/scala/riscv/core/threestage/RegisterFile.scala b/mini-yatcpu/src/main/scala/riscv/core/threestage/RegisterFile.scala new file mode 100644 index 0000000..3d68974 --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/core/threestage/RegisterFile.scala @@ -0,0 +1,78 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.core.threestage + +import chisel3._ +import chisel3.util._ +import riscv.Parameters + +object Registers extends Enumeration { + type Register = Value + val zero, + ra, sp, gp, tp, + t0, t1, t2, fp, + s1, + a0, a1, a2, a3, a4, a5, a6, a7, + s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, + t3, t4, t5, t6 = Value +} + +class RegisterFile extends Module { + val io = IO(new Bundle { + val write_enable = Input(Bool()) + val write_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth)) + val write_data = Input(UInt(Parameters.DataWidth)) + + val read_address1 = Input(UInt(Parameters.PhysicalRegisterAddrWidth)) + val read_address2 = Input(UInt(Parameters.PhysicalRegisterAddrWidth)) + val read_data1 = Output(UInt(Parameters.DataWidth)) + val read_data2 = Output(UInt(Parameters.DataWidth)) + + val debug_read_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth)) + val debug_read_data = Output(UInt(Parameters.DataWidth)) + }) + val registers = Reg(Vec(Parameters.PhysicalRegisters, UInt(Parameters.DataWidth))) + + when(!reset.asBool) { + when(io.write_enable && io.write_address =/= 0.U) { + registers(io.write_address) := io.write_data + } + } + + io.read_data1 := MuxCase( + registers(io.read_address1), + IndexedSeq( + (io.read_address1 === 0.U) -> 0.U, + (io.read_address1 === io.write_address && io.write_enable) -> io.write_data + ) + ) + + io.read_data2 := MuxCase( + registers(io.read_address2), + IndexedSeq( + (io.read_address2 === 0.U) -> 0.U, + (io.read_address2 === io.write_address && io.write_enable) -> io.write_data + ) + ) + + io.debug_read_data := MuxCase( + registers(io.debug_read_address), + IndexedSeq( + (io.debug_read_address === 0.U) -> 0.U, + (io.debug_read_address === io.write_address && io.write_enable) -> io.write_data + ) + ) + +} diff --git a/mini-yatcpu/src/main/scala/riscv/debug/DebugModule.scala b/mini-yatcpu/src/main/scala/riscv/debug/DebugModule.scala new file mode 100644 index 0000000..23ab101 --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/debug/DebugModule.scala @@ -0,0 +1,33 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.debug + +import chisel3._ + +object DMRegisters { + val DATA0 = 0x04.U + val DATA11 = 0x0F.U + val DMCONTROL = 0x10.U + val DMSTATUS = 0x11.U + val HARTINFO = 0x12.U + val ABSTRACTCS = 0x16.U + val COMMAND = 0x17.U +} + +class DebugModule extends Module { + val io = IO(new Bundle { + + }) +} diff --git a/mini-yatcpu/src/main/scala/riscv/debug/DebugTransportModule.scala b/mini-yatcpu/src/main/scala/riscv/debug/DebugTransportModule.scala new file mode 100644 index 0000000..9e6a29f --- /dev/null +++ b/mini-yatcpu/src/main/scala/riscv/debug/DebugTransportModule.scala @@ -0,0 +1,34 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.debug + +import chisel3._ + +object DTMRegisters { + val IDCODE = 0x01.U + val DTMCS = 0x10.U + val DMI = 0x11.U + val BYPASS1F = 0x1F.U +} + +class DebugTransportModule extends Module { + val io = IO(new Bundle { + + }) + + val idcode = 0x1e200151.U + val dtmcs = RegInit("b00000000000000000101000011100001".U) + val dmi = RegInit(UInt(48.W)) +} diff --git a/mini-yatcpu/src/test/scala/riscv/BoardTest.scala b/mini-yatcpu/src/test/scala/riscv/BoardTest.scala new file mode 100644 index 0000000..40bd459 --- /dev/null +++ b/mini-yatcpu/src/test/scala/riscv/BoardTest.scala @@ -0,0 +1,25 @@ +package riscv + +import board.z710.Top + +import riscv.{Parameters, TestAnnotations} +import chisel3._ +import chisel3.util.{is, switch} +import chiseltest._ +import org.scalatest.flatspec.AnyFlatSpec +import board.z710.Top + + +class SayGoodbyeTest extends AnyFlatSpec with ChiselScalatestTester { + behavior of "Board simulation" + it should "say goodbye " in { + test(new Top("say_goodbye.asmbin")).withAnnotations(TestAnnotations.annos) { c => + + for (i <- 1 to 50000) { + c.clock.step(5) + c.io.rx.poke((i % 2).U) // poke some useless value, since rx not yet used + } + } + } +} + diff --git a/mini-yatcpu/src/test/scala/riscv/PeripheralTest.scala b/mini-yatcpu/src/test/scala/riscv/PeripheralTest.scala new file mode 100644 index 0000000..9e9fe1a --- /dev/null +++ b/mini-yatcpu/src/test/scala/riscv/PeripheralTest.scala @@ -0,0 +1,164 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv + +import bus.{AXI4LiteMaster, AXI4LiteMasterBundle, AXI4LiteSlave, AXI4LiteSlaveBundle} +import chisel3._ +import chiseltest._ +import org.scalatest.flatspec.AnyFlatSpec +import peripheral.{Memory, ROMLoader} + +class TimerTest extends AnyFlatSpec with ChiselScalatestTester { + class TestTimerLimit extends Module { + val io = IO(new Bundle { + val limit = Output(UInt()) + val bundle = new AXI4LiteMasterBundle(Parameters.AddrBits, Parameters.DataBits) + }) + val timer = Module(new peripheral.Timer) + val master = Module(new AXI4LiteMaster(Parameters.AddrBits, Parameters.DataBits)) + io.limit := timer.io.debug_limit + master.io.bundle <> io.bundle + timer.io.channels <> master.io.channels + } + + behavior of "Timer" + it should "read and write the limit" in { + test(new TestTimerLimit).withAnnotations(TestAnnotations.annos) { + c => + c.io.bundle.read.poke(false.B) + c.io.bundle.write.poke(true.B) + c.io.bundle.address.poke(0x4.U) + c.io.bundle.write_data.poke(0x990315.U) + c.clock.step() + c.io.bundle.busy.expect(true.B) + c.io.bundle.write.poke(false.B) + c.io.bundle.address.poke(0x0.U) + c.io.bundle.write_data.poke(0.U) + c.clock.step(8) + c.io.bundle.busy.expect(false.B) + c.io.bundle.write_valid.expect(true.B) + c.io.limit.expect(0x990315.U) + c.io.bundle.read.poke(true.B) + c.io.bundle.address.poke(0x4.U) + c.clock.step() + c.io.bundle.busy.expect(true.B) + c.clock.step(6) + c.io.bundle.busy.expect(false.B) + c.io.bundle.read_valid.expect(true.B) + c.io.bundle.read_data.expect(0x990315.U) + } + } +} + +class MemoryTest extends AnyFlatSpec with ChiselScalatestTester { + class MemoryTest extends Module { + val io = IO(new Bundle { + val bundle = new AXI4LiteMasterBundle(Parameters.AddrBits, Parameters.DataBits) + + val write_strobe = Input(UInt(4.W)) + }) + val memory = Module(new Memory(4096)) + val master = Module(new AXI4LiteMaster(Parameters.AddrBits, Parameters.DataBits)) + + master.io.bundle <> io.bundle + master.io.bundle.write_strobe := VecInit(io.write_strobe.asBools) + master.io.channels <> memory.io.channels + + memory.io.debug_read_address := 0.U + } + + behavior of "Memory" + it should "perform read and write" in { + test(new MemoryTest).withAnnotations(TestAnnotations.annos) { c => + c.io.bundle.read.poke(false.B) + c.io.bundle.write.poke(true.B) + c.io.write_strobe.poke(0xF.U) + c.io.bundle.address.poke(0x4.U) + c.io.bundle.write_data.poke(0xDEADBEEFL.U) + c.clock.step() + c.io.bundle.busy.expect(true.B) + c.io.bundle.write.poke(false.B) + c.io.bundle.address.poke(0x0.U) + c.io.bundle.write_data.poke(0.U) + c.clock.step(8) + c.io.bundle.busy.expect(false.B) + c.io.bundle.write_valid.expect(true.B) + c.io.bundle.read.poke(true.B) + c.io.bundle.address.poke(0x4.U) + c.clock.step() + c.io.bundle.busy.expect(true.B) + c.clock.step(6) + c.io.bundle.busy.expect(false.B) + c.io.bundle.read_valid.expect(true.B) + c.io.bundle.read_data.expect(0xDEADBEEFL.U) + } + } + +} + +class ROMLoaderTest extends AnyFlatSpec with ChiselScalatestTester { + + class ROMLoaderTest extends Module { + val io = IO(new Bundle { + val rom_address = Output(UInt(32.W)) + val rom_data = Input(UInt(32.W)) + val load_start = Input(Bool()) + val load_address = Input(UInt(32.W)) + val load_finished = Output(Bool()) + + val bundle = new AXI4LiteSlaveBundle(32, 32) + }) + + val rom_loader = Module(new ROMLoader(2)) + rom_loader.io.rom_data := io.rom_data + rom_loader.io.load_start := io.load_start + rom_loader.io.load_address := io.load_address + io.load_finished := rom_loader.io.load_finished + io.rom_address := rom_loader.io.rom_address + + val slave = Module(new AXI4LiteSlave(Parameters.AddrBits, Parameters.DataBits)) + slave.io.bundle <> io.bundle + slave.io.channels <> rom_loader.io.channels + slave.io.bundle.read_data := 0.U + } + + + behavior of "ROMLoader" + it should "load program" in { + test(new ROMLoaderTest).withAnnotations(TestAnnotations.annos) { c => + c.io.load_address.poke(0x100.U) + c.io.load_start.poke(true.B) + c.clock.step() + c.io.load_start.poke(false.B) + c.io.rom_address.expect(0x0.U) + c.clock.step(8) + c.io.bundle.write.expect(true.B) + c.io.bundle.address.expect(0x100.U) + c.clock.step(4) + c.io.rom_address.expect(0x1.U) + c.clock.step(7) + c.io.rom_address.expect(0x1.U) + c.io.bundle.write.expect(true.B) + c.io.bundle.address.expect(0x104.U) + c.clock.step() + c.io.rom_address.expect(0x1.U) + c.clock.step(3) + c.io.load_finished.expect(true.B) + } + } +} + + + diff --git a/mini-yatcpu/src/test/scala/riscv/TestAnnotations.scala b/mini-yatcpu/src/test/scala/riscv/TestAnnotations.scala new file mode 100644 index 0000000..7842a95 --- /dev/null +++ b/mini-yatcpu/src/test/scala/riscv/TestAnnotations.scala @@ -0,0 +1,52 @@ +// Copyright 2022 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv + +import chiseltest.{VerilatorBackendAnnotation, WriteVcdAnnotation} +import firrtl.AnnotationSeq + +import java.nio.file.{Files, Paths} + +object VerilatorEnabler { + val annos: AnnotationSeq = if (sys.env.contains("Path")) { + if (sys.env.getOrElse("Path", "").split(";").exists(path => { + Files.exists(Paths.get(path, "verilator")) + })) { + Seq(VerilatorBackendAnnotation) + } else { + Seq() + } + } else { + if (sys.env.getOrElse("PATH", "").split(":").exists(path => { + Files.exists(Paths.get(path, "verilator")) + })) { + Seq(VerilatorBackendAnnotation) + } else { + Seq() + } + } +} + +object WriteVcdEnabler { + val annos: AnnotationSeq = if (sys.env.contains("WRITE_VCD")) { + Seq(WriteVcdAnnotation) + } else { + Seq() + } +} + +object TestAnnotations { + val annos = VerilatorEnabler.annos ++ WriteVcdEnabler.annos +} diff --git a/mini-yatcpu/src/test/scala/riscv/fivestage/CPUTest.scala b/mini-yatcpu/src/test/scala/riscv/fivestage/CPUTest.scala new file mode 100644 index 0000000..baef0b2 --- /dev/null +++ b/mini-yatcpu/src/test/scala/riscv/fivestage/CPUTest.scala @@ -0,0 +1,184 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.fivestage + +import board.basys3.BootStates +import bus.BusSwitch +import chisel3._ +import chisel3.util.{is, switch} +import chiseltest._ +import org.scalatest.flatspec.AnyFlatSpec +import peripheral.{DummySlave, Memory, ROMLoader} +import riscv.core.fivestage.{CPU, ProgramCounter} +import riscv.{Parameters, TestAnnotations} + +import java.nio.{ByteBuffer, ByteOrder} + +class TestInstructionROM(asmBin: String) extends Module { + val io = IO(new Bundle { + val address = Input(UInt(32.W)) + val data = Output(UInt(32.W)) + }) + + val (insts, capacity) = loadAsmBinary(asmBin) + val mem = RegInit(insts) + io.data := mem(io.address) + + def loadAsmBinary(filename: String) = { + val inputStream = getClass.getClassLoader.getResourceAsStream(filename) + var instructions = new Array[BigInt](0) + val arr = new Array[Byte](4) + while (inputStream.read(arr) == 4) { + val instBuf = ByteBuffer.wrap(arr) + instBuf.order(ByteOrder.LITTLE_ENDIAN) + val inst = BigInt(instBuf.getInt() & 0xFFFFFFFFL) + instructions = instructions :+ inst + } + (VecInit((instructions.map(inst => inst.U(32.W))).toIndexedSeq), instructions.length) + } +} + +class TestTopModule(exeFilename: String) extends Module { + val io = IO(new Bundle { + val mem_debug_read_address = Input(UInt(Parameters.AddrWidth)) + val regs_debug_read_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth)) + val regs_debug_read_data = Output(UInt(Parameters.DataWidth)) + val mem_debug_read_data = Output(UInt(Parameters.DataWidth)) + + val interrupt = Input(UInt(Parameters.InterruptFlagWidth)) + val boot_state = Output(UInt()) + }) + val boot_state = RegInit(BootStates.Init) + io.boot_state := boot_state.asUInt + val instruction_rom = Module(new TestInstructionROM(exeFilename)) + val rom_loader = Module(new ROMLoader(instruction_rom.capacity)) + val mem = Module(new Memory(8192)) + val cpu = Module(new CPU) + val timer = Module(new peripheral.Timer) + val bus_switch = Module(new BusSwitch) + val dummy = Module(new DummySlave) + bus_switch.io.master <> cpu.io.axi4_channels + bus_switch.io.address := cpu.io.bus_address + for (i <- 0 until Parameters.SlaveDeviceCount) { + bus_switch.io.slaves(i) <> dummy.io.channels + } + rom_loader.io.load_address := ProgramCounter.EntryAddress + rom_loader.io.rom_data := instruction_rom.io.data + rom_loader.io.load_start := false.B + instruction_rom.io.address := rom_loader.io.rom_address + cpu.io.stall_flag_bus := true.B + cpu.io.instruction_valid := false.B + bus_switch.io.slaves(0) <> mem.io.channels + rom_loader.io.channels <> dummy.io.channels + switch(boot_state) { + is(BootStates.Init) { + rom_loader.io.load_start := true.B + boot_state := BootStates.Loading + rom_loader.io.channels <> mem.io.channels + } + is(BootStates.Loading) { + rom_loader.io.load_start := false.B + rom_loader.io.channels <> mem.io.channels + when(rom_loader.io.load_finished) { + boot_state := BootStates.Finished + } + } + is(BootStates.Finished) { + rom_loader.io.load_start := false.B + cpu.io.stall_flag_bus := false.B + cpu.io.instruction_valid := true.B + } + } + bus_switch.io.slaves(4) <> timer.io.channels + + mem.io.debug_read_address := io.mem_debug_read_address + cpu.io.debug_read_address := io.regs_debug_read_address + io.regs_debug_read_data := cpu.io.debug_read_data + io.mem_debug_read_data := mem.io.debug_read_data + + cpu.io.interrupt_flag := io.interrupt +} + + +class FibonacciTest extends AnyFlatSpec with ChiselScalatestTester { + behavior of "Five Stage CPU" + it should "calculate recursively fibonacci(10)" in { + test(new TestTopModule("fibonacci.asmbin")).withAnnotations(TestAnnotations.annos) { c => + c.io.interrupt.poke(0.U) + for (i <- 1 to 100) { + c.clock.step(1000) + c.io.mem_debug_read_address.poke((i * 4).U) // Avoid timeout + } + + c.io.mem_debug_read_address.poke(4.U) + c.clock.step() + c.io.mem_debug_read_data.expect(55.U) + } + } +} + +class QuicksortTest extends AnyFlatSpec with ChiselScalatestTester { + behavior of "Five Stage CPU" + it should "quicksort 10 numbers" in { + test(new TestTopModule("quicksort.asmbin")).withAnnotations(TestAnnotations.annos) { c => + c.io.interrupt.poke(0.U) + for (i <- 1 to 50) { + c.clock.step(1000) + c.io.mem_debug_read_address.poke((i * 4).U) // Avoid timeout + } + for (i <- 1 to 10) { + c.io.mem_debug_read_address.poke((4 * i).U) + c.clock.step() + c.io.mem_debug_read_data.expect((i - 1).U) + } + } + } +} + +class MMIOTest extends AnyFlatSpec with ChiselScalatestTester { + behavior of "Five Stage CPU" + it should "read and write timer register" in { + test(new TestTopModule("mmio.asmbin")).withAnnotations(TestAnnotations.annos) { c => + c.io.interrupt.poke(0.U) + for (i <- 1 to 1000) { + c.clock.step() + c.io.mem_debug_read_address.poke((i * 4).U) // Avoid timeout + } + c.io.regs_debug_read_address.poke(5.U) + c.io.regs_debug_read_data.expect(100000000.U) + c.io.regs_debug_read_address.poke(6.U) + c.io.regs_debug_read_data.expect(0xBEEF.U) + } + } +} + +class ByteAccessTest extends AnyFlatSpec with ChiselScalatestTester { + behavior of "Five Stage CPU" + it should "store and load single byte" in { + test(new TestTopModule("sb.asmbin")).withAnnotations(TestAnnotations.annos) { c => + c.io.interrupt.poke(0.U) + for (i <- 1 to 500) { + c.clock.step() + c.io.mem_debug_read_address.poke((i * 4).U) // Avoid timeout + } + c.io.regs_debug_read_address.poke(5.U) + c.io.regs_debug_read_data.expect(0xDEADBEEFL.U) + c.io.regs_debug_read_address.poke(6.U) + c.io.regs_debug_read_data.expect(0xEF.U) + c.io.regs_debug_read_address.poke(1.U) + c.io.regs_debug_read_data.expect(0x15EF.U) + } + } +} diff --git a/mini-yatcpu/src/test/scala/riscv/fivestage/RegisterFileTest.scala b/mini-yatcpu/src/test/scala/riscv/fivestage/RegisterFileTest.scala new file mode 100644 index 0000000..a230b87 --- /dev/null +++ b/mini-yatcpu/src/test/scala/riscv/fivestage/RegisterFileTest.scala @@ -0,0 +1,68 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.fivestage + +import chisel3._ +import chiseltest._ +import org.scalatest.flatspec.AnyFlatSpec +import riscv.TestAnnotations +import riscv.core.fivestage.RegisterFile + +class RegisterFileTest extends AnyFlatSpec with ChiselScalatestTester { + behavior of "Register File of Five-stage CPU" + it should "read the written content" in { + test(new RegisterFile).withAnnotations(TestAnnotations.annos) { c => + timescope { + c.io.write_enable.poke(true.B) + c.io.write_address.poke(1.U) + c.io.write_data.poke(0xDEADBEEFL.U) + c.clock.step() + } + c.io.read_address1.poke(1.U) + c.io.read_data1.expect(0xDEADBEEFL.U) + } + } + + it should "x0 always be zero" in { + test(new RegisterFile).withAnnotations(TestAnnotations.annos) { c => + timescope { + c.io.write_enable.poke(true.B) + c.io.write_address.poke(0.U) + c.io.write_data.poke(0xDEADBEEFL.U) + c.clock.step() + } + c.io.read_address1.poke(0.U) + c.io.read_data1.expect(0.U) + } + } + + it should "read the writing content" in { + test(new RegisterFile).withAnnotations(TestAnnotations.annos) { c => + timescope { + c.io.read_address1.poke(2.U) + c.io.read_data1.expect(0.U) + c.io.write_enable.poke(true.B) + c.io.write_address.poke(2.U) + c.io.write_data.poke(0xDEADBEEFL.U) + c.io.read_address1.poke(2.U) + c.io.read_data1.expect(0xDEADBEEFL.U) + c.clock.step() + } + c.io.read_address1.poke(2.U) + c.io.read_data1.expect(0xDEADBEEFL.U) + } + } + +} diff --git a/mini-yatcpu/src/test/scala/riscv/threestage/CPUTest.scala b/mini-yatcpu/src/test/scala/riscv/threestage/CPUTest.scala new file mode 100644 index 0000000..0c1535c --- /dev/null +++ b/mini-yatcpu/src/test/scala/riscv/threestage/CPUTest.scala @@ -0,0 +1,185 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.threestage + +import board.basys3.BootStates +import bus.BusSwitch +import chisel3._ +import chisel3.util.{is, switch} +import chiseltest._ +import org.scalatest.flatspec.AnyFlatSpec +import peripheral.{DummySlave, Memory, ROMLoader} +import riscv.core.threestage.{CPU, ProgramCounter} +import riscv.{Parameters, TestAnnotations} + +import java.nio.{ByteBuffer, ByteOrder} + +class TestInstructionROM(asmBin: String) extends Module { + val io = IO(new Bundle { + val address = Input(UInt(32.W)) + val data = Output(UInt(32.W)) + }) + + val (insts, capacity) = loadAsmBinary(asmBin) + val mem = RegInit(insts) + io.data := mem(io.address) + + def loadAsmBinary(filename: String) = { + val inputStream = getClass.getClassLoader.getResourceAsStream(filename) + var instructions = new Array[BigInt](0) + val arr = new Array[Byte](4) + while (inputStream.read(arr) == 4) { + val instBuf = ByteBuffer.wrap(arr) + instBuf.order(ByteOrder.LITTLE_ENDIAN) + val inst = BigInt(instBuf.getInt() & 0xFFFFFFFFL) + instructions = instructions :+ inst + } + (VecInit((instructions.map(inst => inst.U(32.W))).toIndexedSeq), instructions.length) + } +} + +class TestTopModule(exeFilename: String) extends Module { + val io = IO(new Bundle { + val mem_debug_read_address = Input(UInt(Parameters.AddrWidth)) + val regs_debug_read_address = Input(UInt(Parameters.PhysicalRegisterAddrWidth)) + val regs_debug_read_data = Output(UInt(Parameters.DataWidth)) + val mem_debug_read_data = Output(UInt(Parameters.DataWidth)) + + val interrupt = Input(UInt(Parameters.InterruptFlagWidth)) + val boot_state = Output(UInt()) + }) + val boot_state = RegInit(BootStates.Init) + io.boot_state := boot_state.asUInt + val instruction_rom = Module(new TestInstructionROM(exeFilename)) + val rom_loader = Module(new ROMLoader(instruction_rom.capacity)) + val mem = Module(new Memory(8192)) + val cpu = Module(new CPU) + val timer = Module(new peripheral.Timer) + val bus_switch = Module(new BusSwitch) + val dummy = Module(new DummySlave) + bus_switch.io.master <> cpu.io.axi4_channels + bus_switch.io.address := cpu.io.bus_address + for (i <- 0 until Parameters.SlaveDeviceCount) { + bus_switch.io.slaves(i) <> dummy.io.channels + } + rom_loader.io.load_address := ProgramCounter.EntryAddress + rom_loader.io.rom_data := instruction_rom.io.data + rom_loader.io.load_start := false.B + instruction_rom.io.address := rom_loader.io.rom_address + cpu.io.stall_flag_bus := true.B + cpu.io.instruction_valid := false.B + bus_switch.io.slaves(0) <> mem.io.channels + rom_loader.io.channels <> dummy.io.channels + switch(boot_state) { + is(BootStates.Init) { + rom_loader.io.load_start := true.B + boot_state := BootStates.Loading + rom_loader.io.channels <> mem.io.channels + } + is(BootStates.Loading) { + rom_loader.io.load_start := false.B + rom_loader.io.channels <> mem.io.channels + when(rom_loader.io.load_finished) { + boot_state := BootStates.Finished + } + } + is(BootStates.Finished) { + rom_loader.io.load_start := false.B + cpu.io.stall_flag_bus := false.B + cpu.io.instruction_valid := true.B + } + } + bus_switch.io.slaves(4) <> timer.io.channels + + mem.io.debug_read_address := io.mem_debug_read_address + cpu.io.debug_read_address := io.regs_debug_read_address + io.regs_debug_read_data := cpu.io.debug_read_data + io.mem_debug_read_data := mem.io.debug_read_data + + cpu.io.interrupt_flag := io.interrupt +} + + +class FibonacciTest extends AnyFlatSpec with ChiselScalatestTester { + behavior of "CPU" + it should "calculate recursively fibonacci(10)" in { + test(new TestTopModule("fibonacci.asmbin")).withAnnotations(TestAnnotations.annos) { c => + c.io.interrupt.poke(0.U) + for (i <- 1 to 50) { + c.clock.step(1000) + c.io.mem_debug_read_address.poke((i * 4).U) // Avoid timeout + } + + c.io.mem_debug_read_address.poke(4.U) + c.clock.step() + c.io.mem_debug_read_data.expect(55.U) + } + } +} + +class QuicksortTest extends AnyFlatSpec with ChiselScalatestTester { + behavior of "CPU" + it should "quicksort 10 numbers" in { + test(new TestTopModule("quicksort.asmbin")).withAnnotations(TestAnnotations.annos) { c => + c.io.interrupt.poke(0.U) + for (i <- 1 to 50) { + c.clock.step(1000) + c.io.mem_debug_read_address.poke((i * 4).U) // Avoid timeout + } + for (i <- 1 to 10) { + c.io.mem_debug_read_address.poke((4 * i).U) + c.clock.step() + c.io.mem_debug_read_data.expect((i - 1).U) + } + } + } +} + +class MMIOTest extends AnyFlatSpec with ChiselScalatestTester { + behavior of "CPU" + it should "read and write timer register" in { + test(new TestTopModule("mmio.asmbin")).withAnnotations(TestAnnotations.annos) { c => + c.io.interrupt.poke(0.U) + for (i <- 1 to 200) { + c.clock.step() + c.io.mem_debug_read_address.poke((i * 4).U) // Avoid timeout + } + c.io.regs_debug_read_address.poke(5.U) + c.io.regs_debug_read_data.expect(100000000.U) + c.io.regs_debug_read_address.poke(6.U) + c.io.regs_debug_read_data.expect(0xBEEF.U) + } + } +} + +class ByteAccessTest extends AnyFlatSpec with ChiselScalatestTester { + behavior of "CPU" + it should "store and load single byte" in { + test(new TestTopModule("sb.asmbin")).withAnnotations(TestAnnotations.annos) { c => + c.io.interrupt.poke(0.U) + for (i <- 1 to 500) { + c.clock.step() + c.io.mem_debug_read_address.poke((i * 4).U) // Avoid timeout + } + c.io.regs_debug_read_address.poke(5.U) + c.io.regs_debug_read_data.expect(0xDEADBEEFL.U) + c.io.regs_debug_read_address.poke(6.U) + c.io.regs_debug_read_data.expect(0xEF.U) + c.io.regs_debug_read_address.poke(1.U) + c.io.regs_debug_read_data.expect(0x15EF.U) + } + } +} + diff --git a/mini-yatcpu/src/test/scala/riscv/threestage/RegisterFileTest.scala b/mini-yatcpu/src/test/scala/riscv/threestage/RegisterFileTest.scala new file mode 100644 index 0000000..2c33c10 --- /dev/null +++ b/mini-yatcpu/src/test/scala/riscv/threestage/RegisterFileTest.scala @@ -0,0 +1,68 @@ +// Copyright 2021 Howard Lau +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +package riscv.threestage + +import chisel3._ +import chiseltest._ +import org.scalatest.flatspec.AnyFlatSpec +import riscv.TestAnnotations +import riscv.core.threestage.RegisterFile + +class RegisterFileTest extends AnyFlatSpec with ChiselScalatestTester { + behavior of "Register File" + it should "read the written content" in { + test(new RegisterFile).withAnnotations(TestAnnotations.annos) { c => + timescope { + c.io.write_enable.poke(true.B) + c.io.write_address.poke(1.U) + c.io.write_data.poke(0xDEADBEEFL.U) + c.clock.step() + } + c.io.read_address1.poke(1.U) + c.io.read_data1.expect(0xDEADBEEFL.U) + } + } + + it should "x0 always be zero" in { + test(new RegisterFile).withAnnotations(TestAnnotations.annos) { c => + timescope { + c.io.write_enable.poke(true.B) + c.io.write_address.poke(0.U) + c.io.write_data.poke(0xDEADBEEFL.U) + c.clock.step() + } + c.io.read_address1.poke(0.U) + c.io.read_data1.expect(0.U) + } + } + + it should "read the writing content" in { + test(new RegisterFile).withAnnotations(TestAnnotations.annos) { c => + timescope { + c.io.read_address1.poke(2.U) + c.io.read_data1.expect(0.U) + c.io.write_enable.poke(true.B) + c.io.write_address.poke(2.U) + c.io.write_data.poke(0xDEADBEEFL.U) + c.io.read_address1.poke(2.U) + c.io.read_data1.expect(0xDEADBEEFL.U) + c.clock.step() + } + c.io.read_address1.poke(2.U) + c.io.read_data1.expect(0xDEADBEEFL.U) + } + } + +} diff --git a/mini-yatcpu/verilog/basys3/test.v b/mini-yatcpu/verilog/basys3/test.v new file mode 100644 index 0000000..9f3f6a6 --- /dev/null +++ b/mini-yatcpu/verilog/basys3/test.v @@ -0,0 +1,35 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2021/12/17 16:31:05 +// Design Name: +// Module Name: test +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module test(); +reg clock; +reg reset; +initial begin +clock = 0; +forever #1 clock = ~clock; +end +initial begin +reset = 1; +#2 reset = 0; +end +Top top(clock, reset); +endmodule diff --git a/mini-yatcpu/verilog/pynq/TMDS_PLLVR.v b/mini-yatcpu/verilog/pynq/TMDS_PLLVR.v new file mode 100644 index 0000000..1bc4dfb --- /dev/null +++ b/mini-yatcpu/verilog/pynq/TMDS_PLLVR.v @@ -0,0 +1,221 @@ + +// file: TMDS_PLLVR.v +// +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// __clkout__250.00000______0.000______50.0______200.536____237.727 +// _clkoutd__100.00000______0.000______50.0______226.965____237.727 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary__________25.000____________0.010 + +`timescale 1ps/1ps + +(* CORE_GENERATION_INFO = "TMDS_PLLVR,clk_wiz_v6_0_5_0_0,{component_name=TMDS_PLLVR,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=2,clkin1_period=40.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=true}" *) + +module TMDS_PLLVR + ( + // Clock out ports + output clkout, + output clkoutd, + // Status and control signals + input reset, + output lock, + // Clock in ports + input clkin + ); + + TMDS_PLLVR_clk_wiz inst + ( + // Clock out ports + .clkout(clkout), + .clkoutd(clkoutd), + // Status and control signals + .reset(reset), + .lock(lock), + // Clock in ports + .clk_in1(clkin) + ); + +endmodule + + +module TMDS_PLLVR_clk_wiz + + (// Clock in ports + // Clock out ports + output clkout, + output clkoutd, + // Status and control signals + input reset, + output lock, + input clk_in1 + ); + // Input buffering + //------------------------------------ +wire clk_in1_TMDS_PLLVR; +wire clk_in2_TMDS_PLLVR; + IBUF clkin1_ibufg + (.O (clk_in1_TMDS_PLLVR), + .I (clk_in1)); + + + + + // Clocking PRIMITIVE + //------------------------------------ + + // Instantiation of the MMCM PRIMITIVE + // * Unused inputs are tied off + // * Unused outputs are labeled unused + + wire clkout_TMDS_PLLVR; + wire clkoutd_TMDS_PLLVR; + wire clk_out3_TMDS_PLLVR; + wire clk_out4_TMDS_PLLVR; + wire clk_out5_TMDS_PLLVR; + wire clk_out6_TMDS_PLLVR; + wire clk_out7_TMDS_PLLVR; + + wire [15:0] do_unused; + wire drdy_unused; + wire psdone_unused; + wire lock_int; + wire clkfbout_TMDS_PLLVR; + wire clkfbout_buf_TMDS_PLLVR; + wire clkfboutb_unused; + wire clkout2_unused; + wire clkout3_unused; + wire clkout4_unused; + wire clkout5_unused; + wire clkout6_unused; + wire clkfbstopped_unused; + wire clkinstopped_unused; + wire reset_high; + + PLLE2_ADV + #(.BANDWIDTH ("OPTIMIZED"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (1), + .CLKFBOUT_MULT (40), + .CLKFBOUT_PHASE (0.000), + .CLKOUT0_DIVIDE (4), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT1_DIVIDE (10), + .CLKOUT1_PHASE (0.000), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKIN1_PERIOD (40.000)) + plle2_adv_inst + // Output clocks + ( + .CLKFBOUT (clkfbout_TMDS_PLLVR), + .CLKOUT0 (clkout_TMDS_PLLVR), + .CLKOUT1 (clkoutd_TMDS_PLLVR), + .CLKOUT2 (clkout2_unused), + .CLKOUT3 (clkout3_unused), + .CLKOUT4 (clkout4_unused), + .CLKOUT5 (clkout5_unused), + // Input clock control + .CLKFBIN (clkfbout_buf_TMDS_PLLVR), + .CLKIN1 (clk_in1_TMDS_PLLVR), + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (do_unused), + .DRDY (drdy_unused), + .DWE (1'b0), + // Other control and status signals + .LOCKED (lock_int), + .PWRDWN (1'b0), + .RST (reset_high)); + assign reset_high = reset; + + assign lock = lock_int; +// Clock Monitor clock assigning +//-------------------------------------- + // Output buffering + //----------------------------------- + + BUFG clkf_buf + (.O (clkfbout_buf_TMDS_PLLVR), + .I (clkfbout_TMDS_PLLVR)); + + + + + + + BUFG clkout1_buf + (.O (clkout), + .I (clkout_TMDS_PLLVR)); + + + BUFG clkout2_buf + (.O (clkoutd), + .I (clkoutd_TMDS_PLLVR)); + + + +endmodule diff --git a/mini-yatcpu/verilog/pynq/design_1_wrapper.v b/mini-yatcpu/verilog/pynq/design_1_wrapper.v new file mode 100644 index 0000000..5e2092d --- /dev/null +++ b/mini-yatcpu/verilog/pynq/design_1_wrapper.v @@ -0,0 +1,136 @@ +//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020 +//Date : Thu Jun 9 10:53:21 2022 +//Host : DESKTOP-UR8AHA2 running 64-bit major release (build 9200) +//Command : generate_target design_1_wrapper.bd +//Design : design_1_wrapper +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module design_1_wrapper + (DDR_addr, + DDR_ba, + DDR_cas_n, + DDR_ck_n, + DDR_ck_p, + DDR_cke, + DDR_cs_n, + DDR_dm, + DDR_dq, + DDR_dqs_n, + DDR_dqs_p, + DDR_odt, + DDR_ras_n, + DDR_reset_n, + DDR_we_n, + FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp, + FIXED_IO_mio, + FIXED_IO_ps_clk, + FIXED_IO_ps_porb, + FIXED_IO_ps_srstb, + io_hdmi_clk_n, + io_hdmi_clk_p, + io_hdmi_data_n, + io_hdmi_data_p, + io_hdmi_hpdn, + io_led, + io_rx, + io_tx, + reset); + inout [14:0]DDR_addr; + inout [2:0]DDR_ba; + inout DDR_cas_n; + inout DDR_ck_n; + inout DDR_ck_p; + inout DDR_cke; + inout DDR_cs_n; + inout [3:0]DDR_dm; + inout [31:0]DDR_dq; + inout [3:0]DDR_dqs_n; + inout [3:0]DDR_dqs_p; + inout DDR_odt; + inout DDR_ras_n; + inout DDR_reset_n; + inout DDR_we_n; + inout FIXED_IO_ddr_vrn; + inout FIXED_IO_ddr_vrp; + inout [53:0]FIXED_IO_mio; + inout FIXED_IO_ps_clk; + inout FIXED_IO_ps_porb; + inout FIXED_IO_ps_srstb; + output io_hdmi_clk_n; + output io_hdmi_clk_p; + output [2:0]io_hdmi_data_n; + output [2:0]io_hdmi_data_p; + output io_hdmi_hpdn; + output [3:0]io_led; + input io_rx; + output io_tx; + input reset; + + wire [14:0]DDR_addr; + wire [2:0]DDR_ba; + wire DDR_cas_n; + wire DDR_ck_n; + wire DDR_ck_p; + wire DDR_cke; + wire DDR_cs_n; + wire [3:0]DDR_dm; + wire [31:0]DDR_dq; + wire [3:0]DDR_dqs_n; + wire [3:0]DDR_dqs_p; + wire DDR_odt; + wire DDR_ras_n; + wire DDR_reset_n; + wire DDR_we_n; + wire FIXED_IO_ddr_vrn; + wire FIXED_IO_ddr_vrp; + wire [53:0]FIXED_IO_mio; + wire FIXED_IO_ps_clk; + wire FIXED_IO_ps_porb; + wire FIXED_IO_ps_srstb; + wire io_hdmi_clk_n; + wire io_hdmi_clk_p; + wire [2:0]io_hdmi_data_n; + wire [2:0]io_hdmi_data_p; + wire io_hdmi_hpdn; + wire [3:0]io_led; + wire io_rx; + wire io_tx; + wire reset; + + design_1 design_1_i + (.DDR_addr(DDR_addr), + .DDR_ba(DDR_ba), + .DDR_cas_n(DDR_cas_n), + .DDR_ck_n(DDR_ck_n), + .DDR_ck_p(DDR_ck_p), + .DDR_cke(DDR_cke), + .DDR_cs_n(DDR_cs_n), + .DDR_dm(DDR_dm), + .DDR_dq(DDR_dq), + .DDR_dqs_n(DDR_dqs_n), + .DDR_dqs_p(DDR_dqs_p), + .DDR_odt(DDR_odt), + .DDR_ras_n(DDR_ras_n), + .DDR_reset_n(DDR_reset_n), + .DDR_we_n(DDR_we_n), + .FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn), + .FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp), + .FIXED_IO_mio(FIXED_IO_mio), + .FIXED_IO_ps_clk(FIXED_IO_ps_clk), + .FIXED_IO_ps_porb(FIXED_IO_ps_porb), + .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb), + .io_hdmi_clk_n(io_hdmi_clk_n), + .io_hdmi_clk_p(io_hdmi_clk_p), + .io_hdmi_data_n(io_hdmi_data_n), + .io_hdmi_data_p(io_hdmi_data_p), + .io_hdmi_hpdn(io_hdmi_hpdn), + .io_led(io_led), + .io_rx(io_rx), + .io_tx(io_tx), + .reset(reset)); +endmodule diff --git a/mini-yatcpu/verilog/pynq/test.v b/mini-yatcpu/verilog/pynq/test.v new file mode 100644 index 0000000..9f3f6a6 --- /dev/null +++ b/mini-yatcpu/verilog/pynq/test.v @@ -0,0 +1,35 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2021/12/17 16:31:05 +// Design Name: +// Module Name: test +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module test(); +reg clock; +reg reset; +initial begin +clock = 0; +forever #1 clock = ~clock; +end +initial begin +reset = 1; +#2 reset = 0; +end +Top top(clock, reset); +endmodule diff --git a/mini-yatcpu/verilog/say_goodbye.asmbin.txt b/mini-yatcpu/verilog/say_goodbye.asmbin.txt new file mode 100644 index 0000000..722841d --- /dev/null +++ b/mini-yatcpu/verilog/say_goodbye.asmbin.txt @@ -0,0 +1,2102 @@ +@0 +10000137 +@1 +00000097 +@2 +1e4080e7 +@3 +0000006f +@4 +00000297 +@5 +04028293 +@6 +30529373 +@7 +000022b7 +@8 +88828293 +@9 +30029373 +@a +00008067 +@b +800002b7 +@c +00528293 +@d +18029073 +@e +00008067 +@f +34302573 +@10 +00008067 +@11 +34102573 +@12 +00008067 +@13 +00008067 +@14 +34011073 +@15 +f8010113 +@16 +00112223 +@17 +00312623 +@18 +00412823 +@19 +00512a23 +@1a +00612c23 +@1b +00712e23 +@1c +02412023 +@1d +02912223 +@1e +02a12423 +@1f +02b12623 +@20 +02c12823 +@21 +02d12a23 +@22 +02e12c23 +@23 +02f12e23 +@24 +05012023 +@25 +05112223 +@26 +05212423 +@27 +05312623 +@28 +05412823 +@29 +05512a23 +@2a +05612c23 +@2b +05712e23 +@2c +07812023 +@2d +07912223 +@2e +07a12423 +@2f +07b12623 +@30 +07c12823 +@31 +07d12a23 +@32 +07e12c23 +@33 +07f12e23 +@34 +34102573 +@35 +342025f3 +@36 +00000097 +@37 +000080e7 +@38 +00412083 +@39 +00c12183 +@3a +01012203 +@3b +01412283 +@3c +01812303 +@3d +01c12383 +@3e +02012203 +@3f +02412483 +@40 +02812503 +@41 +02c12583 +@42 +03012603 +@43 +03412683 +@44 +03812703 +@45 +03c12783 +@46 +04012803 +@47 +04412883 +@48 +04812903 +@49 +04c12983 +@4a +05012a03 +@4b +05412a83 +@4c +05812b03 +@4d +05c12b83 +@4e +06012c03 +@4f +06412c83 +@50 +06812d03 +@51 +06c12d83 +@52 +07012e03 +@53 +07412e83 +@54 +07812f03 +@55 +07c12f83 +@56 +34002173 +@57 +30200073 +@58 +ff010113 +@59 +00112623 +@5a +00812423 +@5b +01010413 +@5c +fea40ba3 +@5d +ff744503 +@5e +400005b7 +@5f +00a5a823 +@60 +00c12083 +@61 +00812403 +@62 +01010113 +@63 +00008067 +@64 +ff010113 +@65 +00112623 +@66 +00812423 +@67 +01010413 +@68 +fea42a23 +@69 +08700513 +@6a +fea42823 +@6b +0040006f +@6c +ff442503 +@6d +fff50593 +@6e +feb42a23 +@6f +00000593 +@70 +00b50c63 +@71 +0040006f +@72 +ff042503 +@73 +00150513 +@74 +fea42823 +@75 +fddff06f +@76 +00c12083 +@77 +00812403 +@78 +01010113 +@79 +00008067 +@7a +fe010113 +@7b +00112e23 +@7c +00812c23 +@7d +02010413 +@7e +00000513 +@7f +fea42a23 +@80 +00002537 +@81 +00050513 +@82 +fea42823 +@83 +0040006f +@84 +ff042503 +@85 +fea42623 +@86 +0040006f +@87 +fec42503 +@88 +00054503 +@89 +00000593 +@8a +02b50a63 +@8b +0040006f +@8c +fec42503 +@8d +00054503 +@8e +00000097 +@8f +f28080e7 +@90 +fec42503 +@91 +00150513 +@92 +fea42623 +@93 +06400513 +@94 +00000097 +@95 +f40080e7 +@96 +fc5ff06f +@97 +0c800513 +@98 +00000097 +@99 +f30080e7 +@9a +0040006f +@9b +00000513 +@9c +01c12083 +@9d +01812403 +@9e +02010113 +@9f +00008067 +@a0 +00000000 +@a1 +00000000 +@a2 +00000000 +@a3 +00000000 +@a4 +00000000 +@a5 +00000000 +@a6 +00000000 +@a7 +00000000 +@a8 +00000000 +@a9 +00000000 +@aa +00000000 +@ab +00000000 +@ac +00000000 +@ad +00000000 +@ae +00000000 +@af +00000000 +@b0 +00000000 +@b1 +00000000 +@b2 +00000000 +@b3 +00000000 +@b4 +00000000 +@b5 +00000000 +@b6 +00000000 +@b7 +00000000 +@b8 +00000000 +@b9 +00000000 +@ba +00000000 +@bb +00000000 +@bc +00000000 +@bd +00000000 +@be +00000000 +@bf +00000000 +@c0 +00000000 +@c1 +00000000 +@c2 +00000000 +@c3 +00000000 +@c4 +00000000 +@c5 +00000000 +@c6 +00000000 +@c7 +00000000 +@c8 +00000000 +@c9 +00000000 +@ca +00000000 +@cb +00000000 +@cc +00000000 +@cd +00000000 +@ce +00000000 +@cf +00000000 +@d0 +00000000 +@d1 +00000000 +@d2 +00000000 +@d3 +00000000 +@d4 +00000000 +@d5 +00000000 +@d6 +00000000 +@d7 +00000000 +@d8 +00000000 +@d9 +00000000 +@da +00000000 +@db +00000000 +@dc +00000000 +@dd +00000000 +@de +00000000 +@df +00000000 +@e0 +00000000 +@e1 +00000000 +@e2 +00000000 +@e3 +00000000 +@e4 +00000000 +@e5 +00000000 +@e6 +00000000 +@e7 +00000000 +@e8 +00000000 +@e9 +00000000 +@ea +00000000 +@eb +00000000 +@ec +00000000 +@ed +00000000 +@ee +00000000 +@ef +00000000 +@f0 +00000000 +@f1 +00000000 +@f2 +00000000 +@f3 +00000000 +@f4 +00000000 +@f5 +00000000 +@f6 +00000000 +@f7 +00000000 +@f8 +00000000 +@f9 +00000000 +@fa +00000000 +@fb +00000000 +@fc +00000000 +@fd +00000000 +@fe +00000000 +@ff +00000000 +@100 +00000000 +@101 +00000000 +@102 +00000000 +@103 +00000000 +@104 +00000000 +@105 +00000000 +@106 +00000000 +@107 +00000000 +@108 +00000000 +@109 +00000000 +@10a +00000000 +@10b +00000000 +@10c +00000000 +@10d +00000000 +@10e +00000000 +@10f +00000000 +@110 +00000000 +@111 +00000000 +@112 +00000000 +@113 +00000000 +@114 +00000000 +@115 +00000000 +@116 +00000000 +@117 +00000000 +@118 +00000000 +@119 +00000000 +@11a +00000000 +@11b +00000000 +@11c +00000000 +@11d +00000000 +@11e +00000000 +@11f +00000000 +@120 +00000000 +@121 +00000000 +@122 +00000000 +@123 +00000000 +@124 +00000000 +@125 +00000000 +@126 +00000000 +@127 +00000000 +@128 +00000000 +@129 +00000000 +@12a +00000000 +@12b +00000000 +@12c +00000000 +@12d +00000000 +@12e +00000000 +@12f +00000000 +@130 +00000000 +@131 +00000000 +@132 +00000000 +@133 +00000000 +@134 +00000000 +@135 +00000000 +@136 +00000000 +@137 +00000000 +@138 +00000000 +@139 +00000000 +@13a +00000000 +@13b +00000000 +@13c +00000000 +@13d +00000000 +@13e +00000000 +@13f +00000000 +@140 +00000000 +@141 +00000000 +@142 +00000000 +@143 +00000000 +@144 +00000000 +@145 +00000000 +@146 +00000000 +@147 +00000000 +@148 +00000000 +@149 +00000000 +@14a +00000000 +@14b +00000000 +@14c +00000000 +@14d +00000000 +@14e +00000000 +@14f +00000000 +@150 +00000000 +@151 +00000000 +@152 +00000000 +@153 +00000000 +@154 +00000000 +@155 +00000000 +@156 +00000000 +@157 +00000000 +@158 +00000000 +@159 +00000000 +@15a +00000000 +@15b +00000000 +@15c +00000000 +@15d +00000000 +@15e +00000000 +@15f +00000000 +@160 +00000000 +@161 +00000000 +@162 +00000000 +@163 +00000000 +@164 +00000000 +@165 +00000000 +@166 +00000000 +@167 +00000000 +@168 +00000000 +@169 +00000000 +@16a +00000000 +@16b +00000000 +@16c +00000000 +@16d +00000000 +@16e +00000000 +@16f +00000000 +@170 +00000000 +@171 +00000000 +@172 +00000000 +@173 +00000000 +@174 +00000000 +@175 +00000000 +@176 +00000000 +@177 +00000000 +@178 +00000000 +@179 +00000000 +@17a +00000000 +@17b +00000000 +@17c +00000000 +@17d +00000000 +@17e +00000000 +@17f +00000000 +@180 +00000000 +@181 +00000000 +@182 +00000000 +@183 +00000000 +@184 +00000000 +@185 +00000000 +@186 +00000000 +@187 +00000000 +@188 +00000000 +@189 +00000000 +@18a +00000000 +@18b +00000000 +@18c +00000000 +@18d +00000000 +@18e +00000000 +@18f +00000000 +@190 +00000000 +@191 +00000000 +@192 +00000000 +@193 +00000000 +@194 +00000000 +@195 +00000000 +@196 +00000000 +@197 +00000000 +@198 +00000000 +@199 +00000000 +@19a +00000000 +@19b +00000000 +@19c +00000000 +@19d +00000000 +@19e +00000000 +@19f +00000000 +@1a0 +00000000 +@1a1 +00000000 +@1a2 +00000000 +@1a3 +00000000 +@1a4 +00000000 +@1a5 +00000000 +@1a6 +00000000 +@1a7 +00000000 +@1a8 +00000000 +@1a9 +00000000 +@1aa +00000000 +@1ab +00000000 +@1ac +00000000 +@1ad +00000000 +@1ae +00000000 +@1af +00000000 +@1b0 +00000000 +@1b1 +00000000 +@1b2 +00000000 +@1b3 +00000000 +@1b4 +00000000 +@1b5 +00000000 +@1b6 +00000000 +@1b7 +00000000 +@1b8 +00000000 +@1b9 +00000000 +@1ba +00000000 +@1bb +00000000 +@1bc +00000000 +@1bd +00000000 +@1be +00000000 +@1bf +00000000 +@1c0 +00000000 +@1c1 +00000000 +@1c2 +00000000 +@1c3 +00000000 +@1c4 +00000000 +@1c5 +00000000 +@1c6 +00000000 +@1c7 +00000000 +@1c8 +00000000 +@1c9 +00000000 +@1ca +00000000 +@1cb +00000000 +@1cc +00000000 +@1cd +00000000 +@1ce +00000000 +@1cf +00000000 +@1d0 +00000000 +@1d1 +00000000 +@1d2 +00000000 +@1d3 +00000000 +@1d4 +00000000 +@1d5 +00000000 +@1d6 +00000000 +@1d7 +00000000 +@1d8 +00000000 +@1d9 +00000000 +@1da +00000000 +@1db +00000000 +@1dc +00000000 +@1dd +00000000 +@1de +00000000 +@1df +00000000 +@1e0 +00000000 +@1e1 +00000000 +@1e2 +00000000 +@1e3 +00000000 +@1e4 +00000000 +@1e5 +00000000 +@1e6 +00000000 +@1e7 +00000000 +@1e8 +00000000 +@1e9 +00000000 +@1ea +00000000 +@1eb +00000000 +@1ec +00000000 +@1ed +00000000 +@1ee +00000000 +@1ef +00000000 +@1f0 +00000000 +@1f1 +00000000 +@1f2 +00000000 +@1f3 +00000000 +@1f4 +00000000 +@1f5 +00000000 +@1f6 +00000000 +@1f7 +00000000 +@1f8 +00000000 +@1f9 +00000000 +@1fa +00000000 +@1fb +00000000 +@1fc +00000000 +@1fd +00000000 +@1fe +00000000 +@1ff +00000000 +@200 +00000000 +@201 +00000000 +@202 +00000000 +@203 +00000000 +@204 +00000000 +@205 +00000000 +@206 +00000000 +@207 +00000000 +@208 +00000000 +@209 +00000000 +@20a +00000000 +@20b +00000000 +@20c +00000000 +@20d +00000000 +@20e +00000000 +@20f +00000000 +@210 +00000000 +@211 +00000000 +@212 +00000000 +@213 +00000000 +@214 +00000000 +@215 +00000000 +@216 +00000000 +@217 +00000000 +@218 +00000000 +@219 +00000000 +@21a +00000000 +@21b +00000000 +@21c +00000000 +@21d +00000000 +@21e +00000000 +@21f +00000000 +@220 +00000000 +@221 +00000000 +@222 +00000000 +@223 +00000000 +@224 +00000000 +@225 +00000000 +@226 +00000000 +@227 +00000000 +@228 +00000000 +@229 +00000000 +@22a +00000000 +@22b +00000000 +@22c +00000000 +@22d +00000000 +@22e +00000000 +@22f +00000000 +@230 +00000000 +@231 +00000000 +@232 +00000000 +@233 +00000000 +@234 +00000000 +@235 +00000000 +@236 +00000000 +@237 +00000000 +@238 +00000000 +@239 +00000000 +@23a +00000000 +@23b +00000000 +@23c +00000000 +@23d +00000000 +@23e +00000000 +@23f +00000000 +@240 +00000000 +@241 +00000000 +@242 +00000000 +@243 +00000000 +@244 +00000000 +@245 +00000000 +@246 +00000000 +@247 +00000000 +@248 +00000000 +@249 +00000000 +@24a +00000000 +@24b +00000000 +@24c +00000000 +@24d +00000000 +@24e +00000000 +@24f +00000000 +@250 +00000000 +@251 +00000000 +@252 +00000000 +@253 +00000000 +@254 +00000000 +@255 +00000000 +@256 +00000000 +@257 +00000000 +@258 +00000000 +@259 +00000000 +@25a +00000000 +@25b +00000000 +@25c +00000000 +@25d +00000000 +@25e +00000000 +@25f +00000000 +@260 +00000000 +@261 +00000000 +@262 +00000000 +@263 +00000000 +@264 +00000000 +@265 +00000000 +@266 +00000000 +@267 +00000000 +@268 +00000000 +@269 +00000000 +@26a +00000000 +@26b +00000000 +@26c +00000000 +@26d +00000000 +@26e +00000000 +@26f +00000000 +@270 +00000000 +@271 +00000000 +@272 +00000000 +@273 +00000000 +@274 +00000000 +@275 +00000000 +@276 +00000000 +@277 +00000000 +@278 +00000000 +@279 +00000000 +@27a +00000000 +@27b +00000000 +@27c +00000000 +@27d +00000000 +@27e +00000000 +@27f +00000000 +@280 +00000000 +@281 +00000000 +@282 +00000000 +@283 +00000000 +@284 +00000000 +@285 +00000000 +@286 +00000000 +@287 +00000000 +@288 +00000000 +@289 +00000000 +@28a +00000000 +@28b +00000000 +@28c +00000000 +@28d +00000000 +@28e +00000000 +@28f +00000000 +@290 +00000000 +@291 +00000000 +@292 +00000000 +@293 +00000000 +@294 +00000000 +@295 +00000000 +@296 +00000000 +@297 +00000000 +@298 +00000000 +@299 +00000000 +@29a +00000000 +@29b +00000000 +@29c +00000000 +@29d +00000000 +@29e +00000000 +@29f +00000000 +@2a0 +00000000 +@2a1 +00000000 +@2a2 +00000000 +@2a3 +00000000 +@2a4 +00000000 +@2a5 +00000000 +@2a6 +00000000 +@2a7 +00000000 +@2a8 +00000000 +@2a9 +00000000 +@2aa +00000000 +@2ab +00000000 +@2ac +00000000 +@2ad +00000000 +@2ae +00000000 +@2af +00000000 +@2b0 +00000000 +@2b1 +00000000 +@2b2 +00000000 +@2b3 +00000000 +@2b4 +00000000 +@2b5 +00000000 +@2b6 +00000000 +@2b7 +00000000 +@2b8 +00000000 +@2b9 +00000000 +@2ba +00000000 +@2bb +00000000 +@2bc +00000000 +@2bd +00000000 +@2be +00000000 +@2bf +00000000 +@2c0 +00000000 +@2c1 +00000000 +@2c2 +00000000 +@2c3 +00000000 +@2c4 +00000000 +@2c5 +00000000 +@2c6 +00000000 +@2c7 +00000000 +@2c8 +00000000 +@2c9 +00000000 +@2ca +00000000 +@2cb +00000000 +@2cc +00000000 +@2cd +00000000 +@2ce +00000000 +@2cf +00000000 +@2d0 +00000000 +@2d1 +00000000 +@2d2 +00000000 +@2d3 +00000000 +@2d4 +00000000 +@2d5 +00000000 +@2d6 +00000000 +@2d7 +00000000 +@2d8 +00000000 +@2d9 +00000000 +@2da +00000000 +@2db +00000000 +@2dc +00000000 +@2dd +00000000 +@2de +00000000 +@2df +00000000 +@2e0 +00000000 +@2e1 +00000000 +@2e2 +00000000 +@2e3 +00000000 +@2e4 +00000000 +@2e5 +00000000 +@2e6 +00000000 +@2e7 +00000000 +@2e8 +00000000 +@2e9 +00000000 +@2ea +00000000 +@2eb +00000000 +@2ec +00000000 +@2ed +00000000 +@2ee +00000000 +@2ef +00000000 +@2f0 +00000000 +@2f1 +00000000 +@2f2 +00000000 +@2f3 +00000000 +@2f4 +00000000 +@2f5 +00000000 +@2f6 +00000000 +@2f7 +00000000 +@2f8 +00000000 +@2f9 +00000000 +@2fa +00000000 +@2fb +00000000 +@2fc +00000000 +@2fd +00000000 +@2fe +00000000 +@2ff +00000000 +@300 +00000000 +@301 +00000000 +@302 +00000000 +@303 +00000000 +@304 +00000000 +@305 +00000000 +@306 +00000000 +@307 +00000000 +@308 +00000000 +@309 +00000000 +@30a +00000000 +@30b +00000000 +@30c +00000000 +@30d +00000000 +@30e +00000000 +@30f +00000000 +@310 +00000000 +@311 +00000000 +@312 +00000000 +@313 +00000000 +@314 +00000000 +@315 +00000000 +@316 +00000000 +@317 +00000000 +@318 +00000000 +@319 +00000000 +@31a +00000000 +@31b +00000000 +@31c +00000000 +@31d +00000000 +@31e +00000000 +@31f +00000000 +@320 +00000000 +@321 +00000000 +@322 +00000000 +@323 +00000000 +@324 +00000000 +@325 +00000000 +@326 +00000000 +@327 +00000000 +@328 +00000000 +@329 +00000000 +@32a +00000000 +@32b +00000000 +@32c +00000000 +@32d +00000000 +@32e +00000000 +@32f +00000000 +@330 +00000000 +@331 +00000000 +@332 +00000000 +@333 +00000000 +@334 +00000000 +@335 +00000000 +@336 +00000000 +@337 +00000000 +@338 +00000000 +@339 +00000000 +@33a +00000000 +@33b +00000000 +@33c +00000000 +@33d +00000000 +@33e +00000000 +@33f +00000000 +@340 +00000000 +@341 +00000000 +@342 +00000000 +@343 +00000000 +@344 +00000000 +@345 +00000000 +@346 +00000000 +@347 +00000000 +@348 +00000000 +@349 +00000000 +@34a +00000000 +@34b +00000000 +@34c +00000000 +@34d +00000000 +@34e +00000000 +@34f +00000000 +@350 +00000000 +@351 +00000000 +@352 +00000000 +@353 +00000000 +@354 +00000000 +@355 +00000000 +@356 +00000000 +@357 +00000000 +@358 +00000000 +@359 +00000000 +@35a +00000000 +@35b +00000000 +@35c +00000000 +@35d +00000000 +@35e +00000000 +@35f +00000000 +@360 +00000000 +@361 +00000000 +@362 +00000000 +@363 +00000000 +@364 +00000000 +@365 +00000000 +@366 +00000000 +@367 +00000000 +@368 +00000000 +@369 +00000000 +@36a +00000000 +@36b +00000000 +@36c +00000000 +@36d +00000000 +@36e +00000000 +@36f +00000000 +@370 +00000000 +@371 +00000000 +@372 +00000000 +@373 +00000000 +@374 +00000000 +@375 +00000000 +@376 +00000000 +@377 +00000000 +@378 +00000000 +@379 +00000000 +@37a +00000000 +@37b +00000000 +@37c +00000000 +@37d +00000000 +@37e +00000000 +@37f +00000000 +@380 +00000000 +@381 +00000000 +@382 +00000000 +@383 +00000000 +@384 +00000000 +@385 +00000000 +@386 +00000000 +@387 +00000000 +@388 +00000000 +@389 +00000000 +@38a +00000000 +@38b +00000000 +@38c +00000000 +@38d +00000000 +@38e +00000000 +@38f +00000000 +@390 +00000000 +@391 +00000000 +@392 +00000000 +@393 +00000000 +@394 +00000000 +@395 +00000000 +@396 +00000000 +@397 +00000000 +@398 +00000000 +@399 +00000000 +@39a +00000000 +@39b +00000000 +@39c +00000000 +@39d +00000000 +@39e +00000000 +@39f +00000000 +@3a0 +00000000 +@3a1 +00000000 +@3a2 +00000000 +@3a3 +00000000 +@3a4 +00000000 +@3a5 +00000000 +@3a6 +00000000 +@3a7 +00000000 +@3a8 +00000000 +@3a9 +00000000 +@3aa +00000000 +@3ab +00000000 +@3ac +00000000 +@3ad +00000000 +@3ae +00000000 +@3af +00000000 +@3b0 +00000000 +@3b1 +00000000 +@3b2 +00000000 +@3b3 +00000000 +@3b4 +00000000 +@3b5 +00000000 +@3b6 +00000000 +@3b7 +00000000 +@3b8 +00000000 +@3b9 +00000000 +@3ba +00000000 +@3bb +00000000 +@3bc +00000000 +@3bd +00000000 +@3be +00000000 +@3bf +00000000 +@3c0 +00000000 +@3c1 +00000000 +@3c2 +00000000 +@3c3 +00000000 +@3c4 +00000000 +@3c5 +00000000 +@3c6 +00000000 +@3c7 +00000000 +@3c8 +00000000 +@3c9 +00000000 +@3ca +00000000 +@3cb +00000000 +@3cc +00000000 +@3cd +00000000 +@3ce +00000000 +@3cf +00000000 +@3d0 +00000000 +@3d1 +00000000 +@3d2 +00000000 +@3d3 +00000000 +@3d4 +00000000 +@3d5 +00000000 +@3d6 +00000000 +@3d7 +00000000 +@3d8 +00000000 +@3d9 +00000000 +@3da +00000000 +@3db +00000000 +@3dc +00000000 +@3dd +00000000 +@3de +00000000 +@3df +00000000 +@3e0 +00000000 +@3e1 +00000000 +@3e2 +00000000 +@3e3 +00000000 +@3e4 +00000000 +@3e5 +00000000 +@3e6 +00000000 +@3e7 +00000000 +@3e8 +00000000 +@3e9 +00000000 +@3ea +00000000 +@3eb +00000000 +@3ec +00000000 +@3ed +00000000 +@3ee +00000000 +@3ef +00000000 +@3f0 +00000000 +@3f1 +00000000 +@3f2 +00000000 +@3f3 +00000000 +@3f4 +00000000 +@3f5 +00000000 +@3f6 +00000000 +@3f7 +00000000 +@3f8 +00000000 +@3f9 +00000000 +@3fa +00000000 +@3fb +00000000 +@3fc +00000000 +@3fd +00000000 +@3fe +00000000 +@3ff +00000000 +@400 +6576654e +@401 +6f672072 +@402 +20616e6e +@403 +65766967 +@404 +756f7920 +@405 +7e707520 +@406 +76654e20 +@407 +67207265 +@408 +616e6e6f +@409 +74656c20 +@40a +756f7920 +@40b +776f6420 +@40c +200a7e6e +@40d +4e202020 +@40e +72657665 +@40f +6e6f6720 +@410 +7220616e +@411 +61206e75 +@412 +6e756f72 +@413 +6e612064 +@414 +64207e64 +@415 +72657365 +@416 +6f792074 +@417 +000a7e75 +@418 +00000013 +@419 +00000013 +@41a +00000013 diff --git a/mini-yatcpu/verilog/verilator/sim_main.cpp b/mini-yatcpu/verilog/verilator/sim_main.cpp new file mode 100644 index 0000000..e2713fc --- /dev/null +++ b/mini-yatcpu/verilog/verilator/sim_main.cpp @@ -0,0 +1,230 @@ +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "VTop.h" // From Verilating "top.v" + +class Memory { + std::vector memory; + + public: + Memory(size_t size) : memory(size, 0) {} + uint32_t read(size_t address) { + address = address / 4; + if (address >= memory.size()) { + printf("invalid read address 0x%08x\n", address * 4); + return 0; + } + return memory[address]; + } + + void write(size_t address, uint32_t value, bool write_strobe[4]) { + address = address / 4; + uint32_t write_mask = 0; + if (write_strobe[0]) write_mask |= 0x000000FF; + if (write_strobe[1]) write_mask |= 0x0000FF00; + if (write_strobe[2]) write_mask |= 0x00FF0000; + if (write_strobe[3]) write_mask |= 0xFF000000; + if (address >= memory.size()) { + printf("invalid write address 0x%08x\n", address * 4); + return; + } + memory[address] = (memory[address] & ~write_mask) | (value & write_mask); + } + + void load_binary(std::string const& filename, size_t load_address = 0x1000) { + std::ifstream file(filename, std::ios::binary); + if (!file) { + throw std::runtime_error("Could not open file " + filename); + } + file.seekg(0, std::ios::end); + size_t size = file.tellg(); + if (load_address + size > memory.size() * 4) { + throw std::runtime_error("File " + filename + " is too large (File is " + + std::to_string(size) + " bytes. Memory is " + + std::to_string(memory.size() * 4 - load_address) + " bytes.)"); + } + file.seekg(0, std::ios::beg); + for (int i = 0; i < size / 4; ++i) { + file.read(reinterpret_cast(&memory[i + load_address / 4]), + sizeof(uint32_t)); + } + } +}; + +class VCDTracer { + VerilatedVcdC* tfp = nullptr; + + public: + void enable(std::string const& filename, VTop& top) { + Verilated::traceEverOn(true); + tfp = new VerilatedVcdC; + top.trace(tfp, 99); + tfp->open(filename.c_str()); + tfp->set_time_resolution("1ps"); + tfp->set_time_unit("1ns"); + if (!tfp->isOpen()) { + throw std::runtime_error("Failed to open VCD dump file " + filename); + } + } + + void dump(vluint64_t time) { + if (tfp) { + tfp->dump(time); + } + } + + ~VCDTracer() { + if (tfp) { + tfp->close(); + delete tfp; + } + } +}; + +uint32_t parse_number(std::string const& str) { + if (str.size() > 2) { + auto&& prefix = str.substr(0, 2); + if (prefix == "0x" || prefix == "0X") { + return std::stoul(str.substr(2), nullptr, 16); + } + } + return std::stoul(str); +} + +class Simulator { + vluint64_t main_time = 0; + vluint64_t max_sim_time = 10000; + uint32_t halt_address = 0; + size_t memory_words = 1024 * 1024; // 4MB + bool dump_vcd = false; + std::unique_ptr top; + std::unique_ptr vcd_tracer; + std::unique_ptr memory; + bool dump_signature = false; + unsigned long signature_begin, signature_end; + std::string signature_filename; + std::string instruction_filename; + + public: + void parse_args(std::vector const& args) { + if (auto it = std::find(args.begin(), args.end(), "-halt"); + it != args.end()) { + halt_address = parse_number(*(it + 1)); + } + + if (auto it = std::find(args.begin(), args.end(), "-memory"); + it != args.end()) { + memory_words = std::stoul(*(it + 1)); + } + + if (auto it = std::find(args.begin(), args.end(), "-time"); + it != args.end()) { + max_sim_time = std::stoul(*(it + 1)); + } + + if (auto it = std::find(args.begin(), args.end(), "-vcd"); + it != args.end()) { + vcd_tracer->enable(*(it + 1), *top); + } + + if (auto it = std::find(args.begin(), args.end(), "-signature"); + it != args.end()) { + dump_signature = true; + signature_begin = parse_number(*(it + 1)); + signature_end = parse_number(*(it + 2)); + signature_filename = *(it + 3); + } + + if (auto it = std::find(args.begin(), args.end(), "-instruction"); + it != args.end()) { + instruction_filename = *(it + 1); + } + } + + Simulator(std::vector const& args) + : top(std::make_unique()), + vcd_tracer(std::make_unique()) { + parse_args(args); + memory = std::make_unique(memory_words); + if (!instruction_filename.empty()) { + memory->load_binary(instruction_filename); + } + } + + void run() { + top->reset = 1; + top->clock = 0; + top->io_mem_slave_read_valid = true; + top->eval(); + vcd_tracer->dump(main_time); + uint32_t memory_read_word = 0; + bool memory_write_strobe[4] = {false}; + bool uart_debounce = false; + while (main_time < max_sim_time && !Verilated::gotFinish()) { + ++main_time; + if (main_time > 2) { + top->reset = 0; + } + top->io_mem_slave_read_data = memory_read_word; + top->clock = !top->clock; + top->eval(); + if (top->io_uart_slave_write) { + if (uart_debounce && top->clock) { + std::cout << (char)top->io_uart_slave_write_data << std::flush; + } + if (!uart_debounce && top->clock) { + uart_debounce = true; + } + } else { + uart_debounce = false; + } + if (top->io_mem_slave_read) { + memory_read_word = memory->read(top->io_mem_slave_address); + } + if (top->io_mem_slave_write) { + memory_write_strobe[0] = top->io_mem_slave_write_strobe_0; + memory_write_strobe[1] = top->io_mem_slave_write_strobe_1; + memory_write_strobe[2] = top->io_mem_slave_write_strobe_2; + memory_write_strobe[3] = top->io_mem_slave_write_strobe_3; + memory->write(top->io_mem_slave_address, top->io_mem_slave_write_data, + memory_write_strobe); + } + vcd_tracer->dump(main_time); + if (halt_address) { + if (memory->read(halt_address) == 0xBABECAFE) { + break; + } + } + } + + if (dump_signature) { + char data[9] = {0}; + std::ofstream signature_file(signature_filename); + for (size_t addr = signature_begin; addr < signature_end; addr += 4) { + snprintf(data, 9, "%08x", memory->read(addr)); + signature_file << data << std::endl; + } + } + } + + ~Simulator() { + if (top) { + top->final(); + } + } +}; + +int main(int argc, char** argv) { + Verilated::commandArgs(argc, argv); + std::vector args(argv, argv + argc); + Simulator simulator(args); + simulator.run(); + return 0; +} diff --git a/mini-yatcpu/verilog/z710/Top.anno.json b/mini-yatcpu/verilog/z710/Top.anno.json new file mode 100644 index 0000000..1968819 --- /dev/null +++ b/mini-yatcpu/verilog/z710/Top.anno.json @@ -0,0 +1,498 @@ +[ + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|AXI4LiteSlave", + "duplicate":"~Top|Top/uart:Uart/slave:AXI4LiteSlave", + "index":0.0 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/if2id:IF2ID/instruction:PipelineRegister", + "index":0.11842105263157894 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_1", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/if2id:IF2ID/instruction_address:PipelineRegister_1", + "index":0.13157894736842105 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_2", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/if2id:IF2ID/interrupt_flag:PipelineRegister_2", + "index":0.14473684210526316 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_3", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/instruction:PipelineRegister", + "index":0.18421052631578946 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_4", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/instruction_address:PipelineRegister_1", + "index":0.19736842105263158 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_5", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/regs_write_enable:PipelineRegister_5", + "index":0.21052631578947367 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_6", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/regs_write_address:PipelineRegister_6", + "index":0.2236842105263158 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_7", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/regs_write_source:PipelineRegister_7", + "index":0.23684210526315788 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_8", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/reg1_data:PipelineRegister_2", + "index":0.25 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_9", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/reg2_data:PipelineRegister_2", + "index":0.2631578947368421 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_10", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/immediate:PipelineRegister_2", + "index":0.27631578947368424 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_11", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/aluop1_source:PipelineRegister_5", + "index":0.2894736842105263 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_12", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/aluop2_source:PipelineRegister_5", + "index":0.3026315789473684 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_13", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/csr_write_enable:PipelineRegister_5", + "index":0.3157894736842105 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_15", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/memory_read_enable:PipelineRegister_5", + "index":0.34210526315789475 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_16", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/memory_write_enable:PipelineRegister_5", + "index":0.35526315789473684 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_17", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/csr_read_data:PipelineRegister_2", + "index":0.3684210526315789 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_18", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/regs_write_enable:PipelineRegister_5", + "index":0.4342105263157895 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_19", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/regs_write_source:PipelineRegister_7", + "index":0.4473684210526316 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_20", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/regs_write_address:PipelineRegister_6", + "index":0.4605263157894737 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_21", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/instruction_address:PipelineRegister_2", + "index":0.47368421052631576 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_22", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/instruction:PipelineRegister_2", + "index":0.4868421052631579 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_23", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/reg1_data:PipelineRegister_2", + "index":0.5 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_24", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/reg2_data:PipelineRegister_2", + "index":0.5131578947368421 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_25", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/alu_result:PipelineRegister_2", + "index":0.5263157894736842 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_26", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/memory_read_enable:PipelineRegister_5", + "index":0.5394736842105263 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_27", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/memory_write_enable:PipelineRegister_5", + "index":0.5526315789473685 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_28", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/csr_read_data:PipelineRegister_2", + "index":0.5657894736842105 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_29", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/alu_result:PipelineRegister_2", + "index":0.6052631578947368 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_30", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/memory_read_data:PipelineRegister_2", + "index":0.618421052631579 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_31", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/regs_write_enable:PipelineRegister_5", + "index":0.631578947368421 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_32", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/regs_write_source:PipelineRegister_7", + "index":0.6447368421052632 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_33", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/regs_write_address:PipelineRegister_6", + "index":0.6578947368421053 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_34", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/instruction_address:PipelineRegister_2", + "index":0.6710526315789473 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|PipelineRegister_35", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/csr_read_data:PipelineRegister_2", + "index":0.6842105263157895 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|AXI4LiteMaster", + "duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/axi4_master:AXI4LiteMaster", + "index":0.7631578947368421 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|AXI4LiteSlave_1", + "duplicate":"~Top|Top/mem:Memory/slave:AXI4LiteSlave_1", + "index":0.8289473684210527 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|AXI4LiteSlave_2", + "duplicate":"~Top|Top/timer:Timer/slave:AXI4LiteSlave", + "index":0.8552631578947368 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|AXI4LiteSlave_3", + "duplicate":"~Top|Top/dummy:DummySlave/slave:AXI4LiteSlave_1", + "index":0.881578947368421 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|AXI4LiteMaster_1", + "duplicate":"~Top|Top/bus_switch:BusSwitch/dummy:DummyMaster/master:AXI4LiteMaster", + "index":0.9210526315789473 + }, + { + "class":"firrtl.transforms.DedupedResult", + "original":"~Top|AXI4LiteMaster_2", + "duplicate":"~Top|Top/rom_loader:ROMLoader/master:AXI4LiteMaster", + "index":0.9736842105263158 + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"Top.AXI4LiteMaster.state", + "enumTypeName":"bus.AXI4LiteStates" + }, + { + "class":"firrtl.annotations.MemorySynthInit$" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"Top.AXI4LiteSlave_1.state", + "enumTypeName":"bus.AXI4LiteStates" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"Top.AXI4LiteSlave.state", + "enumTypeName":"bus.AXI4LiteStates" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation", + "typeName":"riscv.core.fivestage.MEMAccessState", + "definition":{ + "if_address_translate":1, + "if_access":4, + "idle":0, + "mem_address_translate":2, + "mem_access":3 + } + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"Top.CPU.mem_access_state", + "enumTypeName":"riscv.core.fivestage.MEMAccessState" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation", + "typeName":"riscv.core.fivestage.BUSGranted", + "definition":{ + "mmu_if_granted":4, + "if_granted":1, + "mmu_mem_granted":3, + "mem_granted":2, + "idle":0 + } + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"Top.CPU.bus_granted", + "enumTypeName":"riscv.core.fivestage.BUSGranted" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation", + "typeName":"riscv.core.fivestage.MMUStates", + "definition":{ + "checkpte1":2, + "gotPhyicalAddress":6, + "setADbit":5, + "idle":0, + "checkpte0":4, + "level1":1, + "level0":3 + } + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"Top.MMU.state", + "enumTypeName":"riscv.core.fivestage.MMUStates" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation", + "typeName":"riscv.core.fivestage.MemoryAccessStates", + "definition":{ + "Idle":0, + "Read":1, + "Write":2, + "ReadWrite":3 + } + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"Top.MemoryAccess.mem_access_state", + "enumTypeName":"riscv.core.fivestage.MemoryAccessStates" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"Top.ALUControl._io_alu_funct_T_33", + "enumTypeName":"riscv.core.fivestage.ALUFunctions" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"Top.ALUControl._io_alu_funct_T_31", + "enumTypeName":"riscv.core.fivestage.ALUFunctions" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"Top.ALUControl._io_alu_funct_T_29", + "enumTypeName":"riscv.core.fivestage.ALUFunctions" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"Top.ALUControl._io_alu_funct_T_27", + "enumTypeName":"riscv.core.fivestage.ALUFunctions" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"Top.ALUControl._io_alu_funct_T_25", + "enumTypeName":"riscv.core.fivestage.ALUFunctions" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"Top.ALUControl._io_alu_funct_T_23", + "enumTypeName":"riscv.core.fivestage.ALUFunctions" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"Top.ALUControl._io_alu_funct_T_21", + "enumTypeName":"riscv.core.fivestage.ALUFunctions" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"Top.ALUControl._io_alu_funct_T_17", + "enumTypeName":"riscv.core.fivestage.ALUFunctions" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"Top.ALUControl._io_alu_funct_T_15", + "enumTypeName":"riscv.core.fivestage.ALUFunctions" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"Top.ALUControl._io_alu_funct_T_13", + "enumTypeName":"riscv.core.fivestage.ALUFunctions" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"Top.ALUControl._io_alu_funct_T_11", + "enumTypeName":"riscv.core.fivestage.ALUFunctions" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"Top.ALUControl._io_alu_funct_T_9", + "enumTypeName":"riscv.core.fivestage.ALUFunctions" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"Top.ALUControl._io_alu_funct_T_7", + "enumTypeName":"riscv.core.fivestage.ALUFunctions" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"Top.ALUControl._io_alu_funct_T_5", + "enumTypeName":"riscv.core.fivestage.ALUFunctions" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"Top.ALUControl._io_alu_funct_T_3", + "enumTypeName":"riscv.core.fivestage.ALUFunctions" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"Top.ALUControl._io_alu_funct_T_1", + "enumTypeName":"riscv.core.fivestage.ALUFunctions" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"Top.ALUControl.io_alu_funct", + "enumTypeName":"riscv.core.fivestage.ALUFunctions" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation", + "typeName":"riscv.core.fivestage.ALUFunctions", + "definition":{ + "sll":3, + "sra":9, + "or":6, + "xor":5, + "slt":4, + "sub":2, + "add":1, + "sltu":10, + "and":7, + "srl":8, + "zero":0 + } + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"Top.ALU.io_func", + "enumTypeName":"riscv.core.fivestage.ALUFunctions" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation", + "typeName":"riscv.core.fivestage.IFAccessStates", + "definition":{ + "idle":0, + "read":1 + } + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"Top.InstructionFetch.state", + "enumTypeName":"riscv.core.fivestage.IFAccessStates" + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation", + "typeName":"bus.AXI4LiteStates", + "definition":{ + "ReadData":2, + "WriteAddr":3, + "WriteResp":5, + "Idle":0, + "WriteData":4, + "ReadAddr":1 + } + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation", + "typeName":"board.z710.BootStates", + "definition":{ + "Init":0, + "Loading":1, + "BusWait":2, + "Finished":3 + } + }, + { + "class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation", + "target":"Top.Top.boot_state", + "enumTypeName":"board.z710.BootStates" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"verilog/z710" + }, + { + "class":"firrtl.annotations.MemoryFileInlineAnnotation", + "target":"~Top|InstructionROM>mem", + "filename":"/workspaces/2023-fall-yatcpu-repo/mini-yatcpu/verilog/say_goodbye.asmbin.txt", + "hexOrBinary":"h" + } +] \ No newline at end of file diff --git a/mini-yatcpu/verilog/z710/Top.fir b/mini-yatcpu/verilog/z710/Top.fir new file mode 100644 index 0000000..85805af --- /dev/null +++ b/mini-yatcpu/verilog/z710/Top.fir @@ -0,0 +1,4250 @@ +FIRRTL version 1.2.0 +circuit Top : + module AXI4LiteSlave : + input clock : Clock + input reset : Reset + output io : { flip channels : { write_address_channel : { AWVALID : UInt<1>, flip AWREADY : UInt<1>, AWADDR : UInt<8>, AWPROT : UInt<3>}, write_data_channel : { WVALID : UInt<1>, flip WREADY : UInt<1>, WDATA : UInt<32>, WSTRB : UInt<4>}, write_response_channel : { flip BVALID : UInt<1>, BREADY : UInt<1>, flip BRESP : UInt<2>}, read_address_channel : { ARVALID : UInt<1>, flip ARREADY : UInt<1>, ARADDR : UInt<8>, ARPROT : UInt<3>}, read_data_channel : { flip RVALID : UInt<1>, RREADY : UInt<1>, flip RDATA : UInt<32>, flip RRESP : UInt<2>}}, bundle : { read : UInt<1>, write : UInt<1>, flip read_data : UInt<32>, flip read_valid : UInt<1>, write_data : UInt<32>, write_strobe : UInt<1>[4], address : UInt<8>}} @[src/main/scala/bus/AXI4Lite.scala 121:14] + + reg state : UInt<3>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 125:22] + reg addr : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[src/main/scala/bus/AXI4Lite.scala 126:21] + io.bundle.address <= addr @[src/main/scala/bus/AXI4Lite.scala 127:21] + reg read : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 128:21] + io.bundle.read <= read @[src/main/scala/bus/AXI4Lite.scala 129:18] + reg write : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 130:22] + io.bundle.write <= write @[src/main/scala/bus/AXI4Lite.scala 131:19] + reg write_data : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[src/main/scala/bus/AXI4Lite.scala 132:27] + io.bundle.write_data <= write_data @[src/main/scala/bus/AXI4Lite.scala 133:24] + wire _write_strobe_WIRE : UInt<1>[4] @[src/main/scala/bus/AXI4Lite.scala 134:37] + _write_strobe_WIRE[0] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 134:37] + _write_strobe_WIRE[1] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 134:37] + _write_strobe_WIRE[2] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 134:37] + _write_strobe_WIRE[3] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 134:37] + reg write_strobe : UInt<1>[4], clock with : + reset => (reset, _write_strobe_WIRE) @[src/main/scala/bus/AXI4Lite.scala 134:29] + io.bundle.write_strobe <= write_strobe @[src/main/scala/bus/AXI4Lite.scala 135:26] + reg ARREADY : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 137:24] + io.channels.read_address_channel.ARREADY <= ARREADY @[src/main/scala/bus/AXI4Lite.scala 138:44] + reg RVALID : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 139:23] + io.channels.read_data_channel.RVALID <= RVALID @[src/main/scala/bus/AXI4Lite.scala 140:40] + reg RRESP : UInt<2>, clock with : + reset => (reset, UInt<2>("h0")) @[src/main/scala/bus/AXI4Lite.scala 141:22] + io.channels.read_data_channel.RRESP <= RRESP @[src/main/scala/bus/AXI4Lite.scala 142:39] + io.channels.read_data_channel.RDATA <= io.bundle.read_data @[src/main/scala/bus/AXI4Lite.scala 144:39] + reg AWREADY : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 146:24] + io.channels.write_address_channel.AWREADY <= AWREADY @[src/main/scala/bus/AXI4Lite.scala 147:45] + reg WREADY : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 148:23] + io.channels.write_data_channel.WREADY <= WREADY @[src/main/scala/bus/AXI4Lite.scala 149:41] + write_data <= io.channels.write_data_channel.WDATA @[src/main/scala/bus/AXI4Lite.scala 150:14] + reg BVALID : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 151:23] + io.channels.write_response_channel.BVALID <= BVALID @[src/main/scala/bus/AXI4Lite.scala 152:45] + wire BRESP : UInt<2> @[src/main/scala/bus/AXI4Lite.scala 153:23] + BRESP <= UInt<2>("h0") @[src/main/scala/bus/AXI4Lite.scala 153:23] + io.channels.write_response_channel.BRESP <= BRESP @[src/main/scala/bus/AXI4Lite.scala 154:44] + node _T = asUInt(UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_1 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_2 = eq(_T, _T_1) @[src/main/scala/bus/AXI4Lite.scala 156:17] + when _T_2 : @[src/main/scala/bus/AXI4Lite.scala 156:17] + read <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 158:12] + write <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 159:13] + RVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 160:14] + BVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 161:14] + when io.channels.write_address_channel.AWVALID : @[src/main/scala/bus/AXI4Lite.scala 162:55] + state <= UInt<2>("h3") @[src/main/scala/bus/AXI4Lite.scala 163:15] + else : + when io.channels.read_address_channel.ARVALID : @[src/main/scala/bus/AXI4Lite.scala 164:60] + state <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 165:15] + else : + node _T_3 = asUInt(UInt<1>("h1")) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_4 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_5 = eq(_T_3, _T_4) @[src/main/scala/bus/AXI4Lite.scala 156:17] + when _T_5 : @[src/main/scala/bus/AXI4Lite.scala 156:17] + ARREADY <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 169:15] + node _T_6 = and(io.channels.read_address_channel.ARVALID, ARREADY) @[src/main/scala/bus/AXI4Lite.scala 170:53] + when _T_6 : @[src/main/scala/bus/AXI4Lite.scala 170:65] + state <= UInt<2>("h2") @[src/main/scala/bus/AXI4Lite.scala 171:15] + addr <= io.channels.read_address_channel.ARADDR @[src/main/scala/bus/AXI4Lite.scala 172:14] + read <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 173:14] + ARREADY <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 174:17] + else : + node _T_7 = asUInt(UInt<2>("h2")) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_8 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_9 = eq(_T_7, _T_8) @[src/main/scala/bus/AXI4Lite.scala 156:17] + when _T_9 : @[src/main/scala/bus/AXI4Lite.scala 156:17] + RVALID <= io.bundle.read_valid @[src/main/scala/bus/AXI4Lite.scala 178:14] + node _T_10 = and(io.channels.read_data_channel.RREADY, RVALID) @[src/main/scala/bus/AXI4Lite.scala 179:49] + when _T_10 : @[src/main/scala/bus/AXI4Lite.scala 179:60] + state <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 180:15] + RVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 181:16] + else : + node _T_11 = asUInt(UInt<2>("h3")) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_12 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_13 = eq(_T_11, _T_12) @[src/main/scala/bus/AXI4Lite.scala 156:17] + when _T_13 : @[src/main/scala/bus/AXI4Lite.scala 156:17] + AWREADY <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 185:15] + node _T_14 = and(io.channels.write_address_channel.AWVALID, AWREADY) @[src/main/scala/bus/AXI4Lite.scala 186:54] + when _T_14 : @[src/main/scala/bus/AXI4Lite.scala 186:66] + addr <= io.channels.write_address_channel.AWADDR @[src/main/scala/bus/AXI4Lite.scala 187:14] + state <= UInt<3>("h4") @[src/main/scala/bus/AXI4Lite.scala 188:15] + AWREADY <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 189:17] + else : + node _T_15 = asUInt(UInt<3>("h4")) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_16 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_17 = eq(_T_15, _T_16) @[src/main/scala/bus/AXI4Lite.scala 156:17] + when _T_17 : @[src/main/scala/bus/AXI4Lite.scala 156:17] + WREADY <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 193:14] + node _T_18 = and(io.channels.write_data_channel.WVALID, WREADY) @[src/main/scala/bus/AXI4Lite.scala 194:50] + when _T_18 : @[src/main/scala/bus/AXI4Lite.scala 194:61] + state <= UInt<3>("h5") @[src/main/scala/bus/AXI4Lite.scala 195:15] + write_data <= io.channels.write_data_channel.WDATA @[src/main/scala/bus/AXI4Lite.scala 196:20] + node _T_19 = bits(io.channels.write_data_channel.WSTRB, 0, 0) @[src/main/scala/bus/AXI4Lite.scala 197:62] + node _T_20 = bits(io.channels.write_data_channel.WSTRB, 1, 1) @[src/main/scala/bus/AXI4Lite.scala 197:62] + node _T_21 = bits(io.channels.write_data_channel.WSTRB, 2, 2) @[src/main/scala/bus/AXI4Lite.scala 197:62] + node _T_22 = bits(io.channels.write_data_channel.WSTRB, 3, 3) @[src/main/scala/bus/AXI4Lite.scala 197:62] + write_strobe[0] <= _T_19 @[src/main/scala/bus/AXI4Lite.scala 197:22] + write_strobe[1] <= _T_20 @[src/main/scala/bus/AXI4Lite.scala 197:22] + write_strobe[2] <= _T_21 @[src/main/scala/bus/AXI4Lite.scala 197:22] + write_strobe[3] <= _T_22 @[src/main/scala/bus/AXI4Lite.scala 197:22] + write <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 198:15] + WREADY <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 199:16] + else : + node _T_23 = asUInt(UInt<3>("h5")) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_24 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_25 = eq(_T_23, _T_24) @[src/main/scala/bus/AXI4Lite.scala 156:17] + when _T_25 : @[src/main/scala/bus/AXI4Lite.scala 156:17] + WREADY <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 203:14] + BVALID <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 204:14] + node _T_26 = and(io.channels.write_response_channel.BREADY, BVALID) @[src/main/scala/bus/AXI4Lite.scala 205:54] + when _T_26 : @[src/main/scala/bus/AXI4Lite.scala 205:65] + state <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 206:15] + write <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 207:15] + BVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 208:16] + + + module Tx : + input clock : Clock + input reset : Reset + output io : { txd : UInt<1>, flip channel : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<8>}} @[src/main/scala/peripheral/UART.scala 32:14] + + reg shiftReg : UInt, clock with : + reset => (reset, UInt<11>("h7ff")) @[src/main/scala/peripheral/UART.scala 40:25] + reg cntReg : UInt<20>, clock with : + reset => (reset, UInt<20>("h0")) @[src/main/scala/peripheral/UART.scala 41:23] + reg bitsReg : UInt<4>, clock with : + reset => (reset, UInt<4>("h0")) @[src/main/scala/peripheral/UART.scala 42:24] + node _io_channel_ready_T = eq(cntReg, UInt<1>("h0")) @[src/main/scala/peripheral/UART.scala 44:31] + node _io_channel_ready_T_1 = eq(bitsReg, UInt<1>("h0")) @[src/main/scala/peripheral/UART.scala 44:52] + node _io_channel_ready_T_2 = and(_io_channel_ready_T, _io_channel_ready_T_1) @[src/main/scala/peripheral/UART.scala 44:40] + io.channel.ready <= _io_channel_ready_T_2 @[src/main/scala/peripheral/UART.scala 44:20] + node _io_txd_T = bits(shiftReg, 0, 0) @[src/main/scala/peripheral/UART.scala 45:21] + io.txd <= _io_txd_T @[src/main/scala/peripheral/UART.scala 45:10] + node _T = eq(cntReg, UInt<1>("h0")) @[src/main/scala/peripheral/UART.scala 47:15] + when _T : @[src/main/scala/peripheral/UART.scala 47:24] + cntReg <= UInt<11>("h43c") @[src/main/scala/peripheral/UART.scala 49:12] + node _T_1 = neq(bitsReg, UInt<1>("h0")) @[src/main/scala/peripheral/UART.scala 50:18] + when _T_1 : @[src/main/scala/peripheral/UART.scala 50:27] + node shift = shr(shiftReg, 1) @[src/main/scala/peripheral/UART.scala 51:28] + node _shiftReg_T = bits(shift, 9, 0) @[src/main/scala/peripheral/UART.scala 52:33] + node _shiftReg_T_1 = cat(UInt<1>("h1"), _shiftReg_T) @[src/main/scala/peripheral/UART.scala 52:22] + shiftReg <= _shiftReg_T_1 @[src/main/scala/peripheral/UART.scala 52:16] + node _bitsReg_T = sub(bitsReg, UInt<1>("h1")) @[src/main/scala/peripheral/UART.scala 53:26] + node _bitsReg_T_1 = tail(_bitsReg_T, 1) @[src/main/scala/peripheral/UART.scala 53:26] + bitsReg <= _bitsReg_T_1 @[src/main/scala/peripheral/UART.scala 53:15] + else : + when io.channel.valid : @[src/main/scala/peripheral/UART.scala 55:30] + node _shiftReg_T_2 = cat(UInt<2>("h3"), io.channel.bits) @[src/main/scala/peripheral/UART.scala 56:28] + node _shiftReg_T_3 = cat(_shiftReg_T_2, UInt<1>("h0")) @[src/main/scala/peripheral/UART.scala 56:24] + shiftReg <= _shiftReg_T_3 @[src/main/scala/peripheral/UART.scala 56:18] + bitsReg <= UInt<4>("hb") @[src/main/scala/peripheral/UART.scala 57:17] + else : + shiftReg <= UInt<11>("h7ff") @[src/main/scala/peripheral/UART.scala 59:18] + else : + node _cntReg_T = sub(cntReg, UInt<1>("h1")) @[src/main/scala/peripheral/UART.scala 64:22] + node _cntReg_T_1 = tail(_cntReg_T, 1) @[src/main/scala/peripheral/UART.scala 64:22] + cntReg <= _cntReg_T_1 @[src/main/scala/peripheral/UART.scala 64:12] + + + module Buffer : + input clock : Clock + input reset : Reset + output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<8>}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<8>}} @[src/main/scala/peripheral/UART.scala 121:14] + + reg stateReg : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/peripheral/UART.scala 127:25] + reg dataReg : UInt<8>, clock with : + reset => (reset, UInt<8>("h0")) @[src/main/scala/peripheral/UART.scala 128:24] + node _io_in_ready_T = eq(stateReg, UInt<1>("h0")) @[src/main/scala/peripheral/UART.scala 130:27] + io.in.ready <= _io_in_ready_T @[src/main/scala/peripheral/UART.scala 130:15] + node _io_out_valid_T = eq(stateReg, UInt<1>("h1")) @[src/main/scala/peripheral/UART.scala 131:28] + io.out.valid <= _io_out_valid_T @[src/main/scala/peripheral/UART.scala 131:16] + node _T = eq(stateReg, UInt<1>("h0")) @[src/main/scala/peripheral/UART.scala 133:17] + when _T : @[src/main/scala/peripheral/UART.scala 133:28] + when io.in.valid : @[src/main/scala/peripheral/UART.scala 134:23] + dataReg <= io.in.bits @[src/main/scala/peripheral/UART.scala 135:15] + stateReg <= UInt<1>("h1") @[src/main/scala/peripheral/UART.scala 136:16] + else : + when io.out.ready : @[src/main/scala/peripheral/UART.scala 139:24] + stateReg <= UInt<1>("h0") @[src/main/scala/peripheral/UART.scala 140:16] + io.out.bits <= dataReg @[src/main/scala/peripheral/UART.scala 143:15] + + module BufferedTx : + input clock : Clock + input reset : Reset + output io : { txd : UInt<1>, flip channel : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<8>}} @[src/main/scala/peripheral/UART.scala 150:14] + + inst tx of Tx @[src/main/scala/peripheral/UART.scala 155:18] + tx.clock <= clock + tx.reset <= reset + inst buf of Buffer @[src/main/scala/peripheral/UART.scala 156:19] + buf.clock <= clock + buf.reset <= reset + buf.io.in <= io.channel @[src/main/scala/peripheral/UART.scala 158:13] + tx.io.channel <= buf.io.out @[src/main/scala/peripheral/UART.scala 159:17] + io.txd <= tx.io.txd @[src/main/scala/peripheral/UART.scala 160:10] + + module Rx : + input clock : Clock + input reset : Reset + output io : { flip rxd : UInt<1>, channel : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<8>}} @[src/main/scala/peripheral/UART.scala 77:14] + + reg rxReg_REG : UInt, clock with : + reset => (reset, UInt<1>("h1")) @[src/main/scala/peripheral/UART.scala 87:30] + rxReg_REG <= io.rxd @[src/main/scala/peripheral/UART.scala 87:30] + reg rxReg : UInt, clock with : + reset => (reset, UInt<1>("h1")) @[src/main/scala/peripheral/UART.scala 87:22] + rxReg <= rxReg_REG @[src/main/scala/peripheral/UART.scala 87:22] + reg shiftReg : UInt<8>, clock with : + reset => (reset, UInt<8>("h0")) @[src/main/scala/peripheral/UART.scala 89:25] + reg cntReg : UInt<20>, clock with : + reset => (reset, UInt<20>("h0")) @[src/main/scala/peripheral/UART.scala 90:23] + reg bitsReg : UInt<4>, clock with : + reset => (reset, UInt<4>("h0")) @[src/main/scala/peripheral/UART.scala 91:24] + reg valReg : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/peripheral/UART.scala 92:23] + node _T = neq(cntReg, UInt<1>("h0")) @[src/main/scala/peripheral/UART.scala 94:15] + when _T : @[src/main/scala/peripheral/UART.scala 94:24] + node _cntReg_T = sub(cntReg, UInt<1>("h1")) @[src/main/scala/peripheral/UART.scala 95:22] + node _cntReg_T_1 = tail(_cntReg_T, 1) @[src/main/scala/peripheral/UART.scala 95:22] + cntReg <= _cntReg_T_1 @[src/main/scala/peripheral/UART.scala 95:12] + else : + node _T_1 = neq(bitsReg, UInt<1>("h0")) @[src/main/scala/peripheral/UART.scala 96:22] + when _T_1 : @[src/main/scala/peripheral/UART.scala 96:31] + cntReg <= UInt<11>("h43c") @[src/main/scala/peripheral/UART.scala 97:12] + node _shiftReg_T = shr(shiftReg, 1) @[src/main/scala/peripheral/UART.scala 98:37] + node _shiftReg_T_1 = cat(rxReg, _shiftReg_T) @[src/main/scala/peripheral/UART.scala 98:20] + shiftReg <= _shiftReg_T_1 @[src/main/scala/peripheral/UART.scala 98:14] + node _bitsReg_T = sub(bitsReg, UInt<1>("h1")) @[src/main/scala/peripheral/UART.scala 99:24] + node _bitsReg_T_1 = tail(_bitsReg_T, 1) @[src/main/scala/peripheral/UART.scala 99:24] + bitsReg <= _bitsReg_T_1 @[src/main/scala/peripheral/UART.scala 99:13] + node _T_2 = eq(bitsReg, UInt<1>("h1")) @[src/main/scala/peripheral/UART.scala 101:18] + when _T_2 : @[src/main/scala/peripheral/UART.scala 101:27] + valReg <= UInt<1>("h1") @[src/main/scala/peripheral/UART.scala 102:14] + else : + node _T_3 = eq(rxReg, UInt<1>("h0")) @[src/main/scala/peripheral/UART.scala 104:20] + when _T_3 : @[src/main/scala/peripheral/UART.scala 104:29] + cntReg <= UInt<11>("h65b") @[src/main/scala/peripheral/UART.scala 105:12] + bitsReg <= UInt<4>("h8") @[src/main/scala/peripheral/UART.scala 106:13] + node _T_4 = and(valReg, io.channel.ready) @[src/main/scala/peripheral/UART.scala 109:15] + when _T_4 : @[src/main/scala/peripheral/UART.scala 109:36] + valReg <= UInt<1>("h0") @[src/main/scala/peripheral/UART.scala 110:12] + io.channel.bits <= shiftReg @[src/main/scala/peripheral/UART.scala 113:19] + io.channel.valid <= valReg @[src/main/scala/peripheral/UART.scala 114:20] + + module Uart : + input clock : Clock + input reset : Reset + output io : { flip channels : { write_address_channel : { AWVALID : UInt<1>, flip AWREADY : UInt<1>, AWADDR : UInt<8>, AWPROT : UInt<3>}, write_data_channel : { WVALID : UInt<1>, flip WREADY : UInt<1>, WDATA : UInt<32>, WSTRB : UInt<4>}, write_response_channel : { flip BVALID : UInt<1>, BREADY : UInt<1>, flip BRESP : UInt<2>}, read_address_channel : { ARVALID : UInt<1>, flip ARREADY : UInt<1>, ARADDR : UInt<8>, ARPROT : UInt<3>}, read_data_channel : { flip RVALID : UInt<1>, RREADY : UInt<1>, flip RDATA : UInt<32>, flip RRESP : UInt<2>}}, flip rxd : UInt<1>, txd : UInt<1>, signal_interrupt : UInt<1>} @[src/main/scala/peripheral/UART.scala 164:14] + + reg interrupt : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/peripheral/UART.scala 171:26] + reg rxData : UInt, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/peripheral/UART.scala 172:23] + inst slave of AXI4LiteSlave @[src/main/scala/peripheral/UART.scala 173:21] + slave.clock <= clock + slave.reset <= reset + slave.io.channels <= io.channels @[src/main/scala/peripheral/UART.scala 174:21] + inst tx of BufferedTx @[src/main/scala/peripheral/UART.scala 176:18] + tx.clock <= clock + tx.reset <= reset + inst rx of Rx @[src/main/scala/peripheral/UART.scala 177:18] + rx.clock <= clock + rx.reset <= reset + slave.io.bundle.read_data <= UInt<1>("h0") @[src/main/scala/peripheral/UART.scala 179:29] + slave.io.bundle.read_valid <= UInt<1>("h1") @[src/main/scala/peripheral/UART.scala 180:30] + when slave.io.bundle.read : @[src/main/scala/peripheral/UART.scala 181:30] + node _T = eq(slave.io.bundle.address, UInt<3>("h4")) @[src/main/scala/peripheral/UART.scala 182:34] + when _T : @[src/main/scala/peripheral/UART.scala 182:45] + slave.io.bundle.read_data <= UInt<17>("h1c200") @[src/main/scala/peripheral/UART.scala 183:33] + else : + node _T_1 = eq(slave.io.bundle.address, UInt<4>("hc")) @[src/main/scala/peripheral/UART.scala 184:40] + when _T_1 : @[src/main/scala/peripheral/UART.scala 184:51] + slave.io.bundle.read_data <= rxData @[src/main/scala/peripheral/UART.scala 185:33] + interrupt <= UInt<1>("h0") @[src/main/scala/peripheral/UART.scala 186:17] + tx.io.channel.valid <= UInt<1>("h0") @[src/main/scala/peripheral/UART.scala 190:23] + tx.io.channel.bits <= UInt<1>("h0") @[src/main/scala/peripheral/UART.scala 191:22] + when slave.io.bundle.write : @[src/main/scala/peripheral/UART.scala 192:31] + node _T_2 = eq(slave.io.bundle.address, UInt<4>("h8")) @[src/main/scala/peripheral/UART.scala 193:34] + when _T_2 : @[src/main/scala/peripheral/UART.scala 193:45] + node _interrupt_T = neq(slave.io.bundle.write_data, UInt<1>("h0")) @[src/main/scala/peripheral/UART.scala 194:47] + interrupt <= _interrupt_T @[src/main/scala/peripheral/UART.scala 194:17] + else : + node _T_3 = eq(slave.io.bundle.address, UInt<5>("h10")) @[src/main/scala/peripheral/UART.scala 195:40] + when _T_3 : @[src/main/scala/peripheral/UART.scala 195:52] + tx.io.channel.valid <= UInt<1>("h1") @[src/main/scala/peripheral/UART.scala 196:27] + tx.io.channel.bits <= slave.io.bundle.write_data @[src/main/scala/peripheral/UART.scala 197:26] + io.txd <= tx.io.txd @[src/main/scala/peripheral/UART.scala 201:10] + rx.io.rxd <= io.rxd @[src/main/scala/peripheral/UART.scala 202:13] + io.signal_interrupt <= interrupt @[src/main/scala/peripheral/UART.scala 204:23] + rx.io.channel.ready <= UInt<1>("h0") @[src/main/scala/peripheral/UART.scala 205:23] + when rx.io.channel.valid : @[src/main/scala/peripheral/UART.scala 206:29] + rx.io.channel.ready <= UInt<1>("h1") @[src/main/scala/peripheral/UART.scala 207:25] + rxData <= rx.io.channel.bits @[src/main/scala/peripheral/UART.scala 208:12] + interrupt <= UInt<1>("h1") @[src/main/scala/peripheral/UART.scala 209:15] + + + module Control : + input clock : Clock + input reset : Reset + output io : { flip jump_flag : UInt<1>, flip jump_instruction_id : UInt<1>, flip stall_flag_if : UInt<1>, flip stall_flag_mem : UInt<1>, flip stall_flag_clint : UInt<1>, flip stall_flag_bus : UInt<1>, flip rs1_id : UInt<5>, flip rs2_id : UInt<5>, flip memory_read_enable_ex : UInt<1>, flip rd_ex : UInt<5>, flip memory_read_enable_mem : UInt<1>, flip rd_mem : UInt<5>, flip csr_start_paging : UInt<1>, if_flush : UInt<1>, id_flush : UInt<1>, pc_stall : UInt<1>, if_stall : UInt<1>, id_stall : UInt<1>, ex_stall : UInt<1>} @[src/main/scala/riscv/core/fivestage/Control.scala 21:14] + + node _id_hazard_T = or(io.memory_read_enable_ex, io.jump_instruction_id) @[src/main/scala/riscv/core/fivestage/Control.scala 44:45] + node _id_hazard_T_1 = neq(io.rd_ex, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/Control.scala 44:84] + node _id_hazard_T_2 = and(_id_hazard_T, _id_hazard_T_1) @[src/main/scala/riscv/core/fivestage/Control.scala 44:72] + node _id_hazard_T_3 = eq(io.rd_ex, io.rs1_id) @[src/main/scala/riscv/core/fivestage/Control.scala 44:105] + node _id_hazard_T_4 = eq(io.rd_ex, io.rs2_id) @[src/main/scala/riscv/core/fivestage/Control.scala 45:17] + node _id_hazard_T_5 = or(_id_hazard_T_3, _id_hazard_T_4) @[src/main/scala/riscv/core/fivestage/Control.scala 45:5] + node _id_hazard_T_6 = and(_id_hazard_T_2, _id_hazard_T_5) @[src/main/scala/riscv/core/fivestage/Control.scala 44:92] + node _id_hazard_T_7 = and(io.jump_instruction_id, io.memory_read_enable_mem) @[src/main/scala/riscv/core/fivestage/Control.scala 46:28] + node _id_hazard_T_8 = neq(io.rd_mem, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/Control.scala 46:70] + node _id_hazard_T_9 = and(_id_hazard_T_7, _id_hazard_T_8) @[src/main/scala/riscv/core/fivestage/Control.scala 46:57] + node _id_hazard_T_10 = eq(io.rd_mem, io.rs1_id) @[src/main/scala/riscv/core/fivestage/Control.scala 46:92] + node _id_hazard_T_11 = eq(io.rd_mem, io.rs2_id) @[src/main/scala/riscv/core/fivestage/Control.scala 47:7] + node _id_hazard_T_12 = or(_id_hazard_T_10, _id_hazard_T_11) @[src/main/scala/riscv/core/fivestage/Control.scala 46:106] + node _id_hazard_T_13 = and(_id_hazard_T_9, _id_hazard_T_12) @[src/main/scala/riscv/core/fivestage/Control.scala 46:78] + node id_hazard = or(_id_hazard_T_6, _id_hazard_T_13) @[src/main/scala/riscv/core/fivestage/Control.scala 45:32] + node _io_if_flush_T = eq(id_hazard, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/Control.scala 48:34] + node _io_if_flush_T_1 = and(io.jump_flag, _io_if_flush_T) @[src/main/scala/riscv/core/fivestage/Control.scala 48:31] + node _io_if_flush_T_2 = or(_io_if_flush_T_1, io.csr_start_paging) @[src/main/scala/riscv/core/fivestage/Control.scala 48:45] + io.if_flush <= _io_if_flush_T_2 @[src/main/scala/riscv/core/fivestage/Control.scala 48:15] + node _io_id_flush_T = or(id_hazard, io.csr_start_paging) @[src/main/scala/riscv/core/fivestage/Control.scala 49:28] + io.id_flush <= _io_id_flush_T @[src/main/scala/riscv/core/fivestage/Control.scala 49:15] + node _io_pc_stall_T = or(io.stall_flag_mem, io.stall_flag_clint) @[src/main/scala/riscv/core/fivestage/Control.scala 51:36] + node _io_pc_stall_T_1 = or(_io_pc_stall_T, id_hazard) @[src/main/scala/riscv/core/fivestage/Control.scala 51:59] + node _io_pc_stall_T_2 = or(_io_pc_stall_T_1, io.stall_flag_bus) @[src/main/scala/riscv/core/fivestage/Control.scala 51:72] + node _io_pc_stall_T_3 = or(_io_pc_stall_T_2, io.stall_flag_if) @[src/main/scala/riscv/core/fivestage/Control.scala 51:93] + io.pc_stall <= _io_pc_stall_T_3 @[src/main/scala/riscv/core/fivestage/Control.scala 51:15] + node _io_if_stall_T = or(io.stall_flag_mem, io.stall_flag_clint) @[src/main/scala/riscv/core/fivestage/Control.scala 52:36] + node _io_if_stall_T_1 = or(_io_if_stall_T, id_hazard) @[src/main/scala/riscv/core/fivestage/Control.scala 52:59] + io.if_stall <= _io_if_stall_T_1 @[src/main/scala/riscv/core/fivestage/Control.scala 52:15] + node _io_id_stall_T = or(io.stall_flag_mem, io.stall_flag_clint) @[src/main/scala/riscv/core/fivestage/Control.scala 53:36] + io.id_stall <= _io_id_stall_T @[src/main/scala/riscv/core/fivestage/Control.scala 53:15] + node _io_ex_stall_T = or(io.stall_flag_mem, io.stall_flag_clint) @[src/main/scala/riscv/core/fivestage/Control.scala 54:36] + io.ex_stall <= _io_ex_stall_T @[src/main/scala/riscv/core/fivestage/Control.scala 54:15] + + module RegisterFile : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip write_address : UInt<5>, flip write_data : UInt<32>, flip read_address1 : UInt<5>, flip read_address2 : UInt<5>, read_data1 : UInt<32>, read_data2 : UInt<32>, flip debug_read_address : UInt<5>, debug_read_data : UInt<32>} @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 33:14] + + reg registers : UInt<32>[32], clock with : + reset => (UInt<1>("h0"), registers) @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + node _T = asUInt(reset) @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:15] + node _T_1 = eq(_T, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:8] + when _T_1 : @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + node _T_2 = neq(io.write_address, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:46] + node _T_3 = and(io.write_enable, _T_2) @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:26] + when _T_3 : @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + registers[io.write_address] <= io.write_data @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + node _io_read_data1_T = eq(io.read_address1, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 57:25] + node _io_read_data1_T_1 = eq(io.read_address1, io.write_address) @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 58:25] + node _io_read_data1_T_2 = and(_io_read_data1_T_1, io.write_enable) @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 58:46] + node _io_read_data1_T_3 = mux(_io_read_data1_T_2, io.write_data, registers[io.read_address1]) @[src/main/scala/chisel3/util/Mux.scala 141:16] + node _io_read_data1_T_4 = mux(_io_read_data1_T, UInt<1>("h0"), _io_read_data1_T_3) @[src/main/scala/chisel3/util/Mux.scala 141:16] + io.read_data1 <= _io_read_data1_T_4 @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 54:17] + node _io_read_data2_T = eq(io.read_address2, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 65:25] + node _io_read_data2_T_1 = eq(io.read_address2, io.write_address) @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 66:25] + node _io_read_data2_T_2 = and(_io_read_data2_T_1, io.write_enable) @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 66:46] + node _io_read_data2_T_3 = mux(_io_read_data2_T_2, io.write_data, registers[io.read_address2]) @[src/main/scala/chisel3/util/Mux.scala 141:16] + node _io_read_data2_T_4 = mux(_io_read_data2_T, UInt<1>("h0"), _io_read_data2_T_3) @[src/main/scala/chisel3/util/Mux.scala 141:16] + io.read_data2 <= _io_read_data2_T_4 @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 62:17] + node _io_debug_read_data_T = eq(io.debug_read_address, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 73:30] + node _io_debug_read_data_T_1 = eq(io.debug_read_address, io.write_address) @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 74:30] + node _io_debug_read_data_T_2 = and(_io_debug_read_data_T_1, io.write_enable) @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 74:51] + node _io_debug_read_data_T_3 = mux(_io_debug_read_data_T_2, io.write_data, registers[io.debug_read_address]) @[src/main/scala/chisel3/util/Mux.scala 141:16] + node _io_debug_read_data_T_4 = mux(_io_debug_read_data_T, UInt<1>("h0"), _io_debug_read_data_T_3) @[src/main/scala/chisel3/util/Mux.scala 141:16] + io.debug_read_data <= _io_debug_read_data_T_4 @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 70:22] + + module InstructionFetch : + input clock : Clock + input reset : Reset + output io : { flip stall_flag_ctrl : UInt<1>, flip jump_flag_id : UInt<1>, flip jump_address_id : UInt<32>, flip physical_address : UInt<32>, ctrl_stall_flag : UInt<1>, id_instruction_address : UInt<32>, id_instruction : UInt<32>, pc_valid : UInt<1>, bus : { read : UInt<1>, address : UInt<32>, flip read_data : UInt<32>, flip read_valid : UInt<1>, write : UInt<1>, write_data : UInt<32>, write_strobe : UInt<1>[4], flip write_valid : UInt<1>, flip busy : UInt<1>, request : UInt<1>, flip granted : UInt<1>}} @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 31:14] + + reg pending_jump : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 45:29] + reg pc : UInt<32>, clock with : + reset => (reset, UInt<32>("h1000")) @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 46:19] + reg state : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 47:22] + reg pc_valid : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 48:25] + io.bus.read <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 51:15] + io.bus.request <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 52:18] + io.bus.write <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 53:16] + io.bus.write_data <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 54:21] + wire _WIRE : UInt<1>[4] @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 55:33] + _WIRE[0] <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 55:33] + _WIRE[1] <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 55:33] + _WIRE[2] <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 55:33] + _WIRE[3] <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 55:33] + io.bus.write_strobe <= _WIRE @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 55:23] + io.pc_valid <= pc_valid @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 56:15] + node _T = eq(pc_valid, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 58:8] + node _T_1 = eq(pc, UInt<32>("h1000")) @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 58:24] + node _T_2 = and(_T, _T_1) @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 58:18] + when _T_2 : @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 58:57] + pc_valid <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 59:14] + node _pc_T = add(pc, UInt<3>("h4")) @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 63:8] + node _pc_T_1 = tail(_pc_T, 1) @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 63:8] + node _pc_T_2 = mux(io.stall_flag_ctrl, pc, _pc_T_1) @[src/main/scala/chisel3/util/Mux.scala 141:16] + node _pc_T_3 = mux(io.jump_flag_id, io.jump_address_id, _pc_T_2) @[src/main/scala/chisel3/util/Mux.scala 141:16] + pc <= _pc_T_3 @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 62:6] + node _T_3 = eq(io.bus.read_valid, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 70:8] + when _T_3 : @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 70:28] + when io.jump_flag_id : @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 71:27] + pending_jump <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 72:20] + when io.bus.read_valid : @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 76:27] + when pending_jump : @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 77:24] + pending_jump <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 78:20] + when io.bus.granted : @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 82:24] + node _T_4 = eq(state, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 83:16] + when _T_4 : @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 83:41] + io.bus.request <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 84:22] + io.bus.read <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 85:19] + state <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 86:13] + else : + node _T_5 = eq(state, UInt<1>("h1")) @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 87:22] + when _T_5 : @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 87:47] + io.bus.read <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 88:19] + io.bus.request <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 89:22] + when io.bus.read_valid : @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 90:31] + state <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 91:15] + node _io_id_instruction_T = eq(pending_jump, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 97:26] + node _io_id_instruction_T_1 = and(io.bus.read_valid, _io_id_instruction_T) @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 97:23] + node _io_id_instruction_T_2 = eq(io.jump_flag_id, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 97:43] + node _io_id_instruction_T_3 = and(_io_id_instruction_T_1, _io_id_instruction_T_2) @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 97:40] + node _io_id_instruction_T_4 = mux(_io_id_instruction_T_3, io.bus.read_data, UInt<32>("h13")) @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 96:27] + io.id_instruction <= _io_id_instruction_T_4 @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 96:21] + node _io_ctrl_stall_flag_T = eq(io.bus.read_valid, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 101:25] + node _io_ctrl_stall_flag_T_1 = or(_io_ctrl_stall_flag_T, pending_jump) @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 101:44] + io.ctrl_stall_flag <= _io_ctrl_stall_flag_T_1 @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 101:22] + io.id_instruction_address <= pc @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 102:29] + io.bus.address <= io.physical_address @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 103:18] + + module PipelineRegister : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<32>, out : UInt<32>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<32>, clock with : + reset => (reset, UInt<32>("h13")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<32>("h13") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_1 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<32>, out : UInt<32>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<32>, clock with : + reset => (reset, UInt<32>("h1000")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<32>("h1000") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_2 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<32>, out : UInt<32>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module IF2ID : + input clock : Clock + input reset : Reset + output io : { flip stall_flag : UInt<1>, flip flush_enable : UInt<1>, flip instruction : UInt<32>, flip instruction_address : UInt<32>, flip interrupt_flag : UInt<32>, output_instruction : UInt<32>, output_instruction_address : UInt<32>, output_interrupt_flag : UInt<32>} @[src/main/scala/riscv/core/fivestage/IF2ID.scala 21:14] + + node write_enable = eq(io.stall_flag, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/IF2ID.scala 33:22] + inst instruction of PipelineRegister @[src/main/scala/riscv/core/fivestage/IF2ID.scala 35:27] + instruction.clock <= clock + instruction.reset <= reset + instruction.io.in <= io.instruction @[src/main/scala/riscv/core/fivestage/IF2ID.scala 36:21] + instruction.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/IF2ID.scala 37:31] + instruction.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/IF2ID.scala 38:31] + io.output_instruction <= instruction.io.out @[src/main/scala/riscv/core/fivestage/IF2ID.scala 39:25] + inst instruction_address of PipelineRegister_1 @[src/main/scala/riscv/core/fivestage/IF2ID.scala 41:35] + instruction_address.clock <= clock + instruction_address.reset <= reset + instruction_address.io.in <= io.instruction_address @[src/main/scala/riscv/core/fivestage/IF2ID.scala 42:29] + instruction_address.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/IF2ID.scala 43:39] + instruction_address.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/IF2ID.scala 44:39] + io.output_instruction_address <= instruction_address.io.out @[src/main/scala/riscv/core/fivestage/IF2ID.scala 45:33] + inst interrupt_flag of PipelineRegister_2 @[src/main/scala/riscv/core/fivestage/IF2ID.scala 47:30] + interrupt_flag.clock <= clock + interrupt_flag.reset <= reset + interrupt_flag.io.in <= io.interrupt_flag @[src/main/scala/riscv/core/fivestage/IF2ID.scala 48:24] + interrupt_flag.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/IF2ID.scala 49:34] + interrupt_flag.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/IF2ID.scala 50:34] + io.output_interrupt_flag <= interrupt_flag.io.out @[src/main/scala/riscv/core/fivestage/IF2ID.scala 51:28] + + module InstructionDecode : + input clock : Clock + input reset : Reset + output io : { flip instruction : UInt<32>, flip instruction_address : UInt<32>, flip reg1_data : UInt<32>, flip reg2_data : UInt<32>, flip forward_from_mem : UInt<32>, flip forward_from_wb : UInt<32>, flip reg1_forward : UInt<2>, flip reg2_forward : UInt<2>, flip interrupt_assert : UInt<1>, flip interrupt_handler_address : UInt<32>, regs_reg1_read_address : UInt<5>, regs_reg2_read_address : UInt<5>, ex_reg1_data : UInt<32>, ex_reg2_data : UInt<32>, ex_immediate : UInt<32>, ex_aluop1_source : UInt<1>, ex_aluop2_source : UInt<1>, ex_memory_read_enable : UInt<1>, ex_memory_write_enable : UInt<1>, ex_reg_write_source : UInt<2>, ex_reg_write_enable : UInt<1>, ex_reg_write_address : UInt<5>, ex_csr_address : UInt<12>, ex_csr_write_enable : UInt<1>, ctrl_jump_instruction : UInt<1>, clint_jump_flag : UInt<1>, clint_jump_address : UInt<32>, if_jump_flag : UInt<1>, if_jump_address : UInt<32>} @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 136:14] + + node opcode = bits(io.instruction, 6, 0) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 168:30] + node funct3 = bits(io.instruction, 14, 12) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 169:30] + node funct7 = bits(io.instruction, 31, 25) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 170:30] + node rd = bits(io.instruction, 11, 7) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 171:26] + node rs1 = bits(io.instruction, 19, 15) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 172:27] + node rs2 = bits(io.instruction, 24, 20) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 173:27] + node _io_regs_reg1_read_address_T = eq(opcode, UInt<6>("h37")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 175:43] + node _io_regs_reg1_read_address_T_1 = mux(_io_regs_reg1_read_address_T, UInt<5>("h0"), rs1) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 175:35] + io.regs_reg1_read_address <= _io_regs_reg1_read_address_T_1 @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 175:29] + io.regs_reg2_read_address <= rs2 @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 176:29] + io.ex_reg1_data <= io.reg1_data @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 177:19] + io.ex_reg2_data <= io.reg2_data @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 178:19] + node _io_ex_immediate_T = bits(io.instruction, 31, 31) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:67] + node _io_ex_immediate_T_1 = bits(_io_ex_immediate_T, 0, 0) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:48] + node _io_ex_immediate_T_2 = mux(_io_ex_immediate_T_1, UInt<20>("hfffff"), UInt<20>("h0")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:48] + node _io_ex_immediate_T_3 = bits(io.instruction, 31, 20) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:88] + node _io_ex_immediate_T_4 = cat(_io_ex_immediate_T_2, _io_ex_immediate_T_3) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:43] + node _io_ex_immediate_T_5 = bits(io.instruction, 31, 31) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 181:56] + node _io_ex_immediate_T_6 = bits(_io_ex_immediate_T_5, 0, 0) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 181:37] + node _io_ex_immediate_T_7 = mux(_io_ex_immediate_T_6, UInt<21>("h1fffff"), UInt<21>("h0")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 181:37] + node _io_ex_immediate_T_8 = bits(io.instruction, 30, 20) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 181:77] + node _io_ex_immediate_T_9 = cat(_io_ex_immediate_T_7, _io_ex_immediate_T_8) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 181:32] + node _io_ex_immediate_T_10 = bits(io.instruction, 31, 31) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 182:56] + node _io_ex_immediate_T_11 = bits(_io_ex_immediate_T_10, 0, 0) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 182:37] + node _io_ex_immediate_T_12 = mux(_io_ex_immediate_T_11, UInt<21>("h1fffff"), UInt<21>("h0")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 182:37] + node _io_ex_immediate_T_13 = bits(io.instruction, 30, 20) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 182:77] + node _io_ex_immediate_T_14 = cat(_io_ex_immediate_T_12, _io_ex_immediate_T_13) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 182:32] + node _io_ex_immediate_T_15 = bits(io.instruction, 31, 31) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 183:55] + node _io_ex_immediate_T_16 = bits(_io_ex_immediate_T_15, 0, 0) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 183:36] + node _io_ex_immediate_T_17 = mux(_io_ex_immediate_T_16, UInt<21>("h1fffff"), UInt<21>("h0")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 183:36] + node _io_ex_immediate_T_18 = bits(io.instruction, 30, 20) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 183:76] + node _io_ex_immediate_T_19 = cat(_io_ex_immediate_T_17, _io_ex_immediate_T_18) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 183:31] + node _io_ex_immediate_T_20 = bits(io.instruction, 31, 31) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 184:56] + node _io_ex_immediate_T_21 = bits(_io_ex_immediate_T_20, 0, 0) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 184:37] + node _io_ex_immediate_T_22 = mux(_io_ex_immediate_T_21, UInt<21>("h1fffff"), UInt<21>("h0")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 184:37] + node _io_ex_immediate_T_23 = bits(io.instruction, 30, 25) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 184:77] + node _io_ex_immediate_T_24 = bits(io.instruction, 11, 7) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 184:101] + node io_ex_immediate_hi = cat(_io_ex_immediate_T_22, _io_ex_immediate_T_23) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 184:32] + node _io_ex_immediate_T_25 = cat(io_ex_immediate_hi, _io_ex_immediate_T_24) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 184:32] + node _io_ex_immediate_T_26 = bits(io.instruction, 31, 31) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 185:56] + node _io_ex_immediate_T_27 = bits(_io_ex_immediate_T_26, 0, 0) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 185:37] + node _io_ex_immediate_T_28 = mux(_io_ex_immediate_T_27, UInt<20>("hfffff"), UInt<20>("h0")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 185:37] + node _io_ex_immediate_T_29 = bits(io.instruction, 7, 7) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 185:77] + node _io_ex_immediate_T_30 = bits(io.instruction, 30, 25) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 185:96] + node _io_ex_immediate_T_31 = bits(io.instruction, 11, 8) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 186:21] + node io_ex_immediate_lo = cat(_io_ex_immediate_T_31, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 185:32] + node io_ex_immediate_hi_hi = cat(_io_ex_immediate_T_28, _io_ex_immediate_T_29) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 185:32] + node io_ex_immediate_hi_1 = cat(io_ex_immediate_hi_hi, _io_ex_immediate_T_30) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 185:32] + node _io_ex_immediate_T_32 = cat(io_ex_immediate_hi_1, io_ex_immediate_lo) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 185:32] + node _io_ex_immediate_T_33 = bits(io.instruction, 31, 12) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 187:45] + node _io_ex_immediate_T_34 = cat(_io_ex_immediate_T_33, UInt<12>("h0")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 187:30] + node _io_ex_immediate_T_35 = bits(io.instruction, 31, 12) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 188:47] + node _io_ex_immediate_T_36 = cat(_io_ex_immediate_T_35, UInt<12>("h0")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 188:32] + node _io_ex_immediate_T_37 = bits(io.instruction, 31, 31) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 189:54] + node _io_ex_immediate_T_38 = bits(_io_ex_immediate_T_37, 0, 0) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 189:35] + node _io_ex_immediate_T_39 = mux(_io_ex_immediate_T_38, UInt<12>("hfff"), UInt<12>("h0")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 189:35] + node _io_ex_immediate_T_40 = bits(io.instruction, 19, 12) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 189:75] + node _io_ex_immediate_T_41 = bits(io.instruction, 20, 20) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 189:99] + node _io_ex_immediate_T_42 = bits(io.instruction, 30, 21) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 190:21] + node io_ex_immediate_lo_1 = cat(_io_ex_immediate_T_42, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 189:30] + node io_ex_immediate_hi_hi_1 = cat(_io_ex_immediate_T_39, _io_ex_immediate_T_40) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 189:30] + node io_ex_immediate_hi_2 = cat(io_ex_immediate_hi_hi_1, _io_ex_immediate_T_41) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 189:30] + node _io_ex_immediate_T_43 = cat(io_ex_immediate_hi_2, io_ex_immediate_lo_1) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 189:30] + node _io_ex_immediate_T_44 = eq(UInt<5>("h13"), opcode) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:98] + node _io_ex_immediate_T_45 = mux(_io_ex_immediate_T_44, _io_ex_immediate_T_9, _io_ex_immediate_T_4) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:98] + node _io_ex_immediate_T_46 = eq(UInt<2>("h3"), opcode) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:98] + node _io_ex_immediate_T_47 = mux(_io_ex_immediate_T_46, _io_ex_immediate_T_14, _io_ex_immediate_T_45) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:98] + node _io_ex_immediate_T_48 = eq(UInt<7>("h67"), opcode) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:98] + node _io_ex_immediate_T_49 = mux(_io_ex_immediate_T_48, _io_ex_immediate_T_19, _io_ex_immediate_T_47) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:98] + node _io_ex_immediate_T_50 = eq(UInt<6>("h23"), opcode) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:98] + node _io_ex_immediate_T_51 = mux(_io_ex_immediate_T_50, _io_ex_immediate_T_25, _io_ex_immediate_T_49) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:98] + node _io_ex_immediate_T_52 = eq(UInt<7>("h63"), opcode) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:98] + node _io_ex_immediate_T_53 = mux(_io_ex_immediate_T_52, _io_ex_immediate_T_32, _io_ex_immediate_T_51) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:98] + node _io_ex_immediate_T_54 = eq(UInt<6>("h37"), opcode) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:98] + node _io_ex_immediate_T_55 = mux(_io_ex_immediate_T_54, _io_ex_immediate_T_34, _io_ex_immediate_T_53) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:98] + node _io_ex_immediate_T_56 = eq(UInt<5>("h17"), opcode) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:98] + node _io_ex_immediate_T_57 = mux(_io_ex_immediate_T_56, _io_ex_immediate_T_36, _io_ex_immediate_T_55) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:98] + node _io_ex_immediate_T_58 = eq(UInt<7>("h6f"), opcode) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:98] + node _io_ex_immediate_T_59 = mux(_io_ex_immediate_T_58, _io_ex_immediate_T_43, _io_ex_immediate_T_57) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:98] + io.ex_immediate <= _io_ex_immediate_T_59 @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:19] + node _io_ex_aluop1_source_T = eq(opcode, UInt<5>("h17")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 194:12] + node _io_ex_aluop1_source_T_1 = eq(opcode, UInt<7>("h63")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 194:45] + node _io_ex_aluop1_source_T_2 = or(_io_ex_aluop1_source_T, _io_ex_aluop1_source_T_1) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 194:35] + node _io_ex_aluop1_source_T_3 = eq(opcode, UInt<7>("h6f")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 194:78] + node _io_ex_aluop1_source_T_4 = or(_io_ex_aluop1_source_T_2, _io_ex_aluop1_source_T_3) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 194:68] + node _io_ex_aluop1_source_T_5 = mux(_io_ex_aluop1_source_T_4, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 193:29] + io.ex_aluop1_source <= _io_ex_aluop1_source_T_5 @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 193:23] + node _io_ex_aluop2_source_T = eq(opcode, UInt<6>("h33")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 199:12] + node _io_ex_aluop2_source_T_1 = mux(_io_ex_aluop2_source_T, UInt<1>("h0"), UInt<1>("h1")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 198:29] + io.ex_aluop2_source <= _io_ex_aluop2_source_T_1 @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 198:23] + node _io_ex_memory_read_enable_T = eq(opcode, UInt<2>("h3")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 203:38] + io.ex_memory_read_enable <= _io_ex_memory_read_enable_T @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 203:28] + node _io_ex_memory_write_enable_T = eq(opcode, UInt<6>("h23")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 204:39] + io.ex_memory_write_enable <= _io_ex_memory_write_enable_T @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 204:29] + node _io_ex_reg_write_source_T = eq(UInt<2>("h3"), opcode) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 205:72] + node _io_ex_reg_write_source_T_1 = mux(_io_ex_reg_write_source_T, UInt<2>("h1"), UInt<2>("h0")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 205:72] + node _io_ex_reg_write_source_T_2 = eq(UInt<7>("h73"), opcode) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 205:72] + node _io_ex_reg_write_source_T_3 = mux(_io_ex_reg_write_source_T_2, UInt<2>("h2"), _io_ex_reg_write_source_T_1) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 205:72] + node _io_ex_reg_write_source_T_4 = eq(UInt<7>("h6f"), opcode) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 205:72] + node _io_ex_reg_write_source_T_5 = mux(_io_ex_reg_write_source_T_4, UInt<2>("h3"), _io_ex_reg_write_source_T_3) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 205:72] + node _io_ex_reg_write_source_T_6 = eq(UInt<7>("h67"), opcode) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 205:72] + node _io_ex_reg_write_source_T_7 = mux(_io_ex_reg_write_source_T_6, UInt<2>("h3"), _io_ex_reg_write_source_T_5) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 205:72] + io.ex_reg_write_source <= _io_ex_reg_write_source_T_7 @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 205:26] + node _io_ex_reg_write_enable_T = eq(opcode, UInt<6>("h33")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 213:37] + node _io_ex_reg_write_enable_T_1 = eq(opcode, UInt<5>("h13")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 213:73] + node _io_ex_reg_write_enable_T_2 = or(_io_ex_reg_write_enable_T, _io_ex_reg_write_enable_T_1) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 213:62] + node _io_ex_reg_write_enable_T_3 = eq(opcode, UInt<2>("h3")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 214:13] + node _io_ex_reg_write_enable_T_4 = or(_io_ex_reg_write_enable_T_2, _io_ex_reg_write_enable_T_3) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 213:97] + node _io_ex_reg_write_enable_T_5 = eq(opcode, UInt<5>("h17")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 214:48] + node _io_ex_reg_write_enable_T_6 = or(_io_ex_reg_write_enable_T_4, _io_ex_reg_write_enable_T_5) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 214:37] + node _io_ex_reg_write_enable_T_7 = eq(opcode, UInt<6>("h37")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 214:83] + node _io_ex_reg_write_enable_T_8 = or(_io_ex_reg_write_enable_T_6, _io_ex_reg_write_enable_T_7) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 214:72] + node _io_ex_reg_write_enable_T_9 = eq(opcode, UInt<7>("h6f")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 215:13] + node _io_ex_reg_write_enable_T_10 = or(_io_ex_reg_write_enable_T_8, _io_ex_reg_write_enable_T_9) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 214:105] + node _io_ex_reg_write_enable_T_11 = eq(opcode, UInt<7>("h67")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 215:46] + node _io_ex_reg_write_enable_T_12 = or(_io_ex_reg_write_enable_T_10, _io_ex_reg_write_enable_T_11) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 215:35] + node _io_ex_reg_write_enable_T_13 = eq(opcode, UInt<7>("h73")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 215:80] + node _io_ex_reg_write_enable_T_14 = or(_io_ex_reg_write_enable_T_12, _io_ex_reg_write_enable_T_13) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 215:69] + io.ex_reg_write_enable <= _io_ex_reg_write_enable_T_14 @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 213:26] + node _io_ex_reg_write_address_T = bits(io.instruction, 11, 7) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 216:44] + io.ex_reg_write_address <= _io_ex_reg_write_address_T @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 216:27] + node _io_ex_csr_address_T = bits(io.instruction, 31, 20) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 217:38] + io.ex_csr_address <= _io_ex_csr_address_T @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 217:21] + node _io_ex_csr_write_enable_T = eq(opcode, UInt<7>("h73")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 218:37] + node _io_ex_csr_write_enable_T_1 = eq(funct3, UInt<1>("h1")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 219:12] + node _io_ex_csr_write_enable_T_2 = eq(funct3, UInt<3>("h5")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 219:52] + node _io_ex_csr_write_enable_T_3 = or(_io_ex_csr_write_enable_T_1, _io_ex_csr_write_enable_T_2) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 219:42] + node _io_ex_csr_write_enable_T_4 = eq(funct3, UInt<2>("h2")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 220:14] + node _io_ex_csr_write_enable_T_5 = or(_io_ex_csr_write_enable_T_3, _io_ex_csr_write_enable_T_4) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 219:83] + node _io_ex_csr_write_enable_T_6 = eq(funct3, UInt<3>("h6")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 220:54] + node _io_ex_csr_write_enable_T_7 = or(_io_ex_csr_write_enable_T_5, _io_ex_csr_write_enable_T_6) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 220:44] + node _io_ex_csr_write_enable_T_8 = eq(funct3, UInt<2>("h3")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 221:14] + node _io_ex_csr_write_enable_T_9 = or(_io_ex_csr_write_enable_T_7, _io_ex_csr_write_enable_T_8) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 220:85] + node _io_ex_csr_write_enable_T_10 = eq(funct3, UInt<3>("h7")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 221:54] + node _io_ex_csr_write_enable_T_11 = or(_io_ex_csr_write_enable_T_9, _io_ex_csr_write_enable_T_10) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 221:44] + node _io_ex_csr_write_enable_T_12 = and(_io_ex_csr_write_enable_T, _io_ex_csr_write_enable_T_11) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 218:59] + io.ex_csr_write_enable <= _io_ex_csr_write_enable_T_12 @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 218:26] + node _reg1_data_T = eq(UInt<2>("h1"), io.reg1_forward) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 224:59] + node _reg1_data_T_1 = mux(_reg1_data_T, io.forward_from_mem, io.reg1_data) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 224:59] + node _reg1_data_T_2 = eq(UInt<2>("h2"), io.reg1_forward) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 224:59] + node reg1_data = mux(_reg1_data_T_2, io.forward_from_wb, _reg1_data_T_1) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 224:59] + node _reg2_data_T = eq(UInt<2>("h1"), io.reg2_forward) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 230:59] + node _reg2_data_T_1 = mux(_reg2_data_T, io.forward_from_mem, io.reg2_data) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 230:59] + node _reg2_data_T_2 = eq(UInt<2>("h2"), io.reg2_forward) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 230:59] + node reg2_data = mux(_reg2_data_T_2, io.forward_from_wb, _reg2_data_T_1) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 230:59] + node _io_ctrl_jump_instruction_T = eq(opcode, UInt<7>("h6f")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 236:39] + node _io_ctrl_jump_instruction_T_1 = eq(opcode, UInt<7>("h67")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 237:13] + node _io_ctrl_jump_instruction_T_2 = or(_io_ctrl_jump_instruction_T, _io_ctrl_jump_instruction_T_1) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 236:61] + node _io_ctrl_jump_instruction_T_3 = eq(opcode, UInt<7>("h63")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 237:47] + node _io_ctrl_jump_instruction_T_4 = or(_io_ctrl_jump_instruction_T_2, _io_ctrl_jump_instruction_T_3) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 237:36] + io.ctrl_jump_instruction <= _io_ctrl_jump_instruction_T_4 @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 236:28] + node _instruction_jump_flag_T = eq(opcode, UInt<7>("h6f")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 238:39] + node _instruction_jump_flag_T_1 = eq(opcode, UInt<7>("h67")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 239:13] + node _instruction_jump_flag_T_2 = or(_instruction_jump_flag_T, _instruction_jump_flag_T_1) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 238:61] + node _instruction_jump_flag_T_3 = eq(opcode, UInt<7>("h63")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 240:13] + node _instruction_jump_flag_T_4 = eq(reg1_data, reg2_data) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 242:45] + node _instruction_jump_flag_T_5 = neq(reg1_data, reg2_data) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 243:45] + node _instruction_jump_flag_T_6 = asSInt(reg1_data) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 244:45] + node _instruction_jump_flag_T_7 = asSInt(reg2_data) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 244:64] + node _instruction_jump_flag_T_8 = lt(_instruction_jump_flag_T_6, _instruction_jump_flag_T_7) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 244:52] + node _instruction_jump_flag_T_9 = asSInt(reg1_data) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 245:45] + node _instruction_jump_flag_T_10 = asSInt(reg2_data) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 245:65] + node _instruction_jump_flag_T_11 = geq(_instruction_jump_flag_T_9, _instruction_jump_flag_T_10) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 245:52] + node _instruction_jump_flag_T_12 = lt(reg1_data, reg2_data) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 246:53] + node _instruction_jump_flag_T_13 = geq(reg1_data, reg2_data) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 247:53] + node _instruction_jump_flag_T_14 = eq(UInt<1>("h0"), funct3) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 240:66] + node _instruction_jump_flag_T_15 = mux(_instruction_jump_flag_T_14, _instruction_jump_flag_T_4, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 240:66] + node _instruction_jump_flag_T_16 = eq(UInt<1>("h1"), funct3) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 240:66] + node _instruction_jump_flag_T_17 = mux(_instruction_jump_flag_T_16, _instruction_jump_flag_T_5, _instruction_jump_flag_T_15) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 240:66] + node _instruction_jump_flag_T_18 = eq(UInt<3>("h4"), funct3) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 240:66] + node _instruction_jump_flag_T_19 = mux(_instruction_jump_flag_T_18, _instruction_jump_flag_T_8, _instruction_jump_flag_T_17) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 240:66] + node _instruction_jump_flag_T_20 = eq(UInt<3>("h5"), funct3) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 240:66] + node _instruction_jump_flag_T_21 = mux(_instruction_jump_flag_T_20, _instruction_jump_flag_T_11, _instruction_jump_flag_T_19) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 240:66] + node _instruction_jump_flag_T_22 = eq(UInt<3>("h6"), funct3) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 240:66] + node _instruction_jump_flag_T_23 = mux(_instruction_jump_flag_T_22, _instruction_jump_flag_T_12, _instruction_jump_flag_T_21) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 240:66] + node _instruction_jump_flag_T_24 = eq(UInt<3>("h7"), funct3) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 240:66] + node _instruction_jump_flag_T_25 = mux(_instruction_jump_flag_T_24, _instruction_jump_flag_T_13, _instruction_jump_flag_T_23) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 240:66] + node _instruction_jump_flag_T_26 = and(_instruction_jump_flag_T_3, _instruction_jump_flag_T_25) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 240:37] + node instruction_jump_flag = or(_instruction_jump_flag_T_2, _instruction_jump_flag_T_26) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 239:36] + node _instruction_jump_address_T = eq(opcode, UInt<7>("h67")) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 250:63] + node _instruction_jump_address_T_1 = mux(_instruction_jump_address_T, reg1_data, io.instruction_address) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 250:55] + node _instruction_jump_address_T_2 = add(io.ex_immediate, _instruction_jump_address_T_1) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 250:50] + node instruction_jump_address = tail(_instruction_jump_address_T_2, 1) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 250:50] + io.clint_jump_flag <= instruction_jump_flag @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 251:22] + io.clint_jump_address <= instruction_jump_address @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 252:25] + node _io_if_jump_flag_T = or(io.interrupt_assert, instruction_jump_flag) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 253:42] + io.if_jump_flag <= _io_if_jump_flag_T @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 253:19] + node _io_if_jump_address_T = mux(io.interrupt_assert, io.interrupt_handler_address, instruction_jump_address) @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 254:28] + io.if_jump_address <= _io_if_jump_address_T @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 254:22] + + module PipelineRegister_3 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<32>, out : UInt<32>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<32>, clock with : + reset => (reset, UInt<32>("h13")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<32>("h13") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_4 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<32>, out : UInt<32>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<32>, clock with : + reset => (reset, UInt<32>("h1000")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<32>("h1000") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_5 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<1>, out : UInt<1>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_6 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<5>, out : UInt<5>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<5>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_7 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<2>, out : UInt<2>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<2>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_8 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<32>, out : UInt<32>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_9 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<32>, out : UInt<32>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_10 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<32>, out : UInt<32>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_11 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<1>, out : UInt<1>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_12 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<1>, out : UInt<1>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_13 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<1>, out : UInt<1>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_14 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<12>, out : UInt<12>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<12>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_15 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<1>, out : UInt<1>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_16 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<1>, out : UInt<1>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_17 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<32>, out : UInt<32>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module ID2EX : + input clock : Clock + input reset : Reset + output io : { flip stall_flag : UInt<1>, flip flush_enable : UInt<1>, flip instruction : UInt<32>, flip instruction_address : UInt<32>, flip regs_write_enable : UInt<1>, flip regs_write_address : UInt<5>, flip regs_write_source : UInt<2>, flip reg1_data : UInt<32>, flip reg2_data : UInt<32>, flip immediate : UInt<32>, flip aluop1_source : UInt<1>, flip aluop2_source : UInt<1>, flip csr_write_enable : UInt<1>, flip csr_address : UInt<12>, flip memory_read_enable : UInt<1>, flip memory_write_enable : UInt<1>, flip csr_read_data : UInt<32>, output_instruction : UInt<32>, output_instruction_address : UInt<32>, output_regs_write_enable : UInt<1>, output_regs_write_address : UInt<5>, output_regs_write_source : UInt<2>, output_reg1_data : UInt<32>, output_reg2_data : UInt<32>, output_immediate : UInt<32>, output_aluop1_source : UInt<1>, output_aluop2_source : UInt<1>, output_csr_write_enable : UInt<1>, output_csr_address : UInt<12>, output_memory_read_enable : UInt<1>, output_memory_write_enable : UInt<1>, output_csr_read_data : UInt<32>} @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + + node write_enable = eq(io.stall_flag, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/ID2EX.scala 56:22] + inst instruction of PipelineRegister_3 @[src/main/scala/riscv/core/fivestage/ID2EX.scala 58:27] + instruction.clock <= clock + instruction.reset <= reset + instruction.io.in <= io.instruction @[src/main/scala/riscv/core/fivestage/ID2EX.scala 59:21] + instruction.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 60:31] + instruction.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 61:31] + io.output_instruction <= instruction.io.out @[src/main/scala/riscv/core/fivestage/ID2EX.scala 62:25] + inst instruction_address of PipelineRegister_4 @[src/main/scala/riscv/core/fivestage/ID2EX.scala 64:35] + instruction_address.clock <= clock + instruction_address.reset <= reset + instruction_address.io.in <= io.instruction_address @[src/main/scala/riscv/core/fivestage/ID2EX.scala 65:29] + instruction_address.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 66:39] + instruction_address.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 67:39] + io.output_instruction_address <= instruction_address.io.out @[src/main/scala/riscv/core/fivestage/ID2EX.scala 68:33] + inst regs_write_enable of PipelineRegister_5 @[src/main/scala/riscv/core/fivestage/ID2EX.scala 70:33] + regs_write_enable.clock <= clock + regs_write_enable.reset <= reset + regs_write_enable.io.in <= io.regs_write_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 71:27] + regs_write_enable.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 72:37] + regs_write_enable.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 73:37] + io.output_regs_write_enable <= regs_write_enable.io.out @[src/main/scala/riscv/core/fivestage/ID2EX.scala 74:31] + inst regs_write_address of PipelineRegister_6 @[src/main/scala/riscv/core/fivestage/ID2EX.scala 76:34] + regs_write_address.clock <= clock + regs_write_address.reset <= reset + regs_write_address.io.in <= io.regs_write_address @[src/main/scala/riscv/core/fivestage/ID2EX.scala 77:28] + regs_write_address.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 78:38] + regs_write_address.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 79:38] + io.output_regs_write_address <= regs_write_address.io.out @[src/main/scala/riscv/core/fivestage/ID2EX.scala 80:32] + inst regs_write_source of PipelineRegister_7 @[src/main/scala/riscv/core/fivestage/ID2EX.scala 82:33] + regs_write_source.clock <= clock + regs_write_source.reset <= reset + regs_write_source.io.in <= io.regs_write_source @[src/main/scala/riscv/core/fivestage/ID2EX.scala 83:27] + regs_write_source.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 84:37] + regs_write_source.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 85:37] + io.output_regs_write_source <= regs_write_source.io.out @[src/main/scala/riscv/core/fivestage/ID2EX.scala 86:31] + inst reg1_data of PipelineRegister_8 @[src/main/scala/riscv/core/fivestage/ID2EX.scala 88:25] + reg1_data.clock <= clock + reg1_data.reset <= reset + reg1_data.io.in <= io.reg1_data @[src/main/scala/riscv/core/fivestage/ID2EX.scala 89:19] + reg1_data.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 90:29] + reg1_data.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 91:29] + io.output_reg1_data <= reg1_data.io.out @[src/main/scala/riscv/core/fivestage/ID2EX.scala 92:23] + inst reg2_data of PipelineRegister_9 @[src/main/scala/riscv/core/fivestage/ID2EX.scala 94:25] + reg2_data.clock <= clock + reg2_data.reset <= reset + reg2_data.io.in <= io.reg2_data @[src/main/scala/riscv/core/fivestage/ID2EX.scala 95:19] + reg2_data.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 96:29] + reg2_data.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 97:29] + io.output_reg2_data <= reg2_data.io.out @[src/main/scala/riscv/core/fivestage/ID2EX.scala 98:23] + inst immediate of PipelineRegister_10 @[src/main/scala/riscv/core/fivestage/ID2EX.scala 100:25] + immediate.clock <= clock + immediate.reset <= reset + immediate.io.in <= io.immediate @[src/main/scala/riscv/core/fivestage/ID2EX.scala 101:19] + immediate.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 102:29] + immediate.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 103:29] + io.output_immediate <= immediate.io.out @[src/main/scala/riscv/core/fivestage/ID2EX.scala 104:23] + inst aluop1_source of PipelineRegister_11 @[src/main/scala/riscv/core/fivestage/ID2EX.scala 106:29] + aluop1_source.clock <= clock + aluop1_source.reset <= reset + aluop1_source.io.in <= io.aluop1_source @[src/main/scala/riscv/core/fivestage/ID2EX.scala 107:23] + aluop1_source.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 108:33] + aluop1_source.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 109:33] + io.output_aluop1_source <= aluop1_source.io.out @[src/main/scala/riscv/core/fivestage/ID2EX.scala 110:27] + inst aluop2_source of PipelineRegister_12 @[src/main/scala/riscv/core/fivestage/ID2EX.scala 112:29] + aluop2_source.clock <= clock + aluop2_source.reset <= reset + aluop2_source.io.in <= io.aluop2_source @[src/main/scala/riscv/core/fivestage/ID2EX.scala 113:23] + aluop2_source.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 114:33] + aluop2_source.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 115:33] + io.output_aluop2_source <= aluop2_source.io.out @[src/main/scala/riscv/core/fivestage/ID2EX.scala 116:27] + inst csr_write_enable of PipelineRegister_13 @[src/main/scala/riscv/core/fivestage/ID2EX.scala 118:32] + csr_write_enable.clock <= clock + csr_write_enable.reset <= reset + csr_write_enable.io.in <= io.csr_write_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 119:26] + csr_write_enable.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 120:36] + csr_write_enable.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 121:36] + io.output_csr_write_enable <= csr_write_enable.io.out @[src/main/scala/riscv/core/fivestage/ID2EX.scala 122:30] + inst csr_address of PipelineRegister_14 @[src/main/scala/riscv/core/fivestage/ID2EX.scala 124:27] + csr_address.clock <= clock + csr_address.reset <= reset + csr_address.io.in <= io.csr_address @[src/main/scala/riscv/core/fivestage/ID2EX.scala 125:21] + csr_address.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 126:31] + csr_address.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 127:31] + io.output_csr_address <= csr_address.io.out @[src/main/scala/riscv/core/fivestage/ID2EX.scala 128:25] + inst memory_read_enable of PipelineRegister_15 @[src/main/scala/riscv/core/fivestage/ID2EX.scala 130:34] + memory_read_enable.clock <= clock + memory_read_enable.reset <= reset + memory_read_enable.io.in <= io.memory_read_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 131:28] + memory_read_enable.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 132:38] + memory_read_enable.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 133:38] + io.output_memory_read_enable <= memory_read_enable.io.out @[src/main/scala/riscv/core/fivestage/ID2EX.scala 134:32] + inst memory_write_enable of PipelineRegister_16 @[src/main/scala/riscv/core/fivestage/ID2EX.scala 136:35] + memory_write_enable.clock <= clock + memory_write_enable.reset <= reset + memory_write_enable.io.in <= io.memory_write_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 137:29] + memory_write_enable.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 138:39] + memory_write_enable.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 139:39] + io.output_memory_write_enable <= memory_write_enable.io.out @[src/main/scala/riscv/core/fivestage/ID2EX.scala 140:33] + inst csr_read_data of PipelineRegister_17 @[src/main/scala/riscv/core/fivestage/ID2EX.scala 142:29] + csr_read_data.clock <= clock + csr_read_data.reset <= reset + csr_read_data.io.in <= io.csr_read_data @[src/main/scala/riscv/core/fivestage/ID2EX.scala 143:23] + csr_read_data.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 144:33] + csr_read_data.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/ID2EX.scala 145:33] + io.output_csr_read_data <= csr_read_data.io.out @[src/main/scala/riscv/core/fivestage/ID2EX.scala 146:27] + + module ALU : + input clock : Clock + input reset : Reset + output io : { flip func : UInt<4>, flip op1 : UInt<32>, flip op2 : UInt<32>, result : UInt<32>} @[src/main/scala/riscv/core/fivestage/ALU.scala 26:14] + + io.result <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/ALU.scala 35:13] + node _T = asUInt(UInt<1>("h1")) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _T_1 = asUInt(io.func) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _T_2 = eq(_T, _T_1) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + when _T_2 : @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _io_result_T = add(io.op1, io.op2) @[src/main/scala/riscv/core/fivestage/ALU.scala 38:27] + node _io_result_T_1 = tail(_io_result_T, 1) @[src/main/scala/riscv/core/fivestage/ALU.scala 38:27] + io.result <= _io_result_T_1 @[src/main/scala/riscv/core/fivestage/ALU.scala 38:17] + else : + node _T_3 = asUInt(UInt<2>("h2")) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _T_4 = asUInt(io.func) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _T_5 = eq(_T_3, _T_4) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + when _T_5 : @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _io_result_T_2 = sub(io.op1, io.op2) @[src/main/scala/riscv/core/fivestage/ALU.scala 41:27] + node _io_result_T_3 = tail(_io_result_T_2, 1) @[src/main/scala/riscv/core/fivestage/ALU.scala 41:27] + io.result <= _io_result_T_3 @[src/main/scala/riscv/core/fivestage/ALU.scala 41:17] + else : + node _T_6 = asUInt(UInt<2>("h3")) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _T_7 = asUInt(io.func) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _T_8 = eq(_T_6, _T_7) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + when _T_8 : @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _io_result_T_4 = bits(io.op2, 4, 0) @[src/main/scala/riscv/core/fivestage/ALU.scala 44:36] + node _io_result_T_5 = dshl(io.op1, _io_result_T_4) @[src/main/scala/riscv/core/fivestage/ALU.scala 44:27] + io.result <= _io_result_T_5 @[src/main/scala/riscv/core/fivestage/ALU.scala 44:17] + else : + node _T_9 = asUInt(UInt<3>("h4")) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _T_10 = asUInt(io.func) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _T_11 = eq(_T_9, _T_10) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + when _T_11 : @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _io_result_T_6 = asSInt(io.op1) @[src/main/scala/riscv/core/fivestage/ALU.scala 47:27] + node _io_result_T_7 = asSInt(io.op2) @[src/main/scala/riscv/core/fivestage/ALU.scala 47:43] + node _io_result_T_8 = lt(_io_result_T_6, _io_result_T_7) @[src/main/scala/riscv/core/fivestage/ALU.scala 47:34] + io.result <= _io_result_T_8 @[src/main/scala/riscv/core/fivestage/ALU.scala 47:17] + else : + node _T_12 = asUInt(UInt<3>("h5")) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _T_13 = asUInt(io.func) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _T_14 = eq(_T_12, _T_13) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + when _T_14 : @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _io_result_T_9 = xor(io.op1, io.op2) @[src/main/scala/riscv/core/fivestage/ALU.scala 50:27] + io.result <= _io_result_T_9 @[src/main/scala/riscv/core/fivestage/ALU.scala 50:17] + else : + node _T_15 = asUInt(UInt<3>("h6")) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _T_16 = asUInt(io.func) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _T_17 = eq(_T_15, _T_16) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + when _T_17 : @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _io_result_T_10 = or(io.op1, io.op2) @[src/main/scala/riscv/core/fivestage/ALU.scala 53:27] + io.result <= _io_result_T_10 @[src/main/scala/riscv/core/fivestage/ALU.scala 53:17] + else : + node _T_18 = asUInt(UInt<3>("h7")) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _T_19 = asUInt(io.func) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _T_20 = eq(_T_18, _T_19) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + when _T_20 : @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _io_result_T_11 = and(io.op1, io.op2) @[src/main/scala/riscv/core/fivestage/ALU.scala 56:27] + io.result <= _io_result_T_11 @[src/main/scala/riscv/core/fivestage/ALU.scala 56:17] + else : + node _T_21 = asUInt(UInt<4>("h8")) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _T_22 = asUInt(io.func) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _T_23 = eq(_T_21, _T_22) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + when _T_23 : @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _io_result_T_12 = bits(io.op2, 4, 0) @[src/main/scala/riscv/core/fivestage/ALU.scala 59:36] + node _io_result_T_13 = dshr(io.op1, _io_result_T_12) @[src/main/scala/riscv/core/fivestage/ALU.scala 59:27] + io.result <= _io_result_T_13 @[src/main/scala/riscv/core/fivestage/ALU.scala 59:17] + else : + node _T_24 = asUInt(UInt<4>("h9")) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _T_25 = asUInt(io.func) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _T_26 = eq(_T_24, _T_25) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + when _T_26 : @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _io_result_T_14 = asSInt(io.op1) @[src/main/scala/riscv/core/fivestage/ALU.scala 62:28] + node _io_result_T_15 = bits(io.op2, 4, 0) @[src/main/scala/riscv/core/fivestage/ALU.scala 62:44] + node _io_result_T_16 = dshr(_io_result_T_14, _io_result_T_15) @[src/main/scala/riscv/core/fivestage/ALU.scala 62:35] + node _io_result_T_17 = asUInt(_io_result_T_16) @[src/main/scala/riscv/core/fivestage/ALU.scala 62:52] + io.result <= _io_result_T_17 @[src/main/scala/riscv/core/fivestage/ALU.scala 62:17] + else : + node _T_27 = asUInt(UInt<4>("ha")) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _T_28 = asUInt(io.func) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _T_29 = eq(_T_27, _T_28) @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + when _T_29 : @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19] + node _io_result_T_18 = lt(io.op1, io.op2) @[src/main/scala/riscv/core/fivestage/ALU.scala 65:27] + io.result <= _io_result_T_18 @[src/main/scala/riscv/core/fivestage/ALU.scala 65:17] + + + module ALUControl : + input clock : Clock + input reset : Reset + output io : { flip opcode : UInt<7>, flip funct3 : UInt<3>, flip funct7 : UInt<7>, alu_funct : UInt<4>} @[src/main/scala/riscv/core/fivestage/ALUControl.scala 21:14] + + io.alu_funct <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/ALUControl.scala 29:16] + node _T = eq(UInt<5>("h13"), io.opcode) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 31:21] + when _T : @[src/main/scala/riscv/core/fivestage/ALUControl.scala 31:21] + node _io_alu_funct_T = bits(io.funct7, 5, 5) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 42:49] + node _io_alu_funct_T_1 = mux(_io_alu_funct_T, UInt<4>("h9"), UInt<4>("h8")) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 42:39] + node _io_alu_funct_T_2 = eq(UInt<1>("h1"), io.funct3) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + node _io_alu_funct_T_3 = mux(_io_alu_funct_T_2, UInt<2>("h3"), UInt<1>("h1")) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + node _io_alu_funct_T_4 = eq(UInt<2>("h2"), io.funct3) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + node _io_alu_funct_T_5 = mux(_io_alu_funct_T_4, UInt<3>("h4"), _io_alu_funct_T_3) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + node _io_alu_funct_T_6 = eq(UInt<2>("h3"), io.funct3) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + node _io_alu_funct_T_7 = mux(_io_alu_funct_T_6, UInt<4>("ha"), _io_alu_funct_T_5) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + node _io_alu_funct_T_8 = eq(UInt<3>("h4"), io.funct3) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + node _io_alu_funct_T_9 = mux(_io_alu_funct_T_8, UInt<3>("h5"), _io_alu_funct_T_7) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + node _io_alu_funct_T_10 = eq(UInt<3>("h6"), io.funct3) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + node _io_alu_funct_T_11 = mux(_io_alu_funct_T_10, UInt<3>("h6"), _io_alu_funct_T_9) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + node _io_alu_funct_T_12 = eq(UInt<3>("h7"), io.funct3) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + node _io_alu_funct_T_13 = mux(_io_alu_funct_T_12, UInt<3>("h7"), _io_alu_funct_T_11) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + node _io_alu_funct_T_14 = eq(UInt<3>("h5"), io.funct3) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + node _io_alu_funct_T_15 = mux(_io_alu_funct_T_14, _io_alu_funct_T_1, _io_alu_funct_T_13) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + io.alu_funct <= _io_alu_funct_T_15 @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:20] + else : + node _T_1 = eq(UInt<6>("h33"), io.opcode) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 31:21] + when _T_1 : @[src/main/scala/riscv/core/fivestage/ALUControl.scala 31:21] + node _io_alu_funct_T_16 = bits(io.funct7, 5, 5) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 49:53] + node _io_alu_funct_T_17 = mux(_io_alu_funct_T_16, UInt<2>("h2"), UInt<1>("h1")) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 49:43] + node _io_alu_funct_T_18 = bits(io.funct7, 5, 5) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 56:48] + node _io_alu_funct_T_19 = mux(_io_alu_funct_T_18, UInt<4>("h9"), UInt<4>("h8")) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 56:38] + node _io_alu_funct_T_20 = eq(UInt<1>("h1"), io.funct3) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 47:62] + node _io_alu_funct_T_21 = mux(_io_alu_funct_T_20, UInt<2>("h3"), _io_alu_funct_T_17) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 47:62] + node _io_alu_funct_T_22 = eq(UInt<2>("h2"), io.funct3) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 47:62] + node _io_alu_funct_T_23 = mux(_io_alu_funct_T_22, UInt<3>("h4"), _io_alu_funct_T_21) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 47:62] + node _io_alu_funct_T_24 = eq(UInt<2>("h3"), io.funct3) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 47:62] + node _io_alu_funct_T_25 = mux(_io_alu_funct_T_24, UInt<4>("ha"), _io_alu_funct_T_23) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 47:62] + node _io_alu_funct_T_26 = eq(UInt<3>("h4"), io.funct3) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 47:62] + node _io_alu_funct_T_27 = mux(_io_alu_funct_T_26, UInt<3>("h5"), _io_alu_funct_T_25) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 47:62] + node _io_alu_funct_T_28 = eq(UInt<3>("h6"), io.funct3) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 47:62] + node _io_alu_funct_T_29 = mux(_io_alu_funct_T_28, UInt<3>("h6"), _io_alu_funct_T_27) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 47:62] + node _io_alu_funct_T_30 = eq(UInt<3>("h7"), io.funct3) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 47:62] + node _io_alu_funct_T_31 = mux(_io_alu_funct_T_30, UInt<3>("h7"), _io_alu_funct_T_29) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 47:62] + node _io_alu_funct_T_32 = eq(UInt<3>("h5"), io.funct3) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 47:62] + node _io_alu_funct_T_33 = mux(_io_alu_funct_T_32, _io_alu_funct_T_19, _io_alu_funct_T_31) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 47:62] + io.alu_funct <= _io_alu_funct_T_33 @[src/main/scala/riscv/core/fivestage/ALUControl.scala 47:20] + else : + node _T_2 = eq(UInt<7>("h63"), io.opcode) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 31:21] + when _T_2 : @[src/main/scala/riscv/core/fivestage/ALUControl.scala 31:21] + io.alu_funct <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/ALUControl.scala 61:20] + else : + node _T_3 = eq(UInt<2>("h3"), io.opcode) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 31:21] + when _T_3 : @[src/main/scala/riscv/core/fivestage/ALUControl.scala 31:21] + io.alu_funct <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/ALUControl.scala 64:20] + else : + node _T_4 = eq(UInt<6>("h23"), io.opcode) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 31:21] + when _T_4 : @[src/main/scala/riscv/core/fivestage/ALUControl.scala 31:21] + io.alu_funct <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/ALUControl.scala 67:20] + else : + node _T_5 = eq(UInt<7>("h6f"), io.opcode) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 31:21] + when _T_5 : @[src/main/scala/riscv/core/fivestage/ALUControl.scala 31:21] + io.alu_funct <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/ALUControl.scala 70:20] + else : + node _T_6 = eq(UInt<7>("h67"), io.opcode) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 31:21] + when _T_6 : @[src/main/scala/riscv/core/fivestage/ALUControl.scala 31:21] + io.alu_funct <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/ALUControl.scala 73:20] + else : + node _T_7 = eq(UInt<6>("h37"), io.opcode) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 31:21] + when _T_7 : @[src/main/scala/riscv/core/fivestage/ALUControl.scala 31:21] + io.alu_funct <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/ALUControl.scala 76:20] + else : + node _T_8 = eq(UInt<5>("h17"), io.opcode) @[src/main/scala/riscv/core/fivestage/ALUControl.scala 31:21] + when _T_8 : @[src/main/scala/riscv/core/fivestage/ALUControl.scala 31:21] + io.alu_funct <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/ALUControl.scala 79:20] + + + module Execute : + input clock : Clock + input reset : Reset + output io : { flip instruction : UInt<32>, flip instruction_address : UInt<32>, flip reg1_data : UInt<32>, flip reg2_data : UInt<32>, flip immediate : UInt<32>, flip aluop1_source : UInt<1>, flip aluop2_source : UInt<1>, flip csr_read_data : UInt<32>, flip forward_from_mem : UInt<32>, flip forward_from_wb : UInt<32>, flip reg1_forward : UInt<2>, flip reg2_forward : UInt<2>, mem_alu_result : UInt<32>, csr_write_data : UInt<32>} @[src/main/scala/riscv/core/fivestage/Execute.scala 26:14] + + node opcode = bits(io.instruction, 6, 0) @[src/main/scala/riscv/core/fivestage/Execute.scala 44:30] + node funct3 = bits(io.instruction, 14, 12) @[src/main/scala/riscv/core/fivestage/Execute.scala 45:30] + node funct7 = bits(io.instruction, 31, 25) @[src/main/scala/riscv/core/fivestage/Execute.scala 46:30] + node rd = bits(io.instruction, 11, 7) @[src/main/scala/riscv/core/fivestage/Execute.scala 47:26] + node uimm = bits(io.instruction, 19, 15) @[src/main/scala/riscv/core/fivestage/Execute.scala 48:28] + inst alu of ALU @[src/main/scala/riscv/core/fivestage/Execute.scala 50:19] + alu.clock <= clock + alu.reset <= reset + inst alu_ctrl of ALUControl @[src/main/scala/riscv/core/fivestage/Execute.scala 51:24] + alu_ctrl.clock <= clock + alu_ctrl.reset <= reset + alu_ctrl.io.opcode <= opcode @[src/main/scala/riscv/core/fivestage/Execute.scala 53:22] + alu_ctrl.io.funct3 <= funct3 @[src/main/scala/riscv/core/fivestage/Execute.scala 54:22] + alu_ctrl.io.funct7 <= funct7 @[src/main/scala/riscv/core/fivestage/Execute.scala 55:22] + alu.io.func <= alu_ctrl.io.alu_funct @[src/main/scala/riscv/core/fivestage/Execute.scala 56:15] + node _alu_io_op1_T = eq(io.aluop1_source, UInt<1>("h1")) @[src/main/scala/riscv/core/fivestage/Execute.scala 58:22] + node _alu_io_op1_T_1 = eq(UInt<2>("h1"), io.reg1_forward) @[src/main/scala/riscv/core/fivestage/Execute.scala 60:45] + node _alu_io_op1_T_2 = mux(_alu_io_op1_T_1, io.forward_from_mem, io.reg1_data) @[src/main/scala/riscv/core/fivestage/Execute.scala 60:45] + node _alu_io_op1_T_3 = eq(UInt<2>("h2"), io.reg1_forward) @[src/main/scala/riscv/core/fivestage/Execute.scala 60:45] + node _alu_io_op1_T_4 = mux(_alu_io_op1_T_3, io.forward_from_wb, _alu_io_op1_T_2) @[src/main/scala/riscv/core/fivestage/Execute.scala 60:45] + node _alu_io_op1_T_5 = mux(_alu_io_op1_T, io.instruction_address, _alu_io_op1_T_4) @[src/main/scala/riscv/core/fivestage/Execute.scala 57:20] + alu.io.op1 <= _alu_io_op1_T_5 @[src/main/scala/riscv/core/fivestage/Execute.scala 57:14] + node _alu_io_op2_T = eq(io.aluop2_source, UInt<1>("h1")) @[src/main/scala/riscv/core/fivestage/Execute.scala 68:22] + node _alu_io_op2_T_1 = eq(UInt<2>("h1"), io.reg2_forward) @[src/main/scala/riscv/core/fivestage/Execute.scala 70:45] + node _alu_io_op2_T_2 = mux(_alu_io_op2_T_1, io.forward_from_mem, io.reg2_data) @[src/main/scala/riscv/core/fivestage/Execute.scala 70:45] + node _alu_io_op2_T_3 = eq(UInt<2>("h2"), io.reg2_forward) @[src/main/scala/riscv/core/fivestage/Execute.scala 70:45] + node _alu_io_op2_T_4 = mux(_alu_io_op2_T_3, io.forward_from_wb, _alu_io_op2_T_2) @[src/main/scala/riscv/core/fivestage/Execute.scala 70:45] + node _alu_io_op2_T_5 = mux(_alu_io_op2_T, io.immediate, _alu_io_op2_T_4) @[src/main/scala/riscv/core/fivestage/Execute.scala 67:20] + alu.io.op2 <= _alu_io_op2_T_5 @[src/main/scala/riscv/core/fivestage/Execute.scala 67:14] + io.mem_alu_result <= alu.io.result @[src/main/scala/riscv/core/fivestage/Execute.scala 77:21] + node _io_csr_write_data_T = not(io.reg1_data) @[src/main/scala/riscv/core/fivestage/Execute.scala 80:54] + node _io_csr_write_data_T_1 = and(io.csr_read_data, _io_csr_write_data_T) @[src/main/scala/riscv/core/fivestage/Execute.scala 80:52] + node _io_csr_write_data_T_2 = or(io.csr_read_data, io.reg1_data) @[src/main/scala/riscv/core/fivestage/Execute.scala 81:52] + node _io_csr_write_data_T_3 = cat(UInt<27>("h0"), uimm) @[src/main/scala/riscv/core/fivestage/Execute.scala 82:38] + node _io_csr_write_data_T_4 = cat(UInt<27>("h0"), uimm) @[src/main/scala/riscv/core/fivestage/Execute.scala 83:59] + node _io_csr_write_data_T_5 = not(_io_csr_write_data_T_4) @[src/main/scala/riscv/core/fivestage/Execute.scala 83:55] + node _io_csr_write_data_T_6 = and(io.csr_read_data, _io_csr_write_data_T_5) @[src/main/scala/riscv/core/fivestage/Execute.scala 83:53] + node _io_csr_write_data_T_7 = cat(UInt<27>("h0"), uimm) @[src/main/scala/riscv/core/fivestage/Execute.scala 84:57] + node _io_csr_write_data_T_8 = or(io.csr_read_data, _io_csr_write_data_T_7) @[src/main/scala/riscv/core/fivestage/Execute.scala 84:53] + node _io_csr_write_data_T_9 = eq(UInt<1>("h1"), funct3) @[src/main/scala/riscv/core/fivestage/Execute.scala 78:46] + node _io_csr_write_data_T_10 = mux(_io_csr_write_data_T_9, io.reg1_data, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/Execute.scala 78:46] + node _io_csr_write_data_T_11 = eq(UInt<2>("h3"), funct3) @[src/main/scala/riscv/core/fivestage/Execute.scala 78:46] + node _io_csr_write_data_T_12 = mux(_io_csr_write_data_T_11, _io_csr_write_data_T_1, _io_csr_write_data_T_10) @[src/main/scala/riscv/core/fivestage/Execute.scala 78:46] + node _io_csr_write_data_T_13 = eq(UInt<2>("h2"), funct3) @[src/main/scala/riscv/core/fivestage/Execute.scala 78:46] + node _io_csr_write_data_T_14 = mux(_io_csr_write_data_T_13, _io_csr_write_data_T_2, _io_csr_write_data_T_12) @[src/main/scala/riscv/core/fivestage/Execute.scala 78:46] + node _io_csr_write_data_T_15 = eq(UInt<3>("h5"), funct3) @[src/main/scala/riscv/core/fivestage/Execute.scala 78:46] + node _io_csr_write_data_T_16 = mux(_io_csr_write_data_T_15, _io_csr_write_data_T_3, _io_csr_write_data_T_14) @[src/main/scala/riscv/core/fivestage/Execute.scala 78:46] + node _io_csr_write_data_T_17 = eq(UInt<3>("h7"), funct3) @[src/main/scala/riscv/core/fivestage/Execute.scala 78:46] + node _io_csr_write_data_T_18 = mux(_io_csr_write_data_T_17, _io_csr_write_data_T_6, _io_csr_write_data_T_16) @[src/main/scala/riscv/core/fivestage/Execute.scala 78:46] + node _io_csr_write_data_T_19 = eq(UInt<3>("h6"), funct3) @[src/main/scala/riscv/core/fivestage/Execute.scala 78:46] + node _io_csr_write_data_T_20 = mux(_io_csr_write_data_T_19, _io_csr_write_data_T_8, _io_csr_write_data_T_18) @[src/main/scala/riscv/core/fivestage/Execute.scala 78:46] + io.csr_write_data <= _io_csr_write_data_T_20 @[src/main/scala/riscv/core/fivestage/Execute.scala 78:21] + + module PipelineRegister_18 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<1>, out : UInt<1>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_19 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<2>, out : UInt<2>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<2>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_20 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<5>, out : UInt<5>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<5>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_21 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<32>, out : UInt<32>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_22 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<32>, out : UInt<32>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_23 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<32>, out : UInt<32>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_24 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<32>, out : UInt<32>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_25 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<32>, out : UInt<32>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_26 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<1>, out : UInt<1>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_27 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<1>, out : UInt<1>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_28 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<32>, out : UInt<32>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module EX2MEM : + input clock : Clock + input reset : Reset + output io : { flip stall_flag : UInt<1>, flip flush_enable : UInt<1>, flip regs_write_enable : UInt<1>, flip regs_write_source : UInt<2>, flip regs_write_address : UInt<32>, flip instruction_address : UInt<32>, flip instruction : UInt<32>, flip reg1_data : UInt<32>, flip reg2_data : UInt<32>, flip memory_read_enable : UInt<1>, flip memory_write_enable : UInt<1>, flip alu_result : UInt<32>, flip csr_read_data : UInt<32>, output_regs_write_enable : UInt<1>, output_regs_write_source : UInt<2>, output_regs_write_address : UInt<32>, output_instruction_address : UInt<32>, output_instruction : UInt<32>, output_reg1_data : UInt<32>, output_reg2_data : UInt<32>, output_memory_read_enable : UInt<1>, output_memory_write_enable : UInt<1>, output_alu_result : UInt<32>, output_csr_read_data : UInt<32>} @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 21:14] + + node write_enable = eq(io.stall_flag, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 48:22] + inst regs_write_enable of PipelineRegister_18 @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 50:33] + regs_write_enable.clock <= clock + regs_write_enable.reset <= reset + regs_write_enable.io.in <= io.regs_write_enable @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 51:27] + regs_write_enable.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 52:37] + regs_write_enable.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 53:37] + io.output_regs_write_enable <= regs_write_enable.io.out @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 54:31] + inst regs_write_source of PipelineRegister_19 @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 56:33] + regs_write_source.clock <= clock + regs_write_source.reset <= reset + regs_write_source.io.in <= io.regs_write_source @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 57:27] + regs_write_source.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 58:37] + regs_write_source.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 59:37] + io.output_regs_write_source <= regs_write_source.io.out @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 60:31] + inst regs_write_address of PipelineRegister_20 @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 62:34] + regs_write_address.clock <= clock + regs_write_address.reset <= reset + regs_write_address.io.in <= io.regs_write_address @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 63:28] + regs_write_address.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 64:38] + regs_write_address.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 65:38] + io.output_regs_write_address <= regs_write_address.io.out @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 66:32] + inst instruction_address of PipelineRegister_21 @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 68:35] + instruction_address.clock <= clock + instruction_address.reset <= reset + instruction_address.io.in <= io.instruction_address @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 69:29] + instruction_address.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 70:39] + instruction_address.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 71:39] + io.output_instruction_address <= instruction_address.io.out @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 72:33] + inst instruction of PipelineRegister_22 @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 74:27] + instruction.clock <= clock + instruction.reset <= reset + instruction.io.in <= io.instruction @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 75:21] + instruction.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 76:31] + instruction.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 77:31] + io.output_instruction <= instruction.io.out @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 78:25] + inst reg1_data of PipelineRegister_23 @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 80:25] + reg1_data.clock <= clock + reg1_data.reset <= reset + reg1_data.io.in <= io.reg1_data @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 81:19] + reg1_data.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 82:29] + reg1_data.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 83:29] + io.output_reg1_data <= reg1_data.io.out @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 84:23] + inst reg2_data of PipelineRegister_24 @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 86:25] + reg2_data.clock <= clock + reg2_data.reset <= reset + reg2_data.io.in <= io.reg2_data @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 87:19] + reg2_data.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 88:29] + reg2_data.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 89:29] + io.output_reg2_data <= reg2_data.io.out @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 90:23] + inst alu_result of PipelineRegister_25 @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 92:26] + alu_result.clock <= clock + alu_result.reset <= reset + alu_result.io.in <= io.alu_result @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 93:20] + alu_result.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 94:30] + alu_result.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 95:30] + io.output_alu_result <= alu_result.io.out @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 96:24] + inst memory_read_enable of PipelineRegister_26 @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 98:34] + memory_read_enable.clock <= clock + memory_read_enable.reset <= reset + memory_read_enable.io.in <= io.memory_read_enable @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 99:28] + memory_read_enable.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 100:38] + memory_read_enable.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 101:38] + io.output_memory_read_enable <= memory_read_enable.io.out @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 102:32] + inst memory_write_enable of PipelineRegister_27 @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 104:35] + memory_write_enable.clock <= clock + memory_write_enable.reset <= reset + memory_write_enable.io.in <= io.memory_write_enable @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 105:29] + memory_write_enable.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 106:39] + memory_write_enable.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 107:39] + io.output_memory_write_enable <= memory_write_enable.io.out @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 108:33] + inst csr_read_data of PipelineRegister_28 @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 110:29] + csr_read_data.clock <= clock + csr_read_data.reset <= reset + csr_read_data.io.in <= io.csr_read_data @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 111:23] + csr_read_data.io.write_enable <= write_enable @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 112:33] + csr_read_data.io.flush_enable <= io.flush_enable @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 113:33] + io.output_csr_read_data <= csr_read_data.io.out @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 114:27] + + module MemoryAccess : + input clock : Clock + input reset : Reset + output io : { flip alu_result : UInt<32>, flip reg2_data : UInt<32>, flip memory_read_enable : UInt<1>, flip memory_write_enable : UInt<1>, flip funct3 : UInt<3>, flip regs_write_source : UInt<2>, flip csr_read_data : UInt<32>, flip clint_exception_token : UInt<1>, wb_memory_read_data : UInt<32>, ctrl_stall_flag : UInt<1>, forward_data : UInt<32>, flip physical_address : UInt<32>, bus : { read : UInt<1>, address : UInt<32>, flip read_data : UInt<32>, flip read_valid : UInt<1>, write : UInt<1>, write_data : UInt<32>, write_strobe : UInt<1>[4], flip write_valid : UInt<1>, flip busy : UInt<1>, request : UInt<1>, flip granted : UInt<1>}} @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 23:14] + + node mem_address_index = bits(io.physical_address, 1, 0) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 41:46] + reg mem_access_state : UInt<2>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 42:33] + io.bus.request <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 49:18] + io.bus.read <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 50:15] + io.bus.address <= io.physical_address @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 51:18] + io.bus.write_data <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 52:21] + wire _WIRE : UInt<1>[4] @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 53:33] + _WIRE[0] <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 53:33] + _WIRE[1] <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 53:33] + _WIRE[2] <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 53:33] + _WIRE[3] <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 53:33] + io.bus.write_strobe <= _WIRE @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 53:23] + io.bus.write <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 54:16] + io.wb_memory_read_data <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 55:26] + io.ctrl_stall_flag <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 56:22] + when io.clint_exception_token : @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 58:34] + io.bus.request <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 59:20] + io.ctrl_stall_flag <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 60:24] + else : + when io.memory_read_enable : @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 61:37] + node _T = eq(mem_access_state, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 62:27] + when _T : @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 62:56] + io.ctrl_stall_flag <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 64:26] + io.bus.read <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 65:19] + io.bus.request <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 66:22] + when io.bus.granted : @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 67:28] + io.bus.address <= io.physical_address @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 68:24] + io.bus.read <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 69:21] + mem_access_state <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 70:26] + else : + node _T_1 = eq(mem_access_state, UInt<1>("h1")) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 72:33] + when _T_1 : @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 72:62] + io.bus.request <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 73:22] + io.bus.read <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 74:19] + io.ctrl_stall_flag <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 75:26] + when io.bus.read_valid : @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 76:31] + node _io_wb_memory_read_data_T = bits(io.bus.read_data, 31, 31) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 80:83] + node _io_wb_memory_read_data_T_1 = bits(_io_wb_memory_read_data_T, 0, 0) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 80:74] + node _io_wb_memory_read_data_T_2 = mux(_io_wb_memory_read_data_T_1, UInt<24>("hffffff"), UInt<24>("h0")) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 80:74] + node _io_wb_memory_read_data_T_3 = bits(io.bus.read_data, 31, 24) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 80:94] + node _io_wb_memory_read_data_T_4 = cat(_io_wb_memory_read_data_T_2, _io_wb_memory_read_data_T_3) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 80:69] + node _io_wb_memory_read_data_T_5 = bits(io.bus.read_data, 7, 7) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 82:41] + node _io_wb_memory_read_data_T_6 = bits(_io_wb_memory_read_data_T_5, 0, 0) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 82:32] + node _io_wb_memory_read_data_T_7 = mux(_io_wb_memory_read_data_T_6, UInt<24>("hffffff"), UInt<24>("h0")) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 82:32] + node _io_wb_memory_read_data_T_8 = bits(io.bus.read_data, 7, 0) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 82:51] + node _io_wb_memory_read_data_T_9 = cat(_io_wb_memory_read_data_T_7, _io_wb_memory_read_data_T_8) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 82:27] + node _io_wb_memory_read_data_T_10 = bits(io.bus.read_data, 15, 15) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 83:41] + node _io_wb_memory_read_data_T_11 = bits(_io_wb_memory_read_data_T_10, 0, 0) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 83:32] + node _io_wb_memory_read_data_T_12 = mux(_io_wb_memory_read_data_T_11, UInt<24>("hffffff"), UInt<24>("h0")) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 83:32] + node _io_wb_memory_read_data_T_13 = bits(io.bus.read_data, 15, 8) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 83:52] + node _io_wb_memory_read_data_T_14 = cat(_io_wb_memory_read_data_T_12, _io_wb_memory_read_data_T_13) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 83:27] + node _io_wb_memory_read_data_T_15 = bits(io.bus.read_data, 23, 23) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 84:41] + node _io_wb_memory_read_data_T_16 = bits(_io_wb_memory_read_data_T_15, 0, 0) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 84:32] + node _io_wb_memory_read_data_T_17 = mux(_io_wb_memory_read_data_T_16, UInt<24>("hffffff"), UInt<24>("h0")) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 84:32] + node _io_wb_memory_read_data_T_18 = bits(io.bus.read_data, 23, 16) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 84:52] + node _io_wb_memory_read_data_T_19 = cat(_io_wb_memory_read_data_T_17, _io_wb_memory_read_data_T_18) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 84:27] + node _io_wb_memory_read_data_T_20 = eq(UInt<1>("h0"), mem_address_index) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 80:104] + node _io_wb_memory_read_data_T_21 = mux(_io_wb_memory_read_data_T_20, _io_wb_memory_read_data_T_9, _io_wb_memory_read_data_T_4) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 80:104] + node _io_wb_memory_read_data_T_22 = eq(UInt<1>("h1"), mem_address_index) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 80:104] + node _io_wb_memory_read_data_T_23 = mux(_io_wb_memory_read_data_T_22, _io_wb_memory_read_data_T_14, _io_wb_memory_read_data_T_21) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 80:104] + node _io_wb_memory_read_data_T_24 = eq(UInt<2>("h2"), mem_address_index) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 80:104] + node _io_wb_memory_read_data_T_25 = mux(_io_wb_memory_read_data_T_24, _io_wb_memory_read_data_T_19, _io_wb_memory_read_data_T_23) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 80:104] + node _io_wb_memory_read_data_T_26 = mux(UInt<1>("h0"), UInt<24>("hffffff"), UInt<24>("h0")) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 87:75] + node _io_wb_memory_read_data_T_27 = bits(io.bus.read_data, 31, 24) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 87:90] + node _io_wb_memory_read_data_T_28 = cat(_io_wb_memory_read_data_T_26, _io_wb_memory_read_data_T_27) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 87:70] + node _io_wb_memory_read_data_T_29 = mux(UInt<1>("h0"), UInt<24>("hffffff"), UInt<24>("h0")) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 89:32] + node _io_wb_memory_read_data_T_30 = bits(io.bus.read_data, 7, 0) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 89:47] + node _io_wb_memory_read_data_T_31 = cat(_io_wb_memory_read_data_T_29, _io_wb_memory_read_data_T_30) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 89:27] + node _io_wb_memory_read_data_T_32 = mux(UInt<1>("h0"), UInt<24>("hffffff"), UInt<24>("h0")) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 90:32] + node _io_wb_memory_read_data_T_33 = bits(io.bus.read_data, 15, 8) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 90:47] + node _io_wb_memory_read_data_T_34 = cat(_io_wb_memory_read_data_T_32, _io_wb_memory_read_data_T_33) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 90:27] + node _io_wb_memory_read_data_T_35 = mux(UInt<1>("h0"), UInt<24>("hffffff"), UInt<24>("h0")) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 91:32] + node _io_wb_memory_read_data_T_36 = bits(io.bus.read_data, 23, 16) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 91:47] + node _io_wb_memory_read_data_T_37 = cat(_io_wb_memory_read_data_T_35, _io_wb_memory_read_data_T_36) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 91:27] + node _io_wb_memory_read_data_T_38 = eq(UInt<1>("h0"), mem_address_index) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 87:100] + node _io_wb_memory_read_data_T_39 = mux(_io_wb_memory_read_data_T_38, _io_wb_memory_read_data_T_31, _io_wb_memory_read_data_T_28) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 87:100] + node _io_wb_memory_read_data_T_40 = eq(UInt<1>("h1"), mem_address_index) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 87:100] + node _io_wb_memory_read_data_T_41 = mux(_io_wb_memory_read_data_T_40, _io_wb_memory_read_data_T_34, _io_wb_memory_read_data_T_39) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 87:100] + node _io_wb_memory_read_data_T_42 = eq(UInt<2>("h2"), mem_address_index) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 87:100] + node _io_wb_memory_read_data_T_43 = mux(_io_wb_memory_read_data_T_42, _io_wb_memory_read_data_T_37, _io_wb_memory_read_data_T_41) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 87:100] + node _io_wb_memory_read_data_T_44 = eq(mem_address_index, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 95:33] + node _io_wb_memory_read_data_T_45 = bits(io.bus.read_data, 15, 15) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 96:32] + node _io_wb_memory_read_data_T_46 = bits(_io_wb_memory_read_data_T_45, 0, 0) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 96:23] + node _io_wb_memory_read_data_T_47 = mux(_io_wb_memory_read_data_T_46, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 96:23] + node _io_wb_memory_read_data_T_48 = bits(io.bus.read_data, 15, 0) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 96:43] + node _io_wb_memory_read_data_T_49 = cat(_io_wb_memory_read_data_T_47, _io_wb_memory_read_data_T_48) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 96:18] + node _io_wb_memory_read_data_T_50 = bits(io.bus.read_data, 31, 31) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 97:32] + node _io_wb_memory_read_data_T_51 = bits(_io_wb_memory_read_data_T_50, 0, 0) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 97:23] + node _io_wb_memory_read_data_T_52 = mux(_io_wb_memory_read_data_T_51, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 97:23] + node _io_wb_memory_read_data_T_53 = bits(io.bus.read_data, 31, 16) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 97:43] + node _io_wb_memory_read_data_T_54 = cat(_io_wb_memory_read_data_T_52, _io_wb_memory_read_data_T_53) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 97:18] + node _io_wb_memory_read_data_T_55 = mux(_io_wb_memory_read_data_T_44, _io_wb_memory_read_data_T_49, _io_wb_memory_read_data_T_54) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 94:40] + node _io_wb_memory_read_data_T_56 = eq(mem_address_index, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 100:33] + node _io_wb_memory_read_data_T_57 = mux(UInt<1>("h0"), UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 101:23] + node _io_wb_memory_read_data_T_58 = bits(io.bus.read_data, 15, 0) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 101:38] + node _io_wb_memory_read_data_T_59 = cat(_io_wb_memory_read_data_T_57, _io_wb_memory_read_data_T_58) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 101:18] + node _io_wb_memory_read_data_T_60 = mux(UInt<1>("h0"), UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 102:23] + node _io_wb_memory_read_data_T_61 = bits(io.bus.read_data, 31, 16) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 102:38] + node _io_wb_memory_read_data_T_62 = cat(_io_wb_memory_read_data_T_60, _io_wb_memory_read_data_T_61) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 102:18] + node _io_wb_memory_read_data_T_63 = mux(_io_wb_memory_read_data_T_56, _io_wb_memory_read_data_T_59, _io_wb_memory_read_data_T_62) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 99:41] + node _io_wb_memory_read_data_T_64 = eq(UInt<1>("h0"), io.funct3) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 78:60] + node _io_wb_memory_read_data_T_65 = mux(_io_wb_memory_read_data_T_64, _io_wb_memory_read_data_T_25, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 78:60] + node _io_wb_memory_read_data_T_66 = eq(UInt<3>("h4"), io.funct3) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 78:60] + node _io_wb_memory_read_data_T_67 = mux(_io_wb_memory_read_data_T_66, _io_wb_memory_read_data_T_43, _io_wb_memory_read_data_T_65) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 78:60] + node _io_wb_memory_read_data_T_68 = eq(UInt<1>("h1"), io.funct3) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 78:60] + node _io_wb_memory_read_data_T_69 = mux(_io_wb_memory_read_data_T_68, _io_wb_memory_read_data_T_55, _io_wb_memory_read_data_T_67) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 78:60] + node _io_wb_memory_read_data_T_70 = eq(UInt<3>("h5"), io.funct3) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 78:60] + node _io_wb_memory_read_data_T_71 = mux(_io_wb_memory_read_data_T_70, _io_wb_memory_read_data_T_63, _io_wb_memory_read_data_T_69) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 78:60] + node _io_wb_memory_read_data_T_72 = eq(UInt<2>("h2"), io.funct3) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 78:60] + node _io_wb_memory_read_data_T_73 = mux(_io_wb_memory_read_data_T_72, io.bus.read_data, _io_wb_memory_read_data_T_71) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 78:60] + io.wb_memory_read_data <= _io_wb_memory_read_data_T_73 @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 78:32] + mem_access_state <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 45:22] + io.ctrl_stall_flag <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 46:24] + else : + when io.memory_write_enable : @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 110:38] + node _T_2 = eq(mem_access_state, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 111:27] + when _T_2 : @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 111:56] + io.ctrl_stall_flag <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 113:26] + io.bus.write_data <= io.reg2_data @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 114:25] + wire _WIRE_1 : UInt<1>[4] @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 115:37] + _WIRE_1[0] <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 115:37] + _WIRE_1[1] <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 115:37] + _WIRE_1[2] <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 115:37] + _WIRE_1[3] <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 115:37] + io.bus.write_strobe <= _WIRE_1 @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 115:27] + node _T_3 = eq(io.funct3, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 116:22] + when _T_3 : @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 116:48] + io.bus.write_strobe[mem_address_index] <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 117:48] + node _io_bus_write_data_T = bits(io.reg2_data, 8, 0) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 118:42] + node _io_bus_write_data_T_1 = dshl(mem_address_index, UInt<2>("h3")) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 118:89] + node _io_bus_write_data_T_2 = dshl(_io_bus_write_data_T, _io_bus_write_data_T_1) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 118:67] + io.bus.write_data <= _io_bus_write_data_T_2 @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 118:27] + else : + node _T_4 = eq(io.funct3, UInt<1>("h1")) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 120:28] + when _T_4 : @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 120:54] + node _T_5 = eq(mem_address_index, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 121:32] + when _T_5 : @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 121:41] + io.bus.write_strobe[0] <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 123:36] + io.bus.write_strobe[1] <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 123:36] + node _io_bus_write_data_T_3 = bits(io.reg2_data, 16, 0) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 125:44] + io.bus.write_data <= _io_bus_write_data_T_3 @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 125:29] + else : + io.bus.write_strobe[2] <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 128:36] + io.bus.write_strobe[3] <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 128:36] + node _io_bus_write_data_T_4 = bits(io.reg2_data, 16, 0) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 130:44] + node _io_bus_write_data_T_5 = shl(_io_bus_write_data_T_4, 16) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 130:95] + io.bus.write_data <= _io_bus_write_data_T_5 @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 130:29] + else : + node _T_6 = eq(io.funct3, UInt<2>("h2")) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 133:28] + when _T_6 : @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 133:54] + io.bus.write_strobe[0] <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 135:34] + io.bus.write_strobe[1] <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 135:34] + io.bus.write_strobe[2] <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 135:34] + io.bus.write_strobe[3] <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 135:34] + io.bus.request <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 138:22] + when io.bus.granted : @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 139:28] + io.bus.write <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 140:22] + mem_access_state <= UInt<2>("h2") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 141:26] + else : + node _T_7 = eq(mem_access_state, UInt<2>("h2")) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 143:33] + when _T_7 : @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 143:63] + io.bus.request <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 144:22] + io.ctrl_stall_flag <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 145:26] + io.bus.write <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 146:20] + when io.bus.write_valid : @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 147:32] + mem_access_state <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 45:22] + io.ctrl_stall_flag <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 46:24] + node _io_forward_data_T = eq(io.regs_write_source, UInt<2>("h2")) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 153:47] + node _io_forward_data_T_1 = mux(_io_forward_data_T, io.csr_read_data, io.alu_result) @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 153:25] + io.forward_data <= _io_forward_data_T_1 @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 153:19] + + module PipelineRegister_29 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<32>, out : UInt<32>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_30 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<32>, out : UInt<32>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_31 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<1>, out : UInt<1>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_32 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<2>, out : UInt<2>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<2>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_33 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<5>, out : UInt<5>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<5>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_34 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<32>, out : UInt<32>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module PipelineRegister_35 : + input clock : Clock + input reset : Reset + output io : { flip write_enable : UInt<1>, flip flush_enable : UInt<1>, flip in : UInt<32>, out : UInt<32>} @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + + reg reg : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + when io.write_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg <= io.in @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + else : + when io.flush_enable : @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + io.out <= reg @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + + module MEM2WB : + input clock : Clock + input reset : Reset + output io : { flip instruction_address : UInt<32>, flip alu_result : UInt<32>, flip regs_write_enable : UInt<1>, flip regs_write_source : UInt<2>, flip regs_write_address : UInt<32>, flip memory_read_data : UInt<32>, flip csr_read_data : UInt<32>, output_instruction_address : UInt<32>, output_alu_result : UInt<32>, output_regs_write_enable : UInt<1>, output_regs_write_source : UInt<2>, output_regs_write_address : UInt<32>, output_memory_read_data : UInt<32>, output_csr_read_data : UInt<32>} @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 21:14] + + inst alu_result of PipelineRegister_29 @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 41:26] + alu_result.clock <= clock + alu_result.reset <= reset + alu_result.io.in <= io.alu_result @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 42:20] + alu_result.io.write_enable <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 43:30] + alu_result.io.flush_enable <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 44:30] + io.output_alu_result <= alu_result.io.out @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 45:24] + inst memory_read_data of PipelineRegister_30 @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 47:32] + memory_read_data.clock <= clock + memory_read_data.reset <= reset + memory_read_data.io.in <= io.memory_read_data @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 48:26] + memory_read_data.io.write_enable <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 49:36] + memory_read_data.io.flush_enable <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 50:36] + io.output_memory_read_data <= memory_read_data.io.out @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 51:30] + inst regs_write_enable of PipelineRegister_31 @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 53:33] + regs_write_enable.clock <= clock + regs_write_enable.reset <= reset + regs_write_enable.io.in <= io.regs_write_enable @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 54:27] + regs_write_enable.io.write_enable <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 55:37] + regs_write_enable.io.flush_enable <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 56:37] + io.output_regs_write_enable <= regs_write_enable.io.out @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 57:31] + inst regs_write_source of PipelineRegister_32 @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 59:33] + regs_write_source.clock <= clock + regs_write_source.reset <= reset + regs_write_source.io.in <= io.regs_write_source @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 60:27] + regs_write_source.io.write_enable <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 61:37] + regs_write_source.io.flush_enable <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 62:37] + io.output_regs_write_source <= regs_write_source.io.out @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 63:31] + inst regs_write_address of PipelineRegister_33 @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 65:34] + regs_write_address.clock <= clock + regs_write_address.reset <= reset + regs_write_address.io.in <= io.regs_write_address @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 66:28] + regs_write_address.io.write_enable <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 67:38] + regs_write_address.io.flush_enable <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 68:38] + io.output_regs_write_address <= regs_write_address.io.out @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 69:32] + inst instruction_address of PipelineRegister_34 @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 71:35] + instruction_address.clock <= clock + instruction_address.reset <= reset + instruction_address.io.in <= io.instruction_address @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 72:29] + instruction_address.io.write_enable <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 73:39] + instruction_address.io.flush_enable <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 74:39] + io.output_instruction_address <= instruction_address.io.out @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 75:33] + inst csr_read_data of PipelineRegister_35 @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 77:29] + csr_read_data.clock <= clock + csr_read_data.reset <= reset + csr_read_data.io.in <= io.csr_read_data @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 78:23] + csr_read_data.io.write_enable <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 79:33] + csr_read_data.io.flush_enable <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 80:33] + io.output_csr_read_data <= csr_read_data.io.out @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 81:27] + + module WriteBack : + input clock : Clock + input reset : Reset + output io : { flip instruction_address : UInt<32>, flip alu_result : UInt<32>, flip memory_read_data : UInt<32>, flip regs_write_source : UInt<2>, flip csr_read_data : UInt<32>, regs_write_data : UInt<32>} @[src/main/scala/riscv/core/fivestage/WriteBack.scala 22:14] + + node _io_regs_write_data_T = add(io.instruction_address, UInt<3>("h4")) @[src/main/scala/riscv/core/fivestage/WriteBack.scala 35:72] + node _io_regs_write_data_T_1 = tail(_io_regs_write_data_T, 1) @[src/main/scala/riscv/core/fivestage/WriteBack.scala 35:72] + node _io_regs_write_data_T_2 = eq(UInt<2>("h1"), io.regs_write_source) @[src/main/scala/riscv/core/fivestage/WriteBack.scala 31:71] + node _io_regs_write_data_T_3 = mux(_io_regs_write_data_T_2, io.memory_read_data, io.alu_result) @[src/main/scala/riscv/core/fivestage/WriteBack.scala 31:71] + node _io_regs_write_data_T_4 = eq(UInt<2>("h2"), io.regs_write_source) @[src/main/scala/riscv/core/fivestage/WriteBack.scala 31:71] + node _io_regs_write_data_T_5 = mux(_io_regs_write_data_T_4, io.csr_read_data, _io_regs_write_data_T_3) @[src/main/scala/riscv/core/fivestage/WriteBack.scala 31:71] + node _io_regs_write_data_T_6 = eq(UInt<2>("h3"), io.regs_write_source) @[src/main/scala/riscv/core/fivestage/WriteBack.scala 31:71] + node _io_regs_write_data_T_7 = mux(_io_regs_write_data_T_6, _io_regs_write_data_T_1, _io_regs_write_data_T_5) @[src/main/scala/riscv/core/fivestage/WriteBack.scala 31:71] + io.regs_write_data <= _io_regs_write_data_T_7 @[src/main/scala/riscv/core/fivestage/WriteBack.scala 31:22] + + module Forwarding : + input clock : Clock + input reset : Reset + output io : { flip rs1_id : UInt<5>, flip rs2_id : UInt<5>, flip rs1_ex : UInt<5>, flip rs2_ex : UInt<5>, flip rd_mem : UInt<5>, flip reg_write_enable_mem : UInt<1>, flip rd_wb : UInt<5>, flip reg_write_enable_wb : UInt<1>, reg1_forward_id : UInt<2>, reg2_forward_id : UInt<2>, reg1_forward_ex : UInt<2>, reg2_forward_ex : UInt<2>} @[src/main/scala/riscv/core/fivestage/Forwarding.scala 27:14] + + node _T = neq(io.rd_mem, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 43:45] + node _T_1 = and(io.reg_write_enable_mem, _T) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 43:32] + node _T_2 = eq(io.rd_mem, io.rs1_id) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 43:66] + node _T_3 = and(_T_1, _T_2) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 43:53] + when _T_3 : @[src/main/scala/riscv/core/fivestage/Forwarding.scala 43:81] + io.reg1_forward_id <= UInt<2>("h1") @[src/main/scala/riscv/core/fivestage/Forwarding.scala 44:24] + else : + node _T_4 = neq(io.rd_wb, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 45:49] + node _T_5 = and(io.reg_write_enable_wb, _T_4) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 45:37] + node _T_6 = eq(io.rd_wb, io.rs1_id) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 45:69] + node _T_7 = and(_T_5, _T_6) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 45:57] + when _T_7 : @[src/main/scala/riscv/core/fivestage/Forwarding.scala 45:84] + io.reg1_forward_id <= UInt<2>("h2") @[src/main/scala/riscv/core/fivestage/Forwarding.scala 46:24] + else : + io.reg1_forward_id <= UInt<2>("h0") @[src/main/scala/riscv/core/fivestage/Forwarding.scala 48:24] + node _T_8 = neq(io.rd_mem, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 51:45] + node _T_9 = and(io.reg_write_enable_mem, _T_8) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 51:32] + node _T_10 = eq(io.rd_mem, io.rs2_id) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 51:66] + node _T_11 = and(_T_9, _T_10) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 51:53] + when _T_11 : @[src/main/scala/riscv/core/fivestage/Forwarding.scala 51:81] + io.reg2_forward_id <= UInt<2>("h1") @[src/main/scala/riscv/core/fivestage/Forwarding.scala 52:24] + else : + node _T_12 = neq(io.rd_wb, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 53:49] + node _T_13 = and(io.reg_write_enable_wb, _T_12) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 53:37] + node _T_14 = eq(io.rd_wb, io.rs2_id) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 53:69] + node _T_15 = and(_T_13, _T_14) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 53:57] + when _T_15 : @[src/main/scala/riscv/core/fivestage/Forwarding.scala 53:84] + io.reg2_forward_id <= UInt<2>("h2") @[src/main/scala/riscv/core/fivestage/Forwarding.scala 54:24] + else : + io.reg2_forward_id <= UInt<2>("h0") @[src/main/scala/riscv/core/fivestage/Forwarding.scala 56:24] + node _T_16 = neq(io.rd_mem, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 59:45] + node _T_17 = and(io.reg_write_enable_mem, _T_16) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 59:32] + node _T_18 = eq(io.rd_mem, io.rs1_ex) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 59:66] + node _T_19 = and(_T_17, _T_18) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 59:53] + when _T_19 : @[src/main/scala/riscv/core/fivestage/Forwarding.scala 59:81] + io.reg1_forward_ex <= UInt<2>("h1") @[src/main/scala/riscv/core/fivestage/Forwarding.scala 60:24] + else : + node _T_20 = neq(io.rd_wb, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 61:49] + node _T_21 = and(io.reg_write_enable_wb, _T_20) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 61:37] + node _T_22 = eq(io.rd_wb, io.rs1_ex) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 61:69] + node _T_23 = and(_T_21, _T_22) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 61:57] + when _T_23 : @[src/main/scala/riscv/core/fivestage/Forwarding.scala 61:84] + io.reg1_forward_ex <= UInt<2>("h2") @[src/main/scala/riscv/core/fivestage/Forwarding.scala 62:24] + else : + io.reg1_forward_ex <= UInt<2>("h0") @[src/main/scala/riscv/core/fivestage/Forwarding.scala 64:24] + node _T_24 = neq(io.rd_mem, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 67:45] + node _T_25 = and(io.reg_write_enable_mem, _T_24) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 67:32] + node _T_26 = eq(io.rd_mem, io.rs2_ex) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 67:66] + node _T_27 = and(_T_25, _T_26) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 67:53] + when _T_27 : @[src/main/scala/riscv/core/fivestage/Forwarding.scala 67:81] + io.reg2_forward_ex <= UInt<2>("h1") @[src/main/scala/riscv/core/fivestage/Forwarding.scala 68:24] + else : + node _T_28 = neq(io.rd_wb, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 69:49] + node _T_29 = and(io.reg_write_enable_wb, _T_28) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 69:37] + node _T_30 = eq(io.rd_wb, io.rs2_ex) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 69:69] + node _T_31 = and(_T_29, _T_30) @[src/main/scala/riscv/core/fivestage/Forwarding.scala 69:57] + when _T_31 : @[src/main/scala/riscv/core/fivestage/Forwarding.scala 69:84] + io.reg2_forward_ex <= UInt<2>("h2") @[src/main/scala/riscv/core/fivestage/Forwarding.scala 70:24] + else : + io.reg2_forward_ex <= UInt<2>("h0") @[src/main/scala/riscv/core/fivestage/Forwarding.scala 72:24] + + + module CLINT : + input clock : Clock + input reset : Reset + output io : { flip interrupt_flag : UInt<32>, flip instruction : UInt<32>, flip instruction_address_if : UInt<32>, flip exception_signal : UInt<1>, flip instruction_address_cause_exception : UInt<32>, flip exception_cause : UInt<32>, flip exception_val : UInt<32>, exception_token : UInt<1>, flip jump_flag : UInt<1>, flip jump_address : UInt<32>, flip csr_mtvec : UInt<32>, flip csr_mepc : UInt<32>, flip csr_mstatus : UInt<32>, flip interrupt_enable : UInt<1>, ctrl_stall_flag : UInt<1>, csr_reg_write_enable : UInt<1>, csr_reg_write_address : UInt<12>, csr_reg_write_data : UInt<32>, id_interrupt_handler_address : UInt<32>, id_interrupt_assert : UInt<1>} @[src/main/scala/riscv/core/fivestage/CLINT.scala 49:14] + + wire interrupt_state : UInt @[src/main/scala/riscv/core/fivestage/CLINT.scala 86:33] + interrupt_state <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/CLINT.scala 86:33] + reg csr_state : UInt, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 87:26] + reg instruction_address : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 88:36] + reg cause : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 89:22] + reg trap_val : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 90:25] + reg interrupt_assert : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 91:33] + reg interrupt_handler_address : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 92:42] + reg csr_reg_write_enable : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 93:37] + reg csr_reg_write_address : UInt<12>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 94:38] + reg csr_reg_write_data : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 95:35] + reg exception_token : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 96:32] + reg exception_signal : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 97:33] + node _io_ctrl_stall_flag_T = neq(interrupt_state, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 98:42] + node _io_ctrl_stall_flag_T_1 = neq(csr_state, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 98:79] + node _io_ctrl_stall_flag_T_2 = or(_io_ctrl_stall_flag_T, _io_ctrl_stall_flag_T_1) @[src/main/scala/riscv/core/fivestage/CLINT.scala 98:66] + node _io_ctrl_stall_flag_T_3 = eq(exception_token, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 98:101] + node _io_ctrl_stall_flag_T_4 = and(_io_ctrl_stall_flag_T_2, _io_ctrl_stall_flag_T_3) @[src/main/scala/riscv/core/fivestage/CLINT.scala 98:98] + io.ctrl_stall_flag <= _io_ctrl_stall_flag_T_4 @[src/main/scala/riscv/core/fivestage/CLINT.scala 98:22] + io.exception_token <= exception_token @[src/main/scala/riscv/core/fivestage/CLINT.scala 99:22] + node _T = eq(csr_state, UInt<3>("h4")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 101:38] + node _T_1 = and(exception_signal, _T) @[src/main/scala/riscv/core/fivestage/CLINT.scala 101:25] + when _T_1 : @[src/main/scala/riscv/core/fivestage/CLINT.scala 101:59] + exception_token <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/CLINT.scala 102:21] + else : + exception_token <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/CLINT.scala 104:21] + when exception_token : @[src/main/scala/riscv/core/fivestage/CLINT.scala 107:25] + exception_signal <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/CLINT.scala 108:22] + else : + node _T_2 = eq(exception_signal, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 109:31] + node _T_3 = and(_T_2, io.exception_signal) @[src/main/scala/riscv/core/fivestage/CLINT.scala 109:43] + when _T_3 : @[src/main/scala/riscv/core/fivestage/CLINT.scala 109:67] + exception_signal <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/CLINT.scala 110:22] + node _T_4 = eq(io.instruction, UInt<32>("h73")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 115:43] + node _T_5 = or(exception_signal, _T_4) @[src/main/scala/riscv/core/fivestage/CLINT.scala 115:25] + node _T_6 = eq(io.instruction, UInt<32>("h100073")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 115:87] + node _T_7 = or(_T_5, _T_6) @[src/main/scala/riscv/core/fivestage/CLINT.scala 115:69] + when _T_7 : @[src/main/scala/riscv/core/fivestage/CLINT.scala 115:115] + interrupt_state <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/CLINT.scala 116:21] + else : + node _T_8 = neq(io.interrupt_flag, UInt<8>("h0")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 117:32] + node _T_9 = and(_T_8, io.interrupt_enable) @[src/main/scala/riscv/core/fivestage/CLINT.scala 117:57] + when _T_9 : @[src/main/scala/riscv/core/fivestage/CLINT.scala 117:81] + interrupt_state <= UInt<2>("h2") @[src/main/scala/riscv/core/fivestage/CLINT.scala 118:21] + else : + node _T_10 = eq(io.instruction, UInt<32>("h30200073")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 119:29] + when _T_10 : @[src/main/scala/riscv/core/fivestage/CLINT.scala 119:55] + interrupt_state <= UInt<2>("h3") @[src/main/scala/riscv/core/fivestage/CLINT.scala 120:21] + else : + interrupt_state <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/CLINT.scala 122:21] + node _T_11 = eq(csr_state, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 126:18] + when _T_11 : @[src/main/scala/riscv/core/fivestage/CLINT.scala 126:37] + node _T_12 = eq(interrupt_state, UInt<1>("h1")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 127:26] + when _T_12 : @[src/main/scala/riscv/core/fivestage/CLINT.scala 127:57] + csr_state <= UInt<2>("h2") @[src/main/scala/riscv/core/fivestage/CLINT.scala 129:17] + node _instruction_address_T = sub(io.jump_address, UInt<3>("h4")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 136:27] + node _instruction_address_T_1 = tail(_instruction_address_T, 1) @[src/main/scala/riscv/core/fivestage/CLINT.scala 136:27] + node _instruction_address_T_2 = mux(io.jump_flag, _instruction_address_T_1, io.instruction_address_if) @[src/main/scala/riscv/core/fivestage/CLINT.scala 134:12] + node _instruction_address_T_3 = mux(exception_signal, io.instruction_address_cause_exception, _instruction_address_T_2) @[src/main/scala/riscv/core/fivestage/CLINT.scala 131:33] + instruction_address <= _instruction_address_T_3 @[src/main/scala/riscv/core/fivestage/CLINT.scala 131:27] + node _cause_T = eq(UInt<32>("h73"), io.instruction) @[src/main/scala/riscv/core/fivestage/CLINT.scala 144:40] + node _cause_T_1 = mux(_cause_T, UInt<4>("hb"), UInt<4>("ha")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 144:40] + node _cause_T_2 = eq(UInt<32>("h100073"), io.instruction) @[src/main/scala/riscv/core/fivestage/CLINT.scala 144:40] + node _cause_T_3 = mux(_cause_T_2, UInt<2>("h3"), _cause_T_1) @[src/main/scala/riscv/core/fivestage/CLINT.scala 144:40] + node _cause_T_4 = mux(exception_signal, io.exception_cause, _cause_T_3) @[src/main/scala/riscv/core/fivestage/CLINT.scala 141:19] + cause <= _cause_T_4 @[src/main/scala/riscv/core/fivestage/CLINT.scala 141:13] + node _trap_val_T = mux(exception_signal, io.exception_val, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 154:22] + trap_val <= _trap_val_T @[src/main/scala/riscv/core/fivestage/CLINT.scala 154:16] + else : + node _T_13 = eq(interrupt_state, UInt<2>("h2")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 159:32] + when _T_13 : @[src/main/scala/riscv/core/fivestage/CLINT.scala 159:64] + cause <= UInt<32>("h8000000b") @[src/main/scala/riscv/core/fivestage/CLINT.scala 161:13] + node _T_14 = bits(io.interrupt_flag, 0, 0) @[src/main/scala/riscv/core/fivestage/CLINT.scala 162:29] + when _T_14 : @[src/main/scala/riscv/core/fivestage/CLINT.scala 162:34] + cause <= UInt<32>("h80000007") @[src/main/scala/riscv/core/fivestage/CLINT.scala 163:15] + trap_val <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/CLINT.scala 165:16] + csr_state <= UInt<2>("h2") @[src/main/scala/riscv/core/fivestage/CLINT.scala 166:17] + node _instruction_address_T_4 = mux(io.jump_flag, io.jump_address, io.instruction_address_if) @[src/main/scala/riscv/core/fivestage/CLINT.scala 167:33] + instruction_address <= _instruction_address_T_4 @[src/main/scala/riscv/core/fivestage/CLINT.scala 167:27] + else : + node _T_15 = eq(interrupt_state, UInt<2>("h3")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 172:32] + when _T_15 : @[src/main/scala/riscv/core/fivestage/CLINT.scala 172:57] + csr_state <= UInt<2>("h3") @[src/main/scala/riscv/core/fivestage/CLINT.scala 174:17] + else : + node _T_16 = eq(csr_state, UInt<2>("h2")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 176:24] + when _T_16 : @[src/main/scala/riscv/core/fivestage/CLINT.scala 176:43] + csr_state <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/CLINT.scala 177:15] + else : + node _T_17 = eq(csr_state, UInt<1>("h1")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 178:24] + when _T_17 : @[src/main/scala/riscv/core/fivestage/CLINT.scala 178:46] + csr_state <= UInt<3>("h5") @[src/main/scala/riscv/core/fivestage/CLINT.scala 179:15] + else : + node _T_18 = eq(csr_state, UInt<3>("h5")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 180:24] + when _T_18 : @[src/main/scala/riscv/core/fivestage/CLINT.scala 180:44] + csr_state <= UInt<3>("h4") @[src/main/scala/riscv/core/fivestage/CLINT.scala 181:15] + else : + node _T_19 = eq(csr_state, UInt<3>("h4")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 182:24] + when _T_19 : @[src/main/scala/riscv/core/fivestage/CLINT.scala 182:45] + csr_state <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/CLINT.scala 183:15] + else : + node _T_20 = eq(csr_state, UInt<2>("h3")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 184:24] + when _T_20 : @[src/main/scala/riscv/core/fivestage/CLINT.scala 184:43] + csr_state <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/CLINT.scala 185:15] + else : + csr_state <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/CLINT.scala 187:15] + node _csr_reg_write_enable_T = neq(csr_state, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 190:37] + csr_reg_write_enable <= _csr_reg_write_enable_T @[src/main/scala/riscv/core/fivestage/CLINT.scala 190:24] + node _csr_reg_write_address_T = mux(UInt<1>("h0"), UInt<20>("hfffff"), UInt<20>("h0")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 191:36] + node _csr_reg_write_address_T_1 = eq(UInt<2>("h2"), csr_state) @[src/main/scala/riscv/core/fivestage/CLINT.scala 191:110] + node _csr_reg_write_address_T_2 = mux(_csr_reg_write_address_T_1, UInt<12>("h341"), UInt<12>("h0")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 191:110] + node _csr_reg_write_address_T_3 = eq(UInt<3>("h4"), csr_state) @[src/main/scala/riscv/core/fivestage/CLINT.scala 191:110] + node _csr_reg_write_address_T_4 = mux(_csr_reg_write_address_T_3, UInt<12>("h342"), _csr_reg_write_address_T_2) @[src/main/scala/riscv/core/fivestage/CLINT.scala 191:110] + node _csr_reg_write_address_T_5 = eq(UInt<1>("h1"), csr_state) @[src/main/scala/riscv/core/fivestage/CLINT.scala 191:110] + node _csr_reg_write_address_T_6 = mux(_csr_reg_write_address_T_5, UInt<12>("h300"), _csr_reg_write_address_T_4) @[src/main/scala/riscv/core/fivestage/CLINT.scala 191:110] + node _csr_reg_write_address_T_7 = eq(UInt<2>("h3"), csr_state) @[src/main/scala/riscv/core/fivestage/CLINT.scala 191:110] + node _csr_reg_write_address_T_8 = mux(_csr_reg_write_address_T_7, UInt<12>("h300"), _csr_reg_write_address_T_6) @[src/main/scala/riscv/core/fivestage/CLINT.scala 191:110] + node _csr_reg_write_address_T_9 = eq(UInt<3>("h5"), csr_state) @[src/main/scala/riscv/core/fivestage/CLINT.scala 191:110] + node _csr_reg_write_address_T_10 = mux(_csr_reg_write_address_T_9, UInt<12>("h343"), _csr_reg_write_address_T_8) @[src/main/scala/riscv/core/fivestage/CLINT.scala 191:110] + node _csr_reg_write_address_T_11 = cat(_csr_reg_write_address_T, _csr_reg_write_address_T_10) @[src/main/scala/riscv/core/fivestage/CLINT.scala 191:31] + csr_reg_write_address <= _csr_reg_write_address_T_11 @[src/main/scala/riscv/core/fivestage/CLINT.scala 191:25] + node _csr_reg_write_data_T = bits(io.csr_mstatus, 31, 4) @[src/main/scala/riscv/core/fivestage/CLINT.scala 205:45] + node _csr_reg_write_data_T_1 = bits(io.csr_mstatus, 2, 0) @[src/main/scala/riscv/core/fivestage/CLINT.scala 205:78] + node csr_reg_write_data_hi = cat(_csr_reg_write_data_T, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 205:30] + node _csr_reg_write_data_T_2 = cat(csr_reg_write_data_hi, _csr_reg_write_data_T_1) @[src/main/scala/riscv/core/fivestage/CLINT.scala 205:30] + node _csr_reg_write_data_T_3 = bits(io.csr_mstatus, 31, 4) @[src/main/scala/riscv/core/fivestage/CLINT.scala 206:42] + node _csr_reg_write_data_T_4 = bits(io.csr_mstatus, 7, 7) @[src/main/scala/riscv/core/fivestage/CLINT.scala 206:65] + node _csr_reg_write_data_T_5 = bits(io.csr_mstatus, 2, 0) @[src/main/scala/riscv/core/fivestage/CLINT.scala 206:84] + node csr_reg_write_data_hi_1 = cat(_csr_reg_write_data_T_3, _csr_reg_write_data_T_4) @[src/main/scala/riscv/core/fivestage/CLINT.scala 206:27] + node _csr_reg_write_data_T_6 = cat(csr_reg_write_data_hi_1, _csr_reg_write_data_T_5) @[src/main/scala/riscv/core/fivestage/CLINT.scala 206:27] + node _csr_reg_write_data_T_7 = eq(UInt<2>("h2"), csr_state) @[src/main/scala/riscv/core/fivestage/CLINT.scala 201:72] + node _csr_reg_write_data_T_8 = mux(_csr_reg_write_data_T_7, instruction_address, UInt<32>("h0")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 201:72] + node _csr_reg_write_data_T_9 = eq(UInt<3>("h4"), csr_state) @[src/main/scala/riscv/core/fivestage/CLINT.scala 201:72] + node _csr_reg_write_data_T_10 = mux(_csr_reg_write_data_T_9, cause, _csr_reg_write_data_T_8) @[src/main/scala/riscv/core/fivestage/CLINT.scala 201:72] + node _csr_reg_write_data_T_11 = eq(UInt<1>("h1"), csr_state) @[src/main/scala/riscv/core/fivestage/CLINT.scala 201:72] + node _csr_reg_write_data_T_12 = mux(_csr_reg_write_data_T_11, _csr_reg_write_data_T_2, _csr_reg_write_data_T_10) @[src/main/scala/riscv/core/fivestage/CLINT.scala 201:72] + node _csr_reg_write_data_T_13 = eq(UInt<2>("h3"), csr_state) @[src/main/scala/riscv/core/fivestage/CLINT.scala 201:72] + node _csr_reg_write_data_T_14 = mux(_csr_reg_write_data_T_13, _csr_reg_write_data_T_6, _csr_reg_write_data_T_12) @[src/main/scala/riscv/core/fivestage/CLINT.scala 201:72] + node _csr_reg_write_data_T_15 = eq(UInt<3>("h5"), csr_state) @[src/main/scala/riscv/core/fivestage/CLINT.scala 201:72] + node _csr_reg_write_data_T_16 = mux(_csr_reg_write_data_T_15, trap_val, _csr_reg_write_data_T_14) @[src/main/scala/riscv/core/fivestage/CLINT.scala 201:72] + csr_reg_write_data <= _csr_reg_write_data_T_16 @[src/main/scala/riscv/core/fivestage/CLINT.scala 201:22] + io.csr_reg_write_enable <= csr_reg_write_enable @[src/main/scala/riscv/core/fivestage/CLINT.scala 211:27] + io.csr_reg_write_address <= csr_reg_write_address @[src/main/scala/riscv/core/fivestage/CLINT.scala 212:28] + io.csr_reg_write_data <= csr_reg_write_data @[src/main/scala/riscv/core/fivestage/CLINT.scala 213:25] + node _interrupt_assert_T = eq(csr_state, UInt<3>("h4")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 215:33] + node _interrupt_assert_T_1 = eq(csr_state, UInt<2>("h3")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 215:66] + node _interrupt_assert_T_2 = or(_interrupt_assert_T, _interrupt_assert_T_1) @[src/main/scala/riscv/core/fivestage/CLINT.scala 215:53] + interrupt_assert <= _interrupt_assert_T_2 @[src/main/scala/riscv/core/fivestage/CLINT.scala 215:20] + node _interrupt_handler_address_T = eq(UInt<3>("h4"), csr_state) @[src/main/scala/riscv/core/fivestage/CLINT.scala 216:79] + node _interrupt_handler_address_T_1 = mux(_interrupt_handler_address_T, io.csr_mtvec, UInt<32>("h0")) @[src/main/scala/riscv/core/fivestage/CLINT.scala 216:79] + node _interrupt_handler_address_T_2 = eq(UInt<2>("h3"), csr_state) @[src/main/scala/riscv/core/fivestage/CLINT.scala 216:79] + node _interrupt_handler_address_T_3 = mux(_interrupt_handler_address_T_2, io.csr_mepc, _interrupt_handler_address_T_1) @[src/main/scala/riscv/core/fivestage/CLINT.scala 216:79] + interrupt_handler_address <= _interrupt_handler_address_T_3 @[src/main/scala/riscv/core/fivestage/CLINT.scala 216:29] + io.id_interrupt_assert <= interrupt_assert @[src/main/scala/riscv/core/fivestage/CLINT.scala 223:26] + io.id_interrupt_handler_address <= interrupt_handler_address @[src/main/scala/riscv/core/fivestage/CLINT.scala 224:35] + + module CSR : + input clock : Clock + input reset : Reset + output io : { flip reg_write_enable_ex : UInt<1>, flip reg_read_address_id : UInt<12>, flip reg_write_address_ex : UInt<12>, flip reg_write_data_ex : UInt<32>, flip reg_write_enable_clint : UInt<1>, flip reg_read_address_clint : UInt<12>, flip reg_write_address_clint : UInt<12>, flip reg_write_data_clint : UInt<32>, interrupt_enable : UInt<1>, mmu_enable : UInt<1>, id_reg_data : UInt<32>, start_paging : UInt<1>, clint_reg_data : UInt<32>, clint_csr_mtvec : UInt<32>, clint_csr_mepc : UInt<32>, clint_csr_mstatus : UInt<32>, mmu_csr_satp : UInt<32>} @[src/main/scala/riscv/core/fivestage/CSR.scala 37:14] + + reg cycles : UInt<64>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CSR.scala 62:23] + reg mtvec : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CSR.scala 63:22] + reg mcause : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CSR.scala 64:23] + reg mepc : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CSR.scala 65:21] + reg mie : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CSR.scala 66:20] + reg mstatus : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CSR.scala 67:24] + reg mscratch : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CSR.scala 68:25] + reg mtval : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CSR.scala 69:22] + reg satp : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CSR.scala 70:21] + node _cycles_T = add(cycles, UInt<1>("h1")) @[src/main/scala/riscv/core/fivestage/CSR.scala 72:20] + node _cycles_T_1 = tail(_cycles_T, 1) @[src/main/scala/riscv/core/fivestage/CSR.scala 72:20] + cycles <= _cycles_T_1 @[src/main/scala/riscv/core/fivestage/CSR.scala 72:10] + io.clint_csr_mtvec <= mtvec @[src/main/scala/riscv/core/fivestage/CSR.scala 73:22] + io.clint_csr_mepc <= mepc @[src/main/scala/riscv/core/fivestage/CSR.scala 74:21] + io.clint_csr_mstatus <= mstatus @[src/main/scala/riscv/core/fivestage/CSR.scala 75:24] + node _io_interrupt_enable_T = bits(mstatus, 3, 3) @[src/main/scala/riscv/core/fivestage/CSR.scala 76:33] + node _io_interrupt_enable_T_1 = eq(_io_interrupt_enable_T, UInt<1>("h1")) @[src/main/scala/riscv/core/fivestage/CSR.scala 76:37] + io.interrupt_enable <= _io_interrupt_enable_T_1 @[src/main/scala/riscv/core/fivestage/CSR.scala 76:23] + io.mmu_csr_satp <= satp @[src/main/scala/riscv/core/fivestage/CSR.scala 77:19] + node _io_mmu_enable_T = bits(satp, 31, 31) @[src/main/scala/riscv/core/fivestage/CSR.scala 78:24] + node _io_mmu_enable_T_1 = eq(_io_mmu_enable_T, UInt<1>("h1")) @[src/main/scala/riscv/core/fivestage/CSR.scala 78:29] + io.mmu_enable <= _io_mmu_enable_T_1 @[src/main/scala/riscv/core/fivestage/CSR.scala 78:17] + io.start_paging <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/CSR.scala 79:19] + wire reg_write_address : UInt<12> @[src/main/scala/riscv/core/fivestage/CSR.scala 81:31] + wire reg_write_data : UInt<32> @[src/main/scala/riscv/core/fivestage/CSR.scala 82:28] + reg_write_address <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/CSR.scala 83:21] + reg_write_data <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/CSR.scala 84:18] + wire reg_read_address : UInt<12> @[src/main/scala/riscv/core/fivestage/CSR.scala 86:30] + wire reg_read_data : UInt<32> @[src/main/scala/riscv/core/fivestage/CSR.scala 87:27] + reg_read_address <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/CSR.scala 88:20] + reg_read_data <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/CSR.scala 89:17] + when io.reg_write_enable_ex : @[src/main/scala/riscv/core/fivestage/CSR.scala 91:32] + node _reg_write_address_T = bits(io.reg_write_address_ex, 11, 0) @[src/main/scala/riscv/core/fivestage/CSR.scala 92:49] + reg_write_address <= _reg_write_address_T @[src/main/scala/riscv/core/fivestage/CSR.scala 92:23] + reg_write_data <= io.reg_write_data_ex @[src/main/scala/riscv/core/fivestage/CSR.scala 93:20] + else : + when io.reg_write_enable_clint : @[src/main/scala/riscv/core/fivestage/CSR.scala 94:41] + node _reg_write_address_T_1 = bits(io.reg_write_address_clint, 11, 0) @[src/main/scala/riscv/core/fivestage/CSR.scala 95:52] + reg_write_address <= _reg_write_address_T_1 @[src/main/scala/riscv/core/fivestage/CSR.scala 95:23] + reg_write_data <= io.reg_write_data_clint @[src/main/scala/riscv/core/fivestage/CSR.scala 96:20] + node _T = eq(reg_write_address, UInt<12>("h305")) @[src/main/scala/riscv/core/fivestage/CSR.scala 99:26] + when _T : @[src/main/scala/riscv/core/fivestage/CSR.scala 99:49] + mtvec <= reg_write_data @[src/main/scala/riscv/core/fivestage/CSR.scala 100:11] + else : + node _T_1 = eq(reg_write_address, UInt<12>("h342")) @[src/main/scala/riscv/core/fivestage/CSR.scala 101:32] + when _T_1 : @[src/main/scala/riscv/core/fivestage/CSR.scala 101:56] + mcause <= reg_write_data @[src/main/scala/riscv/core/fivestage/CSR.scala 102:12] + else : + node _T_2 = eq(reg_write_address, UInt<12>("h341")) @[src/main/scala/riscv/core/fivestage/CSR.scala 103:32] + when _T_2 : @[src/main/scala/riscv/core/fivestage/CSR.scala 103:54] + mepc <= reg_write_data @[src/main/scala/riscv/core/fivestage/CSR.scala 104:10] + else : + node _T_3 = eq(reg_write_address, UInt<12>("h304")) @[src/main/scala/riscv/core/fivestage/CSR.scala 105:32] + when _T_3 : @[src/main/scala/riscv/core/fivestage/CSR.scala 105:53] + mie <= reg_write_data @[src/main/scala/riscv/core/fivestage/CSR.scala 106:9] + else : + node _T_4 = eq(reg_write_address, UInt<12>("h300")) @[src/main/scala/riscv/core/fivestage/CSR.scala 107:32] + when _T_4 : @[src/main/scala/riscv/core/fivestage/CSR.scala 107:57] + mstatus <= reg_write_data @[src/main/scala/riscv/core/fivestage/CSR.scala 108:13] + else : + node _T_5 = eq(reg_write_address, UInt<12>("h340")) @[src/main/scala/riscv/core/fivestage/CSR.scala 109:32] + when _T_5 : @[src/main/scala/riscv/core/fivestage/CSR.scala 109:58] + mscratch <= reg_write_data @[src/main/scala/riscv/core/fivestage/CSR.scala 110:14] + else : + node _T_6 = eq(reg_write_address, UInt<12>("h343")) @[src/main/scala/riscv/core/fivestage/CSR.scala 111:32] + when _T_6 : @[src/main/scala/riscv/core/fivestage/CSR.scala 111:55] + mtval <= reg_write_data @[src/main/scala/riscv/core/fivestage/CSR.scala 112:11] + else : + node _T_7 = eq(reg_write_address, UInt<12>("h180")) @[src/main/scala/riscv/core/fivestage/CSR.scala 113:32] + when _T_7 : @[src/main/scala/riscv/core/fivestage/CSR.scala 113:54] + satp <= reg_write_data @[src/main/scala/riscv/core/fivestage/CSR.scala 114:10] + node _T_8 = bits(reg_write_data, 31, 31) @[src/main/scala/riscv/core/fivestage/CSR.scala 115:24] + node _T_9 = eq(_T_8, UInt<1>("h1")) @[src/main/scala/riscv/core/fivestage/CSR.scala 115:29] + node _T_10 = bits(satp, 31, 31) @[src/main/scala/riscv/core/fivestage/CSR.scala 115:44] + node _T_11 = eq(_T_10, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CSR.scala 115:49] + node _T_12 = and(_T_9, _T_11) @[src/main/scala/riscv/core/fivestage/CSR.scala 115:37] + when _T_12 : @[src/main/scala/riscv/core/fivestage/CSR.scala 115:58] + io.start_paging <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/CSR.scala 116:23] + node _T_13 = bits(cycles, 31, 0) @[src/main/scala/riscv/core/fivestage/CSR.scala 122:35] + node _T_14 = bits(cycles, 63, 32) @[src/main/scala/riscv/core/fivestage/CSR.scala 123:35] + node _io_id_reg_data_T = eq(UInt<12>("hc00"), io.reg_read_address_id) @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + node _io_id_reg_data_T_1 = mux(_io_id_reg_data_T, _T_13, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + node _io_id_reg_data_T_2 = eq(UInt<12>("hc80"), io.reg_read_address_id) @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + node _io_id_reg_data_T_3 = mux(_io_id_reg_data_T_2, _T_14, _io_id_reg_data_T_1) @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + node _io_id_reg_data_T_4 = eq(UInt<12>("h305"), io.reg_read_address_id) @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + node _io_id_reg_data_T_5 = mux(_io_id_reg_data_T_4, mtvec, _io_id_reg_data_T_3) @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + node _io_id_reg_data_T_6 = eq(UInt<12>("h342"), io.reg_read_address_id) @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + node _io_id_reg_data_T_7 = mux(_io_id_reg_data_T_6, mcause, _io_id_reg_data_T_5) @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + node _io_id_reg_data_T_8 = eq(UInt<12>("h341"), io.reg_read_address_id) @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + node _io_id_reg_data_T_9 = mux(_io_id_reg_data_T_8, mepc, _io_id_reg_data_T_7) @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + node _io_id_reg_data_T_10 = eq(UInt<12>("h304"), io.reg_read_address_id) @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + node _io_id_reg_data_T_11 = mux(_io_id_reg_data_T_10, mie, _io_id_reg_data_T_9) @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + node _io_id_reg_data_T_12 = eq(UInt<12>("h300"), io.reg_read_address_id) @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + node _io_id_reg_data_T_13 = mux(_io_id_reg_data_T_12, mstatus, _io_id_reg_data_T_11) @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + node _io_id_reg_data_T_14 = eq(UInt<12>("h340"), io.reg_read_address_id) @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + node _io_id_reg_data_T_15 = mux(_io_id_reg_data_T_14, mscratch, _io_id_reg_data_T_13) @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + node _io_id_reg_data_T_16 = eq(UInt<12>("h343"), io.reg_read_address_id) @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + node _io_id_reg_data_T_17 = mux(_io_id_reg_data_T_16, mtval, _io_id_reg_data_T_15) @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + node _io_id_reg_data_T_18 = eq(UInt<12>("h180"), io.reg_read_address_id) @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + node _io_id_reg_data_T_19 = mux(_io_id_reg_data_T_18, satp, _io_id_reg_data_T_17) @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + io.id_reg_data <= _io_id_reg_data_T_19 @[src/main/scala/riscv/core/fivestage/CSR.scala 134:18] + node _io_clint_reg_data_T = eq(UInt<12>("hc00"), io.reg_read_address_clint) @[src/main/scala/riscv/core/fivestage/CSR.scala 138:65] + node _io_clint_reg_data_T_1 = mux(_io_clint_reg_data_T, _T_13, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CSR.scala 138:65] + node _io_clint_reg_data_T_2 = eq(UInt<12>("hc80"), io.reg_read_address_clint) @[src/main/scala/riscv/core/fivestage/CSR.scala 138:65] + node _io_clint_reg_data_T_3 = mux(_io_clint_reg_data_T_2, _T_14, _io_clint_reg_data_T_1) @[src/main/scala/riscv/core/fivestage/CSR.scala 138:65] + node _io_clint_reg_data_T_4 = eq(UInt<12>("h305"), io.reg_read_address_clint) @[src/main/scala/riscv/core/fivestage/CSR.scala 138:65] + node _io_clint_reg_data_T_5 = mux(_io_clint_reg_data_T_4, mtvec, _io_clint_reg_data_T_3) @[src/main/scala/riscv/core/fivestage/CSR.scala 138:65] + node _io_clint_reg_data_T_6 = eq(UInt<12>("h342"), io.reg_read_address_clint) @[src/main/scala/riscv/core/fivestage/CSR.scala 138:65] + node _io_clint_reg_data_T_7 = mux(_io_clint_reg_data_T_6, mcause, _io_clint_reg_data_T_5) @[src/main/scala/riscv/core/fivestage/CSR.scala 138:65] + node _io_clint_reg_data_T_8 = eq(UInt<12>("h341"), io.reg_read_address_clint) @[src/main/scala/riscv/core/fivestage/CSR.scala 138:65] + node _io_clint_reg_data_T_9 = mux(_io_clint_reg_data_T_8, mepc, _io_clint_reg_data_T_7) @[src/main/scala/riscv/core/fivestage/CSR.scala 138:65] + node _io_clint_reg_data_T_10 = eq(UInt<12>("h304"), io.reg_read_address_clint) @[src/main/scala/riscv/core/fivestage/CSR.scala 138:65] + node _io_clint_reg_data_T_11 = mux(_io_clint_reg_data_T_10, mie, _io_clint_reg_data_T_9) @[src/main/scala/riscv/core/fivestage/CSR.scala 138:65] + node _io_clint_reg_data_T_12 = eq(UInt<12>("h300"), io.reg_read_address_clint) @[src/main/scala/riscv/core/fivestage/CSR.scala 138:65] + node _io_clint_reg_data_T_13 = mux(_io_clint_reg_data_T_12, mstatus, _io_clint_reg_data_T_11) @[src/main/scala/riscv/core/fivestage/CSR.scala 138:65] + node _io_clint_reg_data_T_14 = eq(UInt<12>("h340"), io.reg_read_address_clint) @[src/main/scala/riscv/core/fivestage/CSR.scala 138:65] + node _io_clint_reg_data_T_15 = mux(_io_clint_reg_data_T_14, mscratch, _io_clint_reg_data_T_13) @[src/main/scala/riscv/core/fivestage/CSR.scala 138:65] + node _io_clint_reg_data_T_16 = eq(UInt<12>("h343"), io.reg_read_address_clint) @[src/main/scala/riscv/core/fivestage/CSR.scala 138:65] + node _io_clint_reg_data_T_17 = mux(_io_clint_reg_data_T_16, mtval, _io_clint_reg_data_T_15) @[src/main/scala/riscv/core/fivestage/CSR.scala 138:65] + node _io_clint_reg_data_T_18 = eq(UInt<12>("h180"), io.reg_read_address_clint) @[src/main/scala/riscv/core/fivestage/CSR.scala 138:65] + node _io_clint_reg_data_T_19 = mux(_io_clint_reg_data_T_18, satp, _io_clint_reg_data_T_17) @[src/main/scala/riscv/core/fivestage/CSR.scala 138:65] + io.clint_reg_data <= _io_clint_reg_data_T_19 @[src/main/scala/riscv/core/fivestage/CSR.scala 138:21] + + module AXI4LiteMaster : + input clock : Clock + input reset : Reset + output io : { channels : { write_address_channel : { AWVALID : UInt<1>, flip AWREADY : UInt<1>, AWADDR : UInt<32>, AWPROT : UInt<3>}, write_data_channel : { WVALID : UInt<1>, flip WREADY : UInt<1>, WDATA : UInt<32>, WSTRB : UInt<4>}, write_response_channel : { flip BVALID : UInt<1>, BREADY : UInt<1>, flip BRESP : UInt<2>}, read_address_channel : { ARVALID : UInt<1>, flip ARREADY : UInt<1>, ARADDR : UInt<32>, ARPROT : UInt<3>}, read_data_channel : { flip RVALID : UInt<1>, RREADY : UInt<1>, flip RDATA : UInt<32>, flip RRESP : UInt<2>}}, bundle : { flip read : UInt<1>, flip write : UInt<1>, read_data : UInt<32>, flip write_data : UInt<32>, flip write_strobe : UInt<1>[4], flip address : UInt<32>, busy : UInt<1>, read_valid : UInt<1>, write_valid : UInt<1>}} @[src/main/scala/bus/AXI4Lite.scala 215:14] + + reg state : UInt<3>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 219:22] + node _io_bundle_busy_T = neq(state, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 220:27] + io.bundle.busy <= _io_bundle_busy_T @[src/main/scala/bus/AXI4Lite.scala 220:18] + reg addr : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[src/main/scala/bus/AXI4Lite.scala 222:21] + reg read_valid : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 223:27] + io.bundle.read_valid <= read_valid @[src/main/scala/bus/AXI4Lite.scala 224:24] + reg write_valid : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 225:28] + io.bundle.write_valid <= write_valid @[src/main/scala/bus/AXI4Lite.scala 226:25] + reg write_data : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[src/main/scala/bus/AXI4Lite.scala 227:27] + wire _write_strobe_WIRE : UInt<1>[4] @[src/main/scala/bus/AXI4Lite.scala 228:37] + _write_strobe_WIRE[0] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 228:37] + _write_strobe_WIRE[1] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 228:37] + _write_strobe_WIRE[2] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 228:37] + _write_strobe_WIRE[3] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 228:37] + reg write_strobe : UInt<1>[4], clock with : + reset => (reset, _write_strobe_WIRE) @[src/main/scala/bus/AXI4Lite.scala 228:29] + reg read_data : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[src/main/scala/bus/AXI4Lite.scala 229:26] + io.channels.read_address_channel.ARADDR <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 231:43] + reg ARVALID : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 232:24] + io.channels.read_address_channel.ARVALID <= ARVALID @[src/main/scala/bus/AXI4Lite.scala 233:44] + io.channels.read_address_channel.ARPROT <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 234:43] + reg RREADY : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 235:23] + io.channels.read_data_channel.RREADY <= RREADY @[src/main/scala/bus/AXI4Lite.scala 236:40] + io.bundle.read_data <= io.channels.read_data_channel.RDATA @[src/main/scala/bus/AXI4Lite.scala 238:23] + reg AWVALID : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 239:24] + io.channels.write_address_channel.AWADDR <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 240:44] + io.channels.write_address_channel.AWVALID <= AWVALID @[src/main/scala/bus/AXI4Lite.scala 241:45] + reg WVALID : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 242:23] + io.channels.write_data_channel.WVALID <= WVALID @[src/main/scala/bus/AXI4Lite.scala 243:41] + io.channels.write_data_channel.WDATA <= write_data @[src/main/scala/bus/AXI4Lite.scala 244:40] + io.channels.write_address_channel.AWPROT <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 245:44] + node io_channels_write_data_channel_WSTRB_lo = cat(write_strobe[1], write_strobe[0]) @[src/main/scala/bus/AXI4Lite.scala 246:56] + node io_channels_write_data_channel_WSTRB_hi = cat(write_strobe[3], write_strobe[2]) @[src/main/scala/bus/AXI4Lite.scala 246:56] + node _io_channels_write_data_channel_WSTRB_T = cat(io_channels_write_data_channel_WSTRB_hi, io_channels_write_data_channel_WSTRB_lo) @[src/main/scala/bus/AXI4Lite.scala 246:56] + io.channels.write_data_channel.WSTRB <= _io_channels_write_data_channel_WSTRB_T @[src/main/scala/bus/AXI4Lite.scala 246:40] + reg BREADY : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 247:23] + io.channels.write_response_channel.BREADY <= BREADY @[src/main/scala/bus/AXI4Lite.scala 248:45] + node _T = asUInt(UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_1 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_2 = eq(_T, _T_1) @[src/main/scala/bus/AXI4Lite.scala 250:17] + when _T_2 : @[src/main/scala/bus/AXI4Lite.scala 250:17] + WVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 252:14] + AWVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 253:15] + ARVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 254:15] + RREADY <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 255:14] + read_valid <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 256:18] + write_valid <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 257:19] + when io.bundle.write : @[src/main/scala/bus/AXI4Lite.scala 258:29] + state <= UInt<2>("h3") @[src/main/scala/bus/AXI4Lite.scala 259:15] + addr <= io.bundle.address @[src/main/scala/bus/AXI4Lite.scala 260:14] + write_data <= io.bundle.write_data @[src/main/scala/bus/AXI4Lite.scala 261:20] + write_strobe <= io.bundle.write_strobe @[src/main/scala/bus/AXI4Lite.scala 262:22] + else : + when io.bundle.read : @[src/main/scala/bus/AXI4Lite.scala 263:34] + state <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 264:15] + addr <= io.bundle.address @[src/main/scala/bus/AXI4Lite.scala 265:14] + else : + node _T_3 = asUInt(UInt<1>("h1")) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_4 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_5 = eq(_T_3, _T_4) @[src/main/scala/bus/AXI4Lite.scala 250:17] + when _T_5 : @[src/main/scala/bus/AXI4Lite.scala 250:17] + ARVALID <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 269:15] + io.channels.read_address_channel.ARADDR <= addr @[src/main/scala/bus/AXI4Lite.scala 270:47] + node _T_6 = and(io.channels.read_address_channel.ARREADY, ARVALID) @[src/main/scala/bus/AXI4Lite.scala 271:53] + when _T_6 : @[src/main/scala/bus/AXI4Lite.scala 271:65] + state <= UInt<2>("h2") @[src/main/scala/bus/AXI4Lite.scala 272:15] + io.channels.read_address_channel.ARADDR <= addr @[src/main/scala/bus/AXI4Lite.scala 273:49] + ARVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 274:17] + else : + node _T_7 = asUInt(UInt<2>("h2")) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_8 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_9 = eq(_T_7, _T_8) @[src/main/scala/bus/AXI4Lite.scala 250:17] + when _T_9 : @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_10 = eq(io.channels.read_data_channel.RRESP, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 278:88] + node _T_11 = and(io.channels.read_data_channel.RVALID, _T_10) @[src/main/scala/bus/AXI4Lite.scala 278:49] + when _T_11 : @[src/main/scala/bus/AXI4Lite.scala 278:97] + state <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 279:15] + read_valid <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 280:20] + RREADY <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 281:16] + read_data <= io.channels.read_data_channel.RDATA @[src/main/scala/bus/AXI4Lite.scala 282:19] + else : + node _T_12 = asUInt(UInt<2>("h3")) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_13 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_14 = eq(_T_12, _T_13) @[src/main/scala/bus/AXI4Lite.scala 250:17] + when _T_14 : @[src/main/scala/bus/AXI4Lite.scala 250:17] + AWVALID <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 286:15] + io.channels.write_address_channel.AWADDR <= addr @[src/main/scala/bus/AXI4Lite.scala 287:48] + node _T_15 = and(io.channels.write_address_channel.AWREADY, AWVALID) @[src/main/scala/bus/AXI4Lite.scala 288:54] + when _T_15 : @[src/main/scala/bus/AXI4Lite.scala 288:66] + state <= UInt<3>("h4") @[src/main/scala/bus/AXI4Lite.scala 289:15] + io.channels.write_address_channel.AWADDR <= addr @[src/main/scala/bus/AXI4Lite.scala 290:50] + AWVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 291:17] + else : + node _T_16 = asUInt(UInt<3>("h4")) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_17 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_18 = eq(_T_16, _T_17) @[src/main/scala/bus/AXI4Lite.scala 250:17] + when _T_18 : @[src/main/scala/bus/AXI4Lite.scala 250:17] + WVALID <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 295:14] + io.channels.write_address_channel.AWADDR <= addr @[src/main/scala/bus/AXI4Lite.scala 296:48] + node _T_19 = and(io.channels.write_data_channel.WREADY, WVALID) @[src/main/scala/bus/AXI4Lite.scala 297:50] + when _T_19 : @[src/main/scala/bus/AXI4Lite.scala 297:61] + io.channels.write_address_channel.AWADDR <= addr @[src/main/scala/bus/AXI4Lite.scala 298:50] + state <= UInt<3>("h5") @[src/main/scala/bus/AXI4Lite.scala 299:15] + WVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 300:16] + else : + node _T_20 = asUInt(UInt<3>("h5")) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_21 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_22 = eq(_T_20, _T_21) @[src/main/scala/bus/AXI4Lite.scala 250:17] + when _T_22 : @[src/main/scala/bus/AXI4Lite.scala 250:17] + BREADY <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 304:14] + node _T_23 = and(io.channels.write_response_channel.BVALID, BREADY) @[src/main/scala/bus/AXI4Lite.scala 305:54] + when _T_23 : @[src/main/scala/bus/AXI4Lite.scala 305:65] + state <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 306:15] + write_valid <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 307:21] + BREADY <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 308:16] + + + module MMU : + input clock : Clock + input reset : Reset + output io : { flip instructions : UInt<32>, flip instructions_address : UInt<32>, flip ppn_from_satp : UInt<20>, flip virtual_address : UInt<32>, flip mmu_occupied_by_mem : UInt<1>, flip restart : UInt<1>, restart_done : UInt<1>, pa_valid : UInt<1>, pa : UInt<32>, page_fault_signals : UInt<1>, va_cause_page_fault : UInt<32>, ecause : UInt<32>, epc : UInt<32>, flip page_fault_responed : UInt<1>, bus : { read : UInt<1>, address : UInt<32>, flip read_data : UInt<32>, flip read_valid : UInt<1>, write : UInt<1>, write_data : UInt<32>, write_strobe : UInt<1>[4], flip write_valid : UInt<1>, flip busy : UInt<1>, request : UInt<1>, flip granted : UInt<1>}} @[src/main/scala/riscv/core/fivestage/MMU.scala 14:14] + + node opcode = bits(io.instructions, 6, 0) @[src/main/scala/riscv/core/fivestage/MMU.scala 37:31] + reg state : UInt<3>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/MMU.scala 39:22] + reg pa : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/MMU.scala 41:19] + node vpn1 = bits(io.virtual_address, 31, 22) @[src/main/scala/riscv/core/fivestage/MMU.scala 43:16] + node vpn0 = bits(io.virtual_address, 21, 12) @[src/main/scala/riscv/core/fivestage/MMU.scala 45:16] + node pageoffset = bits(io.virtual_address, 11, 0) @[src/main/scala/riscv/core/fivestage/MMU.scala 46:22] + reg pte1 : UInt<32>, clock with : + reset => (UInt<1>("h0"), pte1) @[src/main/scala/riscv/core/fivestage/MMU.scala 48:17] + reg pte0 : UInt<32>, clock with : + reset => (UInt<1>("h0"), pte0) @[src/main/scala/riscv/core/fivestage/MMU.scala 49:17] + reg page_fault_signals : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/MMU.scala 51:35] + io.pa_valid <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 77:15] + io.bus.request <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 78:18] + io.bus.read <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 79:15] + io.bus.address <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 80:18] + io.bus.write_data <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 81:21] + wire _WIRE : UInt<1>[4] @[src/main/scala/riscv/core/fivestage/MMU.scala 82:33] + _WIRE[0] <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 82:33] + _WIRE[1] <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 82:33] + _WIRE[2] <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 82:33] + _WIRE[3] <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 82:33] + io.bus.write_strobe <= _WIRE @[src/main/scala/riscv/core/fivestage/MMU.scala 82:23] + io.bus.write <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 83:16] + io.page_fault_signals <= page_fault_signals @[src/main/scala/riscv/core/fivestage/MMU.scala 84:25] + io.ecause <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 86:13] + io.pa <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 87:9] + io.restart_done <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 88:19] + io.va_cause_page_fault <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 89:26] + io.epc <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 90:10] + when io.bus.granted : @[src/main/scala/riscv/core/fivestage/MMU.scala 94:24] + node _T = eq(state, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/MMU.scala 95:16] + when _T : @[src/main/scala/riscv/core/fivestage/MMU.scala 95:36] + io.pa_valid <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 98:19] + io.bus.read <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MMU.scala 99:19] + io.restart_done <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 100:23] + node _io_bus_address_T = dshl(io.ppn_from_satp, UInt<4>("hc")) @[src/main/scala/riscv/core/fivestage/MMU.scala 101:44] + node _io_bus_address_T_1 = shl(vpn1, 2) @[src/main/scala/riscv/core/fivestage/MMU.scala 101:91] + node _io_bus_address_T_2 = and(_io_bus_address_T, _io_bus_address_T_1) @[src/main/scala/riscv/core/fivestage/MMU.scala 101:83] + io.bus.address <= _io_bus_address_T_2 @[src/main/scala/riscv/core/fivestage/MMU.scala 101:22] + state <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MMU.scala 103:13] + else : + node _T_1 = eq(state, UInt<1>("h1")) @[src/main/scala/riscv/core/fivestage/MMU.scala 104:22] + when _T_1 : @[src/main/scala/riscv/core/fivestage/MMU.scala 104:44] + io.bus.read <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 106:19] + when io.bus.read_valid : @[src/main/scala/riscv/core/fivestage/MMU.scala 107:31] + pte1 <= io.bus.read_data @[src/main/scala/riscv/core/fivestage/MMU.scala 108:14] + when io.restart : @[src/main/scala/riscv/core/fivestage/MMU.scala 109:26] + io.restart_done <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MMU.scala 110:27] + state <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 111:17] + else : + state <= UInt<2>("h2") @[src/main/scala/riscv/core/fivestage/MMU.scala 113:17] + else : + node _T_2 = eq(state, UInt<2>("h2")) @[src/main/scala/riscv/core/fivestage/MMU.scala 116:22] + when _T_2 : @[src/main/scala/riscv/core/fivestage/MMU.scala 116:47] + when io.restart : @[src/main/scala/riscv/core/fivestage/MMU.scala 118:24] + io.restart_done <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MMU.scala 119:25] + state <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 120:15] + else : + node _T_3 = bits(pte1, 0, 0) @[src/main/scala/riscv/core/fivestage/MMU.scala 121:22] + node _T_4 = eq(_T_3, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/MMU.scala 121:26] + node _T_5 = bits(pte1, 2, 1) @[src/main/scala/riscv/core/fivestage/MMU.scala 121:42] + node _T_6 = eq(_T_5, UInt<2>("h2")) @[src/main/scala/riscv/core/fivestage/MMU.scala 121:49] + node _T_7 = or(_T_4, _T_6) @[src/main/scala/riscv/core/fivestage/MMU.scala 121:34] + node _T_8 = bits(pte1, 9, 8) @[src/main/scala/riscv/core/fivestage/MMU.scala 121:70] + node _T_9 = neq(_T_8, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/MMU.scala 121:77] + node _T_10 = or(_T_7, _T_9) @[src/main/scala/riscv/core/fivestage/MMU.scala 121:62] + when _T_10 : @[src/main/scala/riscv/core/fivestage/MMU.scala 121:91] + node _io_ecause_T = eq(UInt<6>("h23"), io.instructions) @[src/main/scala/riscv/core/fivestage/MMU.scala 56:39] + node _io_ecause_T_1 = mux(_io_ecause_T, UInt<4>("hf"), UInt<4>("ha")) @[src/main/scala/riscv/core/fivestage/MMU.scala 56:39] + node _io_ecause_T_2 = eq(UInt<2>("h3"), io.instructions) @[src/main/scala/riscv/core/fivestage/MMU.scala 56:39] + node _io_ecause_T_3 = mux(_io_ecause_T_2, UInt<4>("hd"), _io_ecause_T_1) @[src/main/scala/riscv/core/fivestage/MMU.scala 56:39] + node _io_ecause_T_4 = mux(io.mmu_occupied_by_mem, _io_ecause_T_3, UInt<4>("hc")) @[src/main/scala/riscv/core/fivestage/MMU.scala 54:21] + io.ecause <= _io_ecause_T_4 @[src/main/scala/riscv/core/fivestage/MMU.scala 54:15] + io.va_cause_page_fault <= io.virtual_address @[src/main/scala/riscv/core/fivestage/MMU.scala 64:28] + page_fault_signals <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MMU.scala 65:24] + node _io_epc_T = mux(io.mmu_occupied_by_mem, io.instructions_address, io.virtual_address) @[src/main/scala/riscv/core/fivestage/MMU.scala 66:18] + io.epc <= _io_epc_T @[src/main/scala/riscv/core/fivestage/MMU.scala 66:12] + when io.page_fault_responed : @[src/main/scala/riscv/core/fivestage/MMU.scala 71:34] + page_fault_signals <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 72:26] + state <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 73:13] + else : + io.bus.read <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MMU.scala 125:21] + node _io_bus_address_T_3 = bits(pte1, 29, 10) @[src/main/scala/riscv/core/fivestage/MMU.scala 126:33] + node _io_bus_address_T_4 = dshl(_io_bus_address_T_3, UInt<4>("hc")) @[src/main/scala/riscv/core/fivestage/MMU.scala 126:42] + node _io_bus_address_T_5 = shl(vpn0, 2) @[src/main/scala/riscv/core/fivestage/MMU.scala 126:89] + node _io_bus_address_T_6 = and(_io_bus_address_T_4, _io_bus_address_T_5) @[src/main/scala/riscv/core/fivestage/MMU.scala 126:81] + io.bus.address <= _io_bus_address_T_6 @[src/main/scala/riscv/core/fivestage/MMU.scala 126:24] + when io.bus.granted : @[src/main/scala/riscv/core/fivestage/MMU.scala 128:30] + state <= UInt<2>("h3") @[src/main/scala/riscv/core/fivestage/MMU.scala 129:17] + else : + node _T_11 = eq(state, UInt<2>("h3")) @[src/main/scala/riscv/core/fivestage/MMU.scala 132:22] + when _T_11 : @[src/main/scala/riscv/core/fivestage/MMU.scala 132:44] + io.bus.read <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 133:19] + when io.bus.read_valid : @[src/main/scala/riscv/core/fivestage/MMU.scala 134:31] + pte0 <= io.bus.read_data @[src/main/scala/riscv/core/fivestage/MMU.scala 135:14] + when io.restart : @[src/main/scala/riscv/core/fivestage/MMU.scala 136:26] + io.restart_done <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MMU.scala 137:27] + state <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 138:17] + else : + state <= UInt<3>("h4") @[src/main/scala/riscv/core/fivestage/MMU.scala 140:17] + else : + node _T_12 = eq(state, UInt<3>("h4")) @[src/main/scala/riscv/core/fivestage/MMU.scala 143:22] + when _T_12 : @[src/main/scala/riscv/core/fivestage/MMU.scala 143:47] + when io.restart : @[src/main/scala/riscv/core/fivestage/MMU.scala 144:24] + io.restart_done <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MMU.scala 145:25] + state <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 146:15] + else : + node _T_13 = bits(pte0, 0, 0) @[src/main/scala/riscv/core/fivestage/MMU.scala 147:22] + node _T_14 = eq(_T_13, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/MMU.scala 147:26] + node _T_15 = bits(pte0, 2, 1) @[src/main/scala/riscv/core/fivestage/MMU.scala 147:42] + node _T_16 = eq(_T_15, UInt<2>("h2")) @[src/main/scala/riscv/core/fivestage/MMU.scala 147:49] + node _T_17 = or(_T_14, _T_16) @[src/main/scala/riscv/core/fivestage/MMU.scala 147:34] + node _T_18 = bits(pte0, 9, 8) @[src/main/scala/riscv/core/fivestage/MMU.scala 147:70] + node _T_19 = neq(_T_18, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/MMU.scala 147:77] + node _T_20 = or(_T_17, _T_19) @[src/main/scala/riscv/core/fivestage/MMU.scala 147:62] + node _T_21 = bits(pte0, 3, 1) @[src/main/scala/riscv/core/fivestage/MMU.scala 147:98] + node _T_22 = eq(_T_21, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/MMU.scala 147:105] + node _T_23 = or(_T_20, _T_22) @[src/main/scala/riscv/core/fivestage/MMU.scala 147:90] + when _T_23 : @[src/main/scala/riscv/core/fivestage/MMU.scala 147:120] + node _io_ecause_T_5 = eq(UInt<6>("h23"), io.instructions) @[src/main/scala/riscv/core/fivestage/MMU.scala 56:39] + node _io_ecause_T_6 = mux(_io_ecause_T_5, UInt<4>("hf"), UInt<4>("ha")) @[src/main/scala/riscv/core/fivestage/MMU.scala 56:39] + node _io_ecause_T_7 = eq(UInt<2>("h3"), io.instructions) @[src/main/scala/riscv/core/fivestage/MMU.scala 56:39] + node _io_ecause_T_8 = mux(_io_ecause_T_7, UInt<4>("hd"), _io_ecause_T_6) @[src/main/scala/riscv/core/fivestage/MMU.scala 56:39] + node _io_ecause_T_9 = mux(io.mmu_occupied_by_mem, _io_ecause_T_8, UInt<4>("hc")) @[src/main/scala/riscv/core/fivestage/MMU.scala 54:21] + io.ecause <= _io_ecause_T_9 @[src/main/scala/riscv/core/fivestage/MMU.scala 54:15] + io.va_cause_page_fault <= io.virtual_address @[src/main/scala/riscv/core/fivestage/MMU.scala 64:28] + page_fault_signals <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MMU.scala 65:24] + node _io_epc_T_1 = mux(io.mmu_occupied_by_mem, io.instructions_address, io.virtual_address) @[src/main/scala/riscv/core/fivestage/MMU.scala 66:18] + io.epc <= _io_epc_T_1 @[src/main/scala/riscv/core/fivestage/MMU.scala 66:12] + when io.page_fault_responed : @[src/main/scala/riscv/core/fivestage/MMU.scala 71:34] + page_fault_signals <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 72:26] + state <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 73:13] + else : + node _T_24 = bits(pte0, 1, 1) @[src/main/scala/riscv/core/fivestage/MMU.scala 150:22] + node _T_25 = eq(_T_24, UInt<1>("h1")) @[src/main/scala/riscv/core/fivestage/MMU.scala 150:26] + node _T_26 = bits(pte0, 3, 3) @[src/main/scala/riscv/core/fivestage/MMU.scala 150:41] + node _T_27 = eq(_T_26, UInt<1>("h1")) @[src/main/scala/riscv/core/fivestage/MMU.scala 150:45] + node _T_28 = or(_T_25, _T_27) @[src/main/scala/riscv/core/fivestage/MMU.scala 150:34] + when _T_28 : @[src/main/scala/riscv/core/fivestage/MMU.scala 150:54] + node _instructionInvalid_T = eq(io.mmu_occupied_by_mem, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/MMU.scala 152:57] + node _instructionInvalid_T_1 = bits(pte0, 3, 3) @[src/main/scala/riscv/core/fivestage/MMU.scala 152:76] + node _instructionInvalid_T_2 = eq(_instructionInvalid_T_1, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/MMU.scala 152:80] + node instructionInvalid = and(_instructionInvalid_T, _instructionInvalid_T_2) @[src/main/scala/riscv/core/fivestage/MMU.scala 152:69] + node _storeInvalid_T = bits(io.instructions, 6, 0) @[src/main/scala/riscv/core/fivestage/MMU.scala 153:43] + node _storeInvalid_T_1 = eq(_storeInvalid_T, UInt<6>("h23")) @[src/main/scala/riscv/core/fivestage/MMU.scala 153:50] + node _storeInvalid_T_2 = bits(pte0, 2, 2) @[src/main/scala/riscv/core/fivestage/MMU.scala 153:80] + node _storeInvalid_T_3 = eq(_storeInvalid_T_2, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/MMU.scala 153:84] + node storeInvalid = and(_storeInvalid_T_1, _storeInvalid_T_3) @[src/main/scala/riscv/core/fivestage/MMU.scala 153:73] + node _loadInvalid_T = bits(io.instructions, 6, 0) @[src/main/scala/riscv/core/fivestage/MMU.scala 154:42] + node _loadInvalid_T_1 = eq(_loadInvalid_T, UInt<2>("h3")) @[src/main/scala/riscv/core/fivestage/MMU.scala 154:49] + node _loadInvalid_T_2 = bits(pte0, 1, 1) @[src/main/scala/riscv/core/fivestage/MMU.scala 154:79] + node _loadInvalid_T_3 = eq(_loadInvalid_T_2, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/MMU.scala 154:83] + node loadInvalid = and(_loadInvalid_T_1, _loadInvalid_T_3) @[src/main/scala/riscv/core/fivestage/MMU.scala 154:72] + node _T_29 = or(instructionInvalid, storeInvalid) @[src/main/scala/riscv/core/fivestage/MMU.scala 155:33] + node _T_30 = or(_T_29, loadInvalid) @[src/main/scala/riscv/core/fivestage/MMU.scala 155:49] + when _T_30 : @[src/main/scala/riscv/core/fivestage/MMU.scala 155:65] + node _io_ecause_T_10 = eq(UInt<6>("h23"), io.instructions) @[src/main/scala/riscv/core/fivestage/MMU.scala 56:39] + node _io_ecause_T_11 = mux(_io_ecause_T_10, UInt<4>("hf"), UInt<4>("ha")) @[src/main/scala/riscv/core/fivestage/MMU.scala 56:39] + node _io_ecause_T_12 = eq(UInt<2>("h3"), io.instructions) @[src/main/scala/riscv/core/fivestage/MMU.scala 56:39] + node _io_ecause_T_13 = mux(_io_ecause_T_12, UInt<4>("hd"), _io_ecause_T_11) @[src/main/scala/riscv/core/fivestage/MMU.scala 56:39] + node _io_ecause_T_14 = mux(io.mmu_occupied_by_mem, _io_ecause_T_13, UInt<4>("hc")) @[src/main/scala/riscv/core/fivestage/MMU.scala 54:21] + io.ecause <= _io_ecause_T_14 @[src/main/scala/riscv/core/fivestage/MMU.scala 54:15] + io.va_cause_page_fault <= io.virtual_address @[src/main/scala/riscv/core/fivestage/MMU.scala 64:28] + page_fault_signals <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MMU.scala 65:24] + node _io_epc_T_2 = mux(io.mmu_occupied_by_mem, io.instructions_address, io.virtual_address) @[src/main/scala/riscv/core/fivestage/MMU.scala 66:18] + io.epc <= _io_epc_T_2 @[src/main/scala/riscv/core/fivestage/MMU.scala 66:12] + when io.page_fault_responed : @[src/main/scala/riscv/core/fivestage/MMU.scala 71:34] + page_fault_signals <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 72:26] + state <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 73:13] + else : + node _T_31 = bits(pte0, 6, 6) @[src/main/scala/riscv/core/fivestage/MMU.scala 158:24] + node _T_32 = eq(_T_31, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/MMU.scala 158:28] + node _T_33 = bits(pte0, 7, 7) @[src/main/scala/riscv/core/fivestage/MMU.scala 158:44] + node _T_34 = eq(_T_33, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/MMU.scala 158:48] + node _T_35 = bits(io.instructions, 6, 0) @[src/main/scala/riscv/core/fivestage/MMU.scala 158:74] + node _T_36 = eq(_T_35, UInt<6>("h23")) @[src/main/scala/riscv/core/fivestage/MMU.scala 158:81] + node _T_37 = and(_T_34, _T_36) @[src/main/scala/riscv/core/fivestage/MMU.scala 158:56] + node _T_38 = or(_T_32, _T_37) @[src/main/scala/riscv/core/fivestage/MMU.scala 158:36] + when _T_38 : @[src/main/scala/riscv/core/fivestage/MMU.scala 158:106] + node _setAbit_T = bits(io.instructions, 6, 0) @[src/main/scala/riscv/core/fivestage/MMU.scala 163:40] + node setAbit = eq(_setAbit_T, UInt<6>("h23")) @[src/main/scala/riscv/core/fivestage/MMU.scala 163:47] + node _io_bus_write_data_T = bits(pte0, 31, 8) @[src/main/scala/riscv/core/fivestage/MMU.scala 164:40] + node _io_bus_write_data_T_1 = bits(pte0, 5, 0) @[src/main/scala/riscv/core/fivestage/MMU.scala 164:72] + node io_bus_write_data_lo = cat(UInt<1>("h1"), _io_bus_write_data_T_1) @[src/main/scala/riscv/core/fivestage/MMU.scala 164:35] + node io_bus_write_data_hi = cat(_io_bus_write_data_T, setAbit) @[src/main/scala/riscv/core/fivestage/MMU.scala 164:35] + node _io_bus_write_data_T_2 = cat(io_bus_write_data_hi, io_bus_write_data_lo) @[src/main/scala/riscv/core/fivestage/MMU.scala 164:35] + io.bus.write_data <= _io_bus_write_data_T_2 @[src/main/scala/riscv/core/fivestage/MMU.scala 164:29] + io.bus.write <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MMU.scala 165:24] + node _io_bus_address_T_7 = bits(pte1, 29, 10) @[src/main/scala/riscv/core/fivestage/MMU.scala 166:35] + node _io_bus_address_T_8 = dshl(_io_bus_address_T_7, UInt<4>("hc")) @[src/main/scala/riscv/core/fivestage/MMU.scala 166:44] + node _io_bus_address_T_9 = shl(vpn0, 2) @[src/main/scala/riscv/core/fivestage/MMU.scala 166:91] + node _io_bus_address_T_10 = add(_io_bus_address_T_8, _io_bus_address_T_9) @[src/main/scala/riscv/core/fivestage/MMU.scala 166:83] + node _io_bus_address_T_11 = tail(_io_bus_address_T_10, 1) @[src/main/scala/riscv/core/fivestage/MMU.scala 166:83] + io.bus.address <= _io_bus_address_T_11 @[src/main/scala/riscv/core/fivestage/MMU.scala 166:26] + io.bus.write_strobe[0] <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MMU.scala 168:36] + io.bus.write_strobe[1] <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MMU.scala 168:36] + io.bus.write_strobe[2] <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MMU.scala 168:36] + io.bus.write_strobe[3] <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MMU.scala 168:36] + state <= UInt<3>("h5") @[src/main/scala/riscv/core/fivestage/MMU.scala 170:17] + else : + state <= UInt<3>("h6") @[src/main/scala/riscv/core/fivestage/MMU.scala 172:17] + else : + node _T_39 = eq(state, UInt<3>("h5")) @[src/main/scala/riscv/core/fivestage/MMU.scala 175:22] + when _T_39 : @[src/main/scala/riscv/core/fivestage/MMU.scala 175:46] + io.bus.write <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 176:20] + when io.bus.write_valid : @[src/main/scala/riscv/core/fivestage/MMU.scala 177:32] + when io.restart : @[src/main/scala/riscv/core/fivestage/MMU.scala 178:26] + io.restart_done <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MMU.scala 179:27] + state <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 180:17] + else : + state <= UInt<3>("h6") @[src/main/scala/riscv/core/fivestage/MMU.scala 182:17] + else : + node _T_40 = eq(state, UInt<3>("h6")) @[src/main/scala/riscv/core/fivestage/MMU.scala 185:22] + when _T_40 : @[src/main/scala/riscv/core/fivestage/MMU.scala 185:55] + when io.restart : @[src/main/scala/riscv/core/fivestage/MMU.scala 186:24] + io.restart_done <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MMU.scala 187:25] + state <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 188:15] + else : + node _io_pa_T = bits(pte0, 29, 10) @[src/main/scala/riscv/core/fivestage/MMU.scala 190:26] + node _io_pa_T_1 = cat(_io_pa_T, pageoffset) @[src/main/scala/riscv/core/fivestage/MMU.scala 190:21] + io.pa <= _io_pa_T_1 @[src/main/scala/riscv/core/fivestage/MMU.scala 190:15] + io.pa_valid <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/MMU.scala 191:21] + state <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/MMU.scala 192:15] + + + module CPU : + input clock : Clock + input reset : Reset + output io : { axi4_channels : { write_address_channel : { AWVALID : UInt<1>, flip AWREADY : UInt<1>, AWADDR : UInt<32>, AWPROT : UInt<3>}, write_data_channel : { WVALID : UInt<1>, flip WREADY : UInt<1>, WDATA : UInt<32>, WSTRB : UInt<4>}, write_response_channel : { flip BVALID : UInt<1>, BREADY : UInt<1>, flip BRESP : UInt<2>}, read_address_channel : { ARVALID : UInt<1>, flip ARREADY : UInt<1>, ARADDR : UInt<32>, ARPROT : UInt<3>}, read_data_channel : { flip RVALID : UInt<1>, RREADY : UInt<1>, flip RDATA : UInt<32>, flip RRESP : UInt<2>}}, bus_address : UInt<32>, flip interrupt_flag : UInt<32>, flip stall_flag_bus : UInt<1>, flip debug_read_address : UInt<5>, debug_read_data : UInt<32>, flip instruction_valid : UInt<1>, bus_busy : UInt<1>, debug : UInt<32>[6]} @[src/main/scala/riscv/core/fivestage/CPU.scala 31:14] + + inst ctrl of Control @[src/main/scala/riscv/core/fivestage/CPU.scala 33:20] + ctrl.clock <= clock + ctrl.reset <= reset + inst regs of RegisterFile @[src/main/scala/riscv/core/fivestage/CPU.scala 34:20] + regs.clock <= clock + regs.reset <= reset + inst inst_fetch of InstructionFetch @[src/main/scala/riscv/core/fivestage/CPU.scala 35:26] + inst_fetch.clock <= clock + inst_fetch.reset <= reset + inst if2id of IF2ID @[src/main/scala/riscv/core/fivestage/CPU.scala 36:21] + if2id.clock <= clock + if2id.reset <= reset + inst id of InstructionDecode @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + id.clock <= clock + id.reset <= reset + inst id2ex of ID2EX @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + id2ex.clock <= clock + id2ex.reset <= reset + inst ex of Execute @[src/main/scala/riscv/core/fivestage/CPU.scala 39:18] + ex.clock <= clock + ex.reset <= reset + inst ex2mem of EX2MEM @[src/main/scala/riscv/core/fivestage/CPU.scala 40:22] + ex2mem.clock <= clock + ex2mem.reset <= reset + inst mem of MemoryAccess @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + mem.clock <= clock + mem.reset <= reset + inst mem2wb of MEM2WB @[src/main/scala/riscv/core/fivestage/CPU.scala 42:22] + mem2wb.clock <= clock + mem2wb.reset <= reset + inst wb of WriteBack @[src/main/scala/riscv/core/fivestage/CPU.scala 43:18] + wb.clock <= clock + wb.reset <= reset + inst forwarding of Forwarding @[src/main/scala/riscv/core/fivestage/CPU.scala 44:26] + forwarding.clock <= clock + forwarding.reset <= reset + inst clint of CLINT @[src/main/scala/riscv/core/fivestage/CPU.scala 45:21] + clint.clock <= clock + clint.reset <= reset + inst csr_regs of CSR @[src/main/scala/riscv/core/fivestage/CPU.scala 46:24] + csr_regs.clock <= clock + csr_regs.reset <= reset + inst axi4_master of AXI4LiteMaster @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + axi4_master.clock <= clock + axi4_master.reset <= reset + inst mmu of MMU @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + mmu.clock <= clock + mmu.reset <= reset + axi4_master.io.channels.read_data_channel.RRESP <= io.axi4_channels.read_data_channel.RRESP @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + axi4_master.io.channels.read_data_channel.RDATA <= io.axi4_channels.read_data_channel.RDATA @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + io.axi4_channels.read_data_channel.RREADY <= axi4_master.io.channels.read_data_channel.RREADY @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + axi4_master.io.channels.read_data_channel.RVALID <= io.axi4_channels.read_data_channel.RVALID @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + io.axi4_channels.read_address_channel.ARPROT <= axi4_master.io.channels.read_address_channel.ARPROT @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + io.axi4_channels.read_address_channel.ARADDR <= axi4_master.io.channels.read_address_channel.ARADDR @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + axi4_master.io.channels.read_address_channel.ARREADY <= io.axi4_channels.read_address_channel.ARREADY @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + io.axi4_channels.read_address_channel.ARVALID <= axi4_master.io.channels.read_address_channel.ARVALID @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + axi4_master.io.channels.write_response_channel.BRESP <= io.axi4_channels.write_response_channel.BRESP @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + io.axi4_channels.write_response_channel.BREADY <= axi4_master.io.channels.write_response_channel.BREADY @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + axi4_master.io.channels.write_response_channel.BVALID <= io.axi4_channels.write_response_channel.BVALID @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + io.axi4_channels.write_data_channel.WSTRB <= axi4_master.io.channels.write_data_channel.WSTRB @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + io.axi4_channels.write_data_channel.WDATA <= axi4_master.io.channels.write_data_channel.WDATA @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + axi4_master.io.channels.write_data_channel.WREADY <= io.axi4_channels.write_data_channel.WREADY @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + io.axi4_channels.write_data_channel.WVALID <= axi4_master.io.channels.write_data_channel.WVALID @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + io.axi4_channels.write_address_channel.AWPROT <= axi4_master.io.channels.write_address_channel.AWPROT @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + io.axi4_channels.write_address_channel.AWADDR <= axi4_master.io.channels.write_address_channel.AWADDR @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + axi4_master.io.channels.write_address_channel.AWREADY <= io.axi4_channels.write_address_channel.AWREADY @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + io.axi4_channels.write_address_channel.AWVALID <= axi4_master.io.channels.write_address_channel.AWVALID @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + io.debug[0] <= ex.io.reg1_data @[src/main/scala/riscv/core/fivestage/CPU.scala 50:15] + io.debug[1] <= ex.io.reg2_data @[src/main/scala/riscv/core/fivestage/CPU.scala 51:15] + io.debug[2] <= ex.io.instruction_address @[src/main/scala/riscv/core/fivestage/CPU.scala 52:15] + io.debug[3] <= ex.io.instruction @[src/main/scala/riscv/core/fivestage/CPU.scala 53:15] + io.debug[4] <= inst_fetch.io.jump_address_id @[src/main/scala/riscv/core/fivestage/CPU.scala 54:15] + io.debug[5] <= inst_fetch.io.jump_flag_id @[src/main/scala/riscv/core/fivestage/CPU.scala 55:15] + io.bus_busy <= axi4_master.io.bundle.busy @[src/main/scala/riscv/core/fivestage/CPU.scala 56:15] + reg bus_granted : UInt<3>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CPU.scala 58:28] + reg mem_access_state : UInt<3>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CPU.scala 59:33] + reg virtual_address : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CPU.scala 60:32] + reg physical_address : UInt<32>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CPU.scala 61:33] + reg mmu_restart : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CPU.scala 62:28] + reg pending : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CPU.scala 63:24] + node _T = eq(mem_access_state, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CPU.scala 66:25] + when _T : @[src/main/scala/riscv/core/fivestage/CPU.scala 66:50] + bus_granted <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/CPU.scala 67:17] + node _T_1 = eq(axi4_master.io.bundle.busy, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CPU.scala 68:10] + node _T_2 = eq(axi4_master.io.bundle.read_valid, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CPU.scala 68:41] + node _T_3 = and(_T_1, _T_2) @[src/main/scala/riscv/core/fivestage/CPU.scala 68:38] + when _T_3 : @[src/main/scala/riscv/core/fivestage/CPU.scala 68:76] + when csr_regs.io.mmu_enable : @[src/main/scala/riscv/core/fivestage/CPU.scala 69:36] + when mem.io.bus.request : @[src/main/scala/riscv/core/fivestage/CPU.scala 70:34] + mem_access_state <= UInt<2>("h2") @[src/main/scala/riscv/core/fivestage/CPU.scala 71:28] + bus_granted <= UInt<2>("h3") @[src/main/scala/riscv/core/fivestage/CPU.scala 72:23] + virtual_address <= ex2mem.io.output_alu_result @[src/main/scala/riscv/core/fivestage/CPU.scala 73:27] + else : + node _T_4 = and(inst_fetch.io.bus.request, io.instruction_valid) @[src/main/scala/riscv/core/fivestage/CPU.scala 74:46] + node _T_5 = and(_T_4, inst_fetch.io.pc_valid) @[src/main/scala/riscv/core/fivestage/CPU.scala 74:70] + when _T_5 : @[src/main/scala/riscv/core/fivestage/CPU.scala 74:97] + mem_access_state <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/CPU.scala 75:28] + bus_granted <= UInt<3>("h4") @[src/main/scala/riscv/core/fivestage/CPU.scala 76:23] + virtual_address <= inst_fetch.io.id_instruction_address @[src/main/scala/riscv/core/fivestage/CPU.scala 77:27] + else : + when mem.io.bus.request : @[src/main/scala/riscv/core/fivestage/CPU.scala 80:34] + mem_access_state <= UInt<2>("h3") @[src/main/scala/riscv/core/fivestage/CPU.scala 81:28] + physical_address <= ex2mem.io.output_alu_result @[src/main/scala/riscv/core/fivestage/CPU.scala 82:28] + bus_granted <= UInt<2>("h2") @[src/main/scala/riscv/core/fivestage/CPU.scala 83:23] + else : + node _T_6 = and(inst_fetch.io.bus.request, io.instruction_valid) @[src/main/scala/riscv/core/fivestage/CPU.scala 84:46] + node _T_7 = and(_T_6, inst_fetch.io.pc_valid) @[src/main/scala/riscv/core/fivestage/CPU.scala 84:70] + when _T_7 : @[src/main/scala/riscv/core/fivestage/CPU.scala 84:97] + mem_access_state <= UInt<3>("h4") @[src/main/scala/riscv/core/fivestage/CPU.scala 85:28] + bus_granted <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/CPU.scala 86:23] + physical_address <= inst_fetch.io.id_instruction_address @[src/main/scala/riscv/core/fivestage/CPU.scala 87:28] + else : + node _T_8 = eq(mem_access_state, UInt<2>("h2")) @[src/main/scala/riscv/core/fivestage/CPU.scala 91:31] + when _T_8 : @[src/main/scala/riscv/core/fivestage/CPU.scala 91:73] + when clint.io.exception_token : @[src/main/scala/riscv/core/fivestage/CPU.scala 92:36] + mem_access_state <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/CPU.scala 93:24] + bus_granted <= UInt<3>("h4") @[src/main/scala/riscv/core/fivestage/CPU.scala 94:19] + virtual_address <= id.io.if_jump_address @[src/main/scala/riscv/core/fivestage/CPU.scala 95:23] + else : + when mmu.io.pa_valid : @[src/main/scala/riscv/core/fivestage/CPU.scala 96:33] + mem_access_state <= UInt<2>("h3") @[src/main/scala/riscv/core/fivestage/CPU.scala 97:24] + bus_granted <= UInt<2>("h2") @[src/main/scala/riscv/core/fivestage/CPU.scala 98:19] + physical_address <= mmu.io.pa @[src/main/scala/riscv/core/fivestage/CPU.scala 99:24] + else : + node _T_9 = eq(mem_access_state, UInt<1>("h1")) @[src/main/scala/riscv/core/fivestage/CPU.scala 101:31] + when _T_9 : @[src/main/scala/riscv/core/fivestage/CPU.scala 101:72] + when mem.io.bus.request : @[src/main/scala/riscv/core/fivestage/CPU.scala 103:30] + mmu_restart <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/CPU.scala 104:19] + when mmu.io.restart_done : @[src/main/scala/riscv/core/fivestage/CPU.scala 105:33] + mmu_restart <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/CPU.scala 106:21] + mem_access_state <= UInt<2>("h2") @[src/main/scala/riscv/core/fivestage/CPU.scala 107:26] + bus_granted <= UInt<2>("h3") @[src/main/scala/riscv/core/fivestage/CPU.scala 108:21] + virtual_address <= ex2mem.io.output_alu_result @[src/main/scala/riscv/core/fivestage/CPU.scala 109:25] + else : + when pending : @[src/main/scala/riscv/core/fivestage/CPU.scala 112:21] + when mmu.io.restart_done : @[src/main/scala/riscv/core/fivestage/CPU.scala 113:35] + mmu_restart <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/CPU.scala 114:23] + pending <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/CPU.scala 115:19] + mem_access_state <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/CPU.scala 116:28] + bus_granted <= UInt<3>("h4") @[src/main/scala/riscv/core/fivestage/CPU.scala 117:23] + virtual_address <= inst_fetch.io.id_instruction_address @[src/main/scala/riscv/core/fivestage/CPU.scala 118:27] + else : + node _T_10 = eq(id.io.if_jump_flag, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CPU.scala 121:14] + node _T_11 = and(_T_10, mmu.io.pa_valid) @[src/main/scala/riscv/core/fivestage/CPU.scala 121:34] + when _T_11 : @[src/main/scala/riscv/core/fivestage/CPU.scala 121:54] + mem_access_state <= UInt<3>("h4") @[src/main/scala/riscv/core/fivestage/CPU.scala 122:28] + bus_granted <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/CPU.scala 123:23] + physical_address <= mmu.io.pa @[src/main/scala/riscv/core/fivestage/CPU.scala 124:28] + when id.io.if_jump_flag : @[src/main/scala/riscv/core/fivestage/CPU.scala 128:32] + mmu_restart <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/CPU.scala 129:21] + pending <= UInt<1>("h1") @[src/main/scala/riscv/core/fivestage/CPU.scala 130:17] + else : + node _T_12 = eq(mem_access_state, UInt<2>("h3")) @[src/main/scala/riscv/core/fivestage/CPU.scala 133:31] + when _T_12 : @[src/main/scala/riscv/core/fivestage/CPU.scala 133:62] + node _T_13 = or(mem.io.bus.read_valid, mem.io.bus.write_valid) @[src/main/scala/riscv/core/fivestage/CPU.scala 134:32] + when _T_13 : @[src/main/scala/riscv/core/fivestage/CPU.scala 134:59] + mem_access_state <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/CPU.scala 135:24] + bus_granted <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/CPU.scala 136:19] + else : + node _T_14 = eq(mem_access_state, UInt<3>("h4")) @[src/main/scala/riscv/core/fivestage/CPU.scala 138:31] + when _T_14 : @[src/main/scala/riscv/core/fivestage/CPU.scala 138:61] + when inst_fetch.io.bus.read_valid : @[src/main/scala/riscv/core/fivestage/CPU.scala 139:40] + bus_granted <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/CPU.scala 140:19] + mem_access_state <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/CPU.scala 141:24] + node _T_15 = eq(bus_granted, UInt<3>("h4")) @[src/main/scala/riscv/core/fivestage/CPU.scala 145:20] + node _T_16 = eq(bus_granted, UInt<2>("h3")) @[src/main/scala/riscv/core/fivestage/CPU.scala 145:65] + node _T_17 = or(_T_15, _T_16) @[src/main/scala/riscv/core/fivestage/CPU.scala 145:50] + when _T_17 : @[src/main/scala/riscv/core/fivestage/CPU.scala 145:97] + io.bus_address <= mmu.io.bus.address @[src/main/scala/riscv/core/fivestage/CPU.scala 146:20] + axi4_master.io.bundle.read <= mmu.io.bus.read @[src/main/scala/riscv/core/fivestage/CPU.scala 147:32] + axi4_master.io.bundle.address <= mmu.io.bus.address @[src/main/scala/riscv/core/fivestage/CPU.scala 148:35] + axi4_master.io.bundle.write <= mmu.io.bus.write @[src/main/scala/riscv/core/fivestage/CPU.scala 149:33] + axi4_master.io.bundle.write_data <= mmu.io.bus.write_data @[src/main/scala/riscv/core/fivestage/CPU.scala 150:38] + axi4_master.io.bundle.write_strobe[0] <= mmu.io.bus.write_strobe[0] @[src/main/scala/riscv/core/fivestage/CPU.scala 151:40] + axi4_master.io.bundle.write_strobe[1] <= mmu.io.bus.write_strobe[1] @[src/main/scala/riscv/core/fivestage/CPU.scala 151:40] + axi4_master.io.bundle.write_strobe[2] <= mmu.io.bus.write_strobe[2] @[src/main/scala/riscv/core/fivestage/CPU.scala 151:40] + axi4_master.io.bundle.write_strobe[3] <= mmu.io.bus.write_strobe[3] @[src/main/scala/riscv/core/fivestage/CPU.scala 151:40] + else : + node _T_18 = eq(bus_granted, UInt<2>("h2")) @[src/main/scala/riscv/core/fivestage/CPU.scala 152:26] + when _T_18 : @[src/main/scala/riscv/core/fivestage/CPU.scala 152:54] + io.bus_address <= mem.io.bus.address @[src/main/scala/riscv/core/fivestage/CPU.scala 153:20] + axi4_master.io.bundle.read <= mem.io.bus.read @[src/main/scala/riscv/core/fivestage/CPU.scala 154:32] + axi4_master.io.bundle.address <= mem.io.bus.address @[src/main/scala/riscv/core/fivestage/CPU.scala 155:35] + axi4_master.io.bundle.write <= mem.io.bus.write @[src/main/scala/riscv/core/fivestage/CPU.scala 156:33] + axi4_master.io.bundle.write_data <= mem.io.bus.write_data @[src/main/scala/riscv/core/fivestage/CPU.scala 157:38] + axi4_master.io.bundle.write_strobe[0] <= mem.io.bus.write_strobe[0] @[src/main/scala/riscv/core/fivestage/CPU.scala 158:40] + axi4_master.io.bundle.write_strobe[1] <= mem.io.bus.write_strobe[1] @[src/main/scala/riscv/core/fivestage/CPU.scala 158:40] + axi4_master.io.bundle.write_strobe[2] <= mem.io.bus.write_strobe[2] @[src/main/scala/riscv/core/fivestage/CPU.scala 158:40] + axi4_master.io.bundle.write_strobe[3] <= mem.io.bus.write_strobe[3] @[src/main/scala/riscv/core/fivestage/CPU.scala 158:40] + else : + io.bus_address <= inst_fetch.io.bus.address @[src/main/scala/riscv/core/fivestage/CPU.scala 160:20] + axi4_master.io.bundle.read <= inst_fetch.io.bus.read @[src/main/scala/riscv/core/fivestage/CPU.scala 161:32] + axi4_master.io.bundle.address <= inst_fetch.io.bus.address @[src/main/scala/riscv/core/fivestage/CPU.scala 162:35] + axi4_master.io.bundle.write <= inst_fetch.io.bus.write @[src/main/scala/riscv/core/fivestage/CPU.scala 163:33] + axi4_master.io.bundle.write_data <= inst_fetch.io.bus.write_data @[src/main/scala/riscv/core/fivestage/CPU.scala 164:38] + axi4_master.io.bundle.write_strobe[0] <= inst_fetch.io.bus.write_strobe[0] @[src/main/scala/riscv/core/fivestage/CPU.scala 165:40] + axi4_master.io.bundle.write_strobe[1] <= inst_fetch.io.bus.write_strobe[1] @[src/main/scala/riscv/core/fivestage/CPU.scala 165:40] + axi4_master.io.bundle.write_strobe[2] <= inst_fetch.io.bus.write_strobe[2] @[src/main/scala/riscv/core/fivestage/CPU.scala 165:40] + axi4_master.io.bundle.write_strobe[3] <= inst_fetch.io.bus.write_strobe[3] @[src/main/scala/riscv/core/fivestage/CPU.scala 165:40] + node _inst_fetch_io_bus_read_valid_T = eq(bus_granted, UInt<1>("h1")) @[src/main/scala/riscv/core/fivestage/CPU.scala 169:17] + node _inst_fetch_io_bus_read_valid_T_1 = and(_inst_fetch_io_bus_read_valid_T, io.instruction_valid) @[src/main/scala/riscv/core/fivestage/CPU.scala 169:43] + node _inst_fetch_io_bus_read_valid_T_2 = mux(_inst_fetch_io_bus_read_valid_T_1, axi4_master.io.bundle.read_valid, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CPU.scala 168:38] + inst_fetch.io.bus.read_valid <= _inst_fetch_io_bus_read_valid_T_2 @[src/main/scala/riscv/core/fivestage/CPU.scala 168:32] + node _inst_fetch_io_bus_read_data_T = eq(bus_granted, UInt<1>("h1")) @[src/main/scala/riscv/core/fivestage/CPU.scala 174:17] + node _inst_fetch_io_bus_read_data_T_1 = and(_inst_fetch_io_bus_read_data_T, io.instruction_valid) @[src/main/scala/riscv/core/fivestage/CPU.scala 174:43] + node _inst_fetch_io_bus_read_data_T_2 = mux(_inst_fetch_io_bus_read_data_T_1, axi4_master.io.bundle.read_data, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CPU.scala 173:37] + inst_fetch.io.bus.read_data <= _inst_fetch_io_bus_read_data_T_2 @[src/main/scala/riscv/core/fivestage/CPU.scala 173:31] + inst_fetch.io.bus.write_valid <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/CPU.scala 178:33] + node _inst_fetch_io_bus_busy_T = eq(bus_granted, UInt<1>("h1")) @[src/main/scala/riscv/core/fivestage/CPU.scala 180:17] + node _inst_fetch_io_bus_busy_T_1 = and(_inst_fetch_io_bus_busy_T, io.instruction_valid) @[src/main/scala/riscv/core/fivestage/CPU.scala 180:43] + node _inst_fetch_io_bus_busy_T_2 = mux(_inst_fetch_io_bus_busy_T_1, axi4_master.io.bundle.busy, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CPU.scala 179:32] + inst_fetch.io.bus.busy <= _inst_fetch_io_bus_busy_T_2 @[src/main/scala/riscv/core/fivestage/CPU.scala 179:26] + node _mem_io_bus_read_valid_T = eq(bus_granted, UInt<2>("h2")) @[src/main/scala/riscv/core/fivestage/CPU.scala 185:17] + node _mem_io_bus_read_valid_T_1 = mux(_mem_io_bus_read_valid_T, axi4_master.io.bundle.read_valid, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CPU.scala 184:31] + mem.io.bus.read_valid <= _mem_io_bus_read_valid_T_1 @[src/main/scala/riscv/core/fivestage/CPU.scala 184:25] + node _mem_io_bus_read_data_T = eq(bus_granted, UInt<2>("h2")) @[src/main/scala/riscv/core/fivestage/CPU.scala 190:17] + node _mem_io_bus_read_data_T_1 = mux(_mem_io_bus_read_data_T, axi4_master.io.bundle.read_data, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CPU.scala 189:30] + mem.io.bus.read_data <= _mem_io_bus_read_data_T_1 @[src/main/scala/riscv/core/fivestage/CPU.scala 189:24] + node _mem_io_bus_write_valid_T = eq(bus_granted, UInt<2>("h2")) @[src/main/scala/riscv/core/fivestage/CPU.scala 195:17] + node _mem_io_bus_write_valid_T_1 = mux(_mem_io_bus_write_valid_T, axi4_master.io.bundle.write_valid, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CPU.scala 194:32] + mem.io.bus.write_valid <= _mem_io_bus_write_valid_T_1 @[src/main/scala/riscv/core/fivestage/CPU.scala 194:26] + node _mem_io_bus_busy_T = eq(bus_granted, UInt<2>("h2")) @[src/main/scala/riscv/core/fivestage/CPU.scala 200:17] + node _mem_io_bus_busy_T_1 = mux(_mem_io_bus_busy_T, axi4_master.io.bundle.busy, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CPU.scala 199:25] + mem.io.bus.busy <= _mem_io_bus_busy_T_1 @[src/main/scala/riscv/core/fivestage/CPU.scala 199:19] + node _mmu_io_bus_read_valid_T = eq(bus_granted, UInt<3>("h4")) @[src/main/scala/riscv/core/fivestage/CPU.scala 205:17] + node _mmu_io_bus_read_valid_T_1 = eq(bus_granted, UInt<2>("h3")) @[src/main/scala/riscv/core/fivestage/CPU.scala 205:62] + node _mmu_io_bus_read_valid_T_2 = or(_mmu_io_bus_read_valid_T, _mmu_io_bus_read_valid_T_1) @[src/main/scala/riscv/core/fivestage/CPU.scala 205:47] + node _mmu_io_bus_read_valid_T_3 = mux(_mmu_io_bus_read_valid_T_2, axi4_master.io.bundle.read_valid, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CPU.scala 204:31] + mmu.io.bus.read_valid <= _mmu_io_bus_read_valid_T_3 @[src/main/scala/riscv/core/fivestage/CPU.scala 204:25] + node _mmu_io_bus_read_data_T = eq(bus_granted, UInt<3>("h4")) @[src/main/scala/riscv/core/fivestage/CPU.scala 210:17] + node _mmu_io_bus_read_data_T_1 = eq(bus_granted, UInt<2>("h3")) @[src/main/scala/riscv/core/fivestage/CPU.scala 210:62] + node _mmu_io_bus_read_data_T_2 = or(_mmu_io_bus_read_data_T, _mmu_io_bus_read_data_T_1) @[src/main/scala/riscv/core/fivestage/CPU.scala 210:47] + node _mmu_io_bus_read_data_T_3 = mux(_mmu_io_bus_read_data_T_2, axi4_master.io.bundle.read_data, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CPU.scala 209:30] + mmu.io.bus.read_data <= _mmu_io_bus_read_data_T_3 @[src/main/scala/riscv/core/fivestage/CPU.scala 209:24] + node _mmu_io_bus_write_valid_T = eq(bus_granted, UInt<3>("h4")) @[src/main/scala/riscv/core/fivestage/CPU.scala 215:17] + node _mmu_io_bus_write_valid_T_1 = eq(bus_granted, UInt<2>("h3")) @[src/main/scala/riscv/core/fivestage/CPU.scala 215:62] + node _mmu_io_bus_write_valid_T_2 = or(_mmu_io_bus_write_valid_T, _mmu_io_bus_write_valid_T_1) @[src/main/scala/riscv/core/fivestage/CPU.scala 215:47] + node _mmu_io_bus_write_valid_T_3 = mux(_mmu_io_bus_write_valid_T_2, axi4_master.io.bundle.write_valid, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CPU.scala 214:32] + mmu.io.bus.write_valid <= _mmu_io_bus_write_valid_T_3 @[src/main/scala/riscv/core/fivestage/CPU.scala 214:26] + node _mmu_io_bus_busy_T = eq(bus_granted, UInt<3>("h4")) @[src/main/scala/riscv/core/fivestage/CPU.scala 220:17] + node _mmu_io_bus_busy_T_1 = eq(bus_granted, UInt<2>("h3")) @[src/main/scala/riscv/core/fivestage/CPU.scala 220:62] + node _mmu_io_bus_busy_T_2 = or(_mmu_io_bus_busy_T, _mmu_io_bus_busy_T_1) @[src/main/scala/riscv/core/fivestage/CPU.scala 220:47] + node _mmu_io_bus_busy_T_3 = mux(_mmu_io_bus_busy_T_2, axi4_master.io.bundle.busy, UInt<1>("h0")) @[src/main/scala/riscv/core/fivestage/CPU.scala 219:25] + mmu.io.bus.busy <= _mmu_io_bus_busy_T_3 @[src/main/scala/riscv/core/fivestage/CPU.scala 219:19] + mmu.io.instructions <= ex2mem.io.output_instruction @[src/main/scala/riscv/core/fivestage/CPU.scala 225:23] + mmu.io.instructions_address <= ex2mem.io.output_instruction_address @[src/main/scala/riscv/core/fivestage/CPU.scala 226:31] + mmu.io.virtual_address <= virtual_address @[src/main/scala/riscv/core/fivestage/CPU.scala 227:26] + node _mmu_io_bus_granted_T = eq(bus_granted, UInt<2>("h3")) @[src/main/scala/riscv/core/fivestage/CPU.scala 228:37] + node _mmu_io_bus_granted_T_1 = eq(bus_granted, UInt<3>("h4")) @[src/main/scala/riscv/core/fivestage/CPU.scala 228:83] + node _mmu_io_bus_granted_T_2 = or(_mmu_io_bus_granted_T, _mmu_io_bus_granted_T_1) @[src/main/scala/riscv/core/fivestage/CPU.scala 228:68] + mmu.io.bus.granted <= _mmu_io_bus_granted_T_2 @[src/main/scala/riscv/core/fivestage/CPU.scala 228:22] + mmu.io.page_fault_responed <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/CPU.scala 229:30] + node _mmu_io_ppn_from_satp_T = bits(csr_regs.io.mmu_csr_satp, 21, 0) @[src/main/scala/riscv/core/fivestage/CPU.scala 230:51] + mmu.io.ppn_from_satp <= _mmu_io_ppn_from_satp_T @[src/main/scala/riscv/core/fivestage/CPU.scala 230:24] + mmu.io.page_fault_responed <= clint.io.exception_token @[src/main/scala/riscv/core/fivestage/CPU.scala 231:30] + node _mmu_io_mmu_occupied_by_mem_T = eq(bus_granted, UInt<2>("h3")) @[src/main/scala/riscv/core/fivestage/CPU.scala 232:45] + mmu.io.mmu_occupied_by_mem <= _mmu_io_mmu_occupied_by_mem_T @[src/main/scala/riscv/core/fivestage/CPU.scala 232:30] + mmu.io.restart <= mmu_restart @[src/main/scala/riscv/core/fivestage/CPU.scala 233:18] + node _inst_fetch_io_bus_granted_T = eq(bus_granted, UInt<1>("h1")) @[src/main/scala/riscv/core/fivestage/CPU.scala 235:44] + inst_fetch.io.bus.granted <= _inst_fetch_io_bus_granted_T @[src/main/scala/riscv/core/fivestage/CPU.scala 235:29] + inst_fetch.io.physical_address <= physical_address @[src/main/scala/riscv/core/fivestage/CPU.scala 236:34] + node _mem_io_bus_granted_T = eq(bus_granted, UInt<2>("h2")) @[src/main/scala/riscv/core/fivestage/CPU.scala 238:37] + mem.io.bus.granted <= _mem_io_bus_granted_T @[src/main/scala/riscv/core/fivestage/CPU.scala 238:22] + mem.io.physical_address <= physical_address @[src/main/scala/riscv/core/fivestage/CPU.scala 239:27] + ctrl.io.jump_flag <= id.io.if_jump_flag @[src/main/scala/riscv/core/fivestage/CPU.scala 241:21] + ctrl.io.jump_instruction_id <= id.io.ctrl_jump_instruction @[src/main/scala/riscv/core/fivestage/CPU.scala 242:31] + ctrl.io.stall_flag_if <= inst_fetch.io.ctrl_stall_flag @[src/main/scala/riscv/core/fivestage/CPU.scala 243:25] + ctrl.io.stall_flag_mem <= mem.io.ctrl_stall_flag @[src/main/scala/riscv/core/fivestage/CPU.scala 244:26] + ctrl.io.stall_flag_clint <= clint.io.ctrl_stall_flag @[src/main/scala/riscv/core/fivestage/CPU.scala 245:28] + ctrl.io.stall_flag_bus <= io.stall_flag_bus @[src/main/scala/riscv/core/fivestage/CPU.scala 246:26] + ctrl.io.rs1_id <= id.io.regs_reg1_read_address @[src/main/scala/riscv/core/fivestage/CPU.scala 247:18] + ctrl.io.rs2_id <= id.io.regs_reg2_read_address @[src/main/scala/riscv/core/fivestage/CPU.scala 248:18] + ctrl.io.memory_read_enable_ex <= id2ex.io.output_memory_read_enable @[src/main/scala/riscv/core/fivestage/CPU.scala 249:33] + ctrl.io.rd_ex <= id2ex.io.output_regs_write_address @[src/main/scala/riscv/core/fivestage/CPU.scala 250:17] + ctrl.io.memory_read_enable_mem <= ex2mem.io.output_memory_read_enable @[src/main/scala/riscv/core/fivestage/CPU.scala 251:34] + ctrl.io.rd_mem <= ex2mem.io.output_regs_write_address @[src/main/scala/riscv/core/fivestage/CPU.scala 252:18] + ctrl.io.csr_start_paging <= csr_regs.io.start_paging @[src/main/scala/riscv/core/fivestage/CPU.scala 253:28] + regs.io.write_enable <= mem2wb.io.output_regs_write_enable @[src/main/scala/riscv/core/fivestage/CPU.scala 255:24] + regs.io.write_address <= mem2wb.io.output_regs_write_address @[src/main/scala/riscv/core/fivestage/CPU.scala 256:25] + regs.io.write_data <= wb.io.regs_write_data @[src/main/scala/riscv/core/fivestage/CPU.scala 257:22] + regs.io.read_address1 <= id.io.regs_reg1_read_address @[src/main/scala/riscv/core/fivestage/CPU.scala 258:25] + regs.io.read_address2 <= id.io.regs_reg2_read_address @[src/main/scala/riscv/core/fivestage/CPU.scala 259:25] + regs.io.debug_read_address <= io.debug_read_address @[src/main/scala/riscv/core/fivestage/CPU.scala 261:30] + io.debug_read_data <= regs.io.debug_read_data @[src/main/scala/riscv/core/fivestage/CPU.scala 262:22] + inst_fetch.io.stall_flag_ctrl <= ctrl.io.pc_stall @[src/main/scala/riscv/core/fivestage/CPU.scala 264:33] + inst_fetch.io.jump_flag_id <= id.io.if_jump_flag @[src/main/scala/riscv/core/fivestage/CPU.scala 265:30] + inst_fetch.io.jump_address_id <= id.io.if_jump_address @[src/main/scala/riscv/core/fivestage/CPU.scala 266:33] + if2id.io.stall_flag <= ctrl.io.if_stall @[src/main/scala/riscv/core/fivestage/CPU.scala 268:23] + if2id.io.flush_enable <= ctrl.io.if_flush @[src/main/scala/riscv/core/fivestage/CPU.scala 269:25] + if2id.io.instruction <= inst_fetch.io.id_instruction @[src/main/scala/riscv/core/fivestage/CPU.scala 270:24] + if2id.io.instruction_address <= inst_fetch.io.id_instruction_address @[src/main/scala/riscv/core/fivestage/CPU.scala 271:32] + if2id.io.interrupt_flag <= io.interrupt_flag @[src/main/scala/riscv/core/fivestage/CPU.scala 272:27] + id.io.instruction <= if2id.io.output_instruction @[src/main/scala/riscv/core/fivestage/CPU.scala 274:21] + id.io.instruction_address <= if2id.io.output_instruction_address @[src/main/scala/riscv/core/fivestage/CPU.scala 275:29] + id.io.reg1_data <= regs.io.read_data1 @[src/main/scala/riscv/core/fivestage/CPU.scala 276:19] + id.io.reg2_data <= regs.io.read_data2 @[src/main/scala/riscv/core/fivestage/CPU.scala 277:19] + id.io.forward_from_mem <= mem.io.forward_data @[src/main/scala/riscv/core/fivestage/CPU.scala 278:26] + id.io.forward_from_wb <= wb.io.regs_write_data @[src/main/scala/riscv/core/fivestage/CPU.scala 279:25] + id.io.reg1_forward <= forwarding.io.reg1_forward_id @[src/main/scala/riscv/core/fivestage/CPU.scala 280:22] + id.io.reg2_forward <= forwarding.io.reg2_forward_id @[src/main/scala/riscv/core/fivestage/CPU.scala 281:22] + id.io.interrupt_assert <= clint.io.id_interrupt_assert @[src/main/scala/riscv/core/fivestage/CPU.scala 282:26] + id.io.interrupt_handler_address <= clint.io.id_interrupt_handler_address @[src/main/scala/riscv/core/fivestage/CPU.scala 283:35] + id2ex.io.stall_flag <= ctrl.io.id_stall @[src/main/scala/riscv/core/fivestage/CPU.scala 285:23] + id2ex.io.flush_enable <= ctrl.io.id_flush @[src/main/scala/riscv/core/fivestage/CPU.scala 286:25] + id2ex.io.instruction <= if2id.io.output_instruction @[src/main/scala/riscv/core/fivestage/CPU.scala 287:24] + id2ex.io.instruction_address <= if2id.io.output_instruction_address @[src/main/scala/riscv/core/fivestage/CPU.scala 288:32] + id2ex.io.regs_write_enable <= id.io.ex_reg_write_enable @[src/main/scala/riscv/core/fivestage/CPU.scala 289:30] + id2ex.io.regs_write_address <= id.io.ex_reg_write_address @[src/main/scala/riscv/core/fivestage/CPU.scala 290:31] + id2ex.io.regs_write_source <= id.io.ex_reg_write_source @[src/main/scala/riscv/core/fivestage/CPU.scala 291:30] + id2ex.io.reg1_data <= regs.io.read_data1 @[src/main/scala/riscv/core/fivestage/CPU.scala 292:22] + id2ex.io.reg2_data <= regs.io.read_data2 @[src/main/scala/riscv/core/fivestage/CPU.scala 293:22] + id2ex.io.immediate <= id.io.ex_immediate @[src/main/scala/riscv/core/fivestage/CPU.scala 294:22] + id2ex.io.aluop1_source <= id.io.ex_aluop1_source @[src/main/scala/riscv/core/fivestage/CPU.scala 295:26] + id2ex.io.aluop2_source <= id.io.ex_aluop2_source @[src/main/scala/riscv/core/fivestage/CPU.scala 296:26] + id2ex.io.csr_write_enable <= id.io.ex_csr_write_enable @[src/main/scala/riscv/core/fivestage/CPU.scala 297:29] + id2ex.io.csr_address <= id.io.ex_csr_address @[src/main/scala/riscv/core/fivestage/CPU.scala 298:24] + id2ex.io.memory_read_enable <= id.io.ex_memory_read_enable @[src/main/scala/riscv/core/fivestage/CPU.scala 299:31] + id2ex.io.memory_write_enable <= id.io.ex_memory_write_enable @[src/main/scala/riscv/core/fivestage/CPU.scala 300:32] + id2ex.io.csr_read_data <= csr_regs.io.id_reg_data @[src/main/scala/riscv/core/fivestage/CPU.scala 301:26] + ex.io.instruction <= id2ex.io.output_instruction @[src/main/scala/riscv/core/fivestage/CPU.scala 303:21] + ex.io.instruction_address <= id2ex.io.output_instruction_address @[src/main/scala/riscv/core/fivestage/CPU.scala 304:29] + ex.io.reg1_data <= id2ex.io.output_reg1_data @[src/main/scala/riscv/core/fivestage/CPU.scala 305:19] + ex.io.reg2_data <= id2ex.io.output_reg2_data @[src/main/scala/riscv/core/fivestage/CPU.scala 306:19] + ex.io.immediate <= id2ex.io.output_immediate @[src/main/scala/riscv/core/fivestage/CPU.scala 307:19] + ex.io.aluop1_source <= id2ex.io.output_aluop1_source @[src/main/scala/riscv/core/fivestage/CPU.scala 308:23] + ex.io.aluop2_source <= id2ex.io.output_aluop2_source @[src/main/scala/riscv/core/fivestage/CPU.scala 309:23] + ex.io.csr_read_data <= id2ex.io.output_csr_read_data @[src/main/scala/riscv/core/fivestage/CPU.scala 310:23] + ex.io.forward_from_mem <= mem.io.forward_data @[src/main/scala/riscv/core/fivestage/CPU.scala 311:26] + ex.io.forward_from_wb <= wb.io.regs_write_data @[src/main/scala/riscv/core/fivestage/CPU.scala 312:25] + ex.io.reg1_forward <= forwarding.io.reg1_forward_ex @[src/main/scala/riscv/core/fivestage/CPU.scala 313:22] + ex.io.reg2_forward <= forwarding.io.reg2_forward_ex @[src/main/scala/riscv/core/fivestage/CPU.scala 314:22] + ex2mem.io.stall_flag <= ctrl.io.ex_stall @[src/main/scala/riscv/core/fivestage/CPU.scala 316:24] + ex2mem.io.flush_enable <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/CPU.scala 317:26] + ex2mem.io.regs_write_enable <= id2ex.io.output_regs_write_enable @[src/main/scala/riscv/core/fivestage/CPU.scala 318:31] + ex2mem.io.regs_write_source <= id2ex.io.output_regs_write_source @[src/main/scala/riscv/core/fivestage/CPU.scala 319:31] + ex2mem.io.regs_write_address <= id2ex.io.output_regs_write_address @[src/main/scala/riscv/core/fivestage/CPU.scala 320:32] + ex2mem.io.instruction_address <= id2ex.io.output_instruction_address @[src/main/scala/riscv/core/fivestage/CPU.scala 321:33] + ex2mem.io.instruction <= id2ex.io.output_instruction @[src/main/scala/riscv/core/fivestage/CPU.scala 322:25] + ex2mem.io.reg1_data <= id2ex.io.output_reg1_data @[src/main/scala/riscv/core/fivestage/CPU.scala 323:23] + ex2mem.io.reg2_data <= id2ex.io.output_reg2_data @[src/main/scala/riscv/core/fivestage/CPU.scala 324:23] + ex2mem.io.memory_read_enable <= id2ex.io.output_memory_read_enable @[src/main/scala/riscv/core/fivestage/CPU.scala 325:32] + ex2mem.io.memory_write_enable <= id2ex.io.output_memory_write_enable @[src/main/scala/riscv/core/fivestage/CPU.scala 326:33] + ex2mem.io.alu_result <= ex.io.mem_alu_result @[src/main/scala/riscv/core/fivestage/CPU.scala 327:24] + ex2mem.io.csr_read_data <= id2ex.io.output_csr_read_data @[src/main/scala/riscv/core/fivestage/CPU.scala 328:27] + mem.io.alu_result <= ex2mem.io.output_alu_result @[src/main/scala/riscv/core/fivestage/CPU.scala 330:21] + mem.io.reg2_data <= ex2mem.io.output_reg2_data @[src/main/scala/riscv/core/fivestage/CPU.scala 331:20] + mem.io.memory_read_enable <= ex2mem.io.output_memory_read_enable @[src/main/scala/riscv/core/fivestage/CPU.scala 332:29] + mem.io.memory_write_enable <= ex2mem.io.output_memory_write_enable @[src/main/scala/riscv/core/fivestage/CPU.scala 333:30] + node _mem_io_funct3_T = bits(ex2mem.io.output_instruction, 14, 12) @[src/main/scala/riscv/core/fivestage/CPU.scala 334:48] + mem.io.funct3 <= _mem_io_funct3_T @[src/main/scala/riscv/core/fivestage/CPU.scala 334:17] + mem.io.regs_write_source <= ex2mem.io.output_regs_write_source @[src/main/scala/riscv/core/fivestage/CPU.scala 335:28] + mem.io.csr_read_data <= ex2mem.io.output_csr_read_data @[src/main/scala/riscv/core/fivestage/CPU.scala 336:24] + mem.io.clint_exception_token <= clint.io.exception_token @[src/main/scala/riscv/core/fivestage/CPU.scala 337:32] + mem2wb.io.instruction_address <= ex2mem.io.output_instruction_address @[src/main/scala/riscv/core/fivestage/CPU.scala 339:33] + mem2wb.io.alu_result <= ex2mem.io.output_alu_result @[src/main/scala/riscv/core/fivestage/CPU.scala 340:24] + mem2wb.io.regs_write_enable <= ex2mem.io.output_regs_write_enable @[src/main/scala/riscv/core/fivestage/CPU.scala 341:31] + mem2wb.io.regs_write_source <= ex2mem.io.output_regs_write_source @[src/main/scala/riscv/core/fivestage/CPU.scala 342:31] + mem2wb.io.regs_write_address <= ex2mem.io.output_regs_write_address @[src/main/scala/riscv/core/fivestage/CPU.scala 343:32] + mem2wb.io.memory_read_data <= mem.io.wb_memory_read_data @[src/main/scala/riscv/core/fivestage/CPU.scala 344:30] + mem2wb.io.csr_read_data <= ex2mem.io.output_csr_read_data @[src/main/scala/riscv/core/fivestage/CPU.scala 345:27] + wb.io.instruction_address <= mem2wb.io.output_instruction_address @[src/main/scala/riscv/core/fivestage/CPU.scala 347:29] + wb.io.alu_result <= mem2wb.io.output_alu_result @[src/main/scala/riscv/core/fivestage/CPU.scala 348:20] + wb.io.memory_read_data <= mem2wb.io.output_memory_read_data @[src/main/scala/riscv/core/fivestage/CPU.scala 349:26] + wb.io.regs_write_source <= mem2wb.io.output_regs_write_source @[src/main/scala/riscv/core/fivestage/CPU.scala 350:27] + wb.io.csr_read_data <= mem2wb.io.output_csr_read_data @[src/main/scala/riscv/core/fivestage/CPU.scala 351:23] + forwarding.io.rs1_id <= id.io.regs_reg1_read_address @[src/main/scala/riscv/core/fivestage/CPU.scala 353:24] + forwarding.io.rs2_id <= id.io.regs_reg2_read_address @[src/main/scala/riscv/core/fivestage/CPU.scala 354:24] + node _forwarding_io_rs1_ex_T = bits(id2ex.io.output_instruction, 19, 15) @[src/main/scala/riscv/core/fivestage/CPU.scala 355:54] + forwarding.io.rs1_ex <= _forwarding_io_rs1_ex_T @[src/main/scala/riscv/core/fivestage/CPU.scala 355:24] + node _forwarding_io_rs2_ex_T = bits(id2ex.io.output_instruction, 24, 20) @[src/main/scala/riscv/core/fivestage/CPU.scala 356:54] + forwarding.io.rs2_ex <= _forwarding_io_rs2_ex_T @[src/main/scala/riscv/core/fivestage/CPU.scala 356:24] + forwarding.io.rd_mem <= ex2mem.io.output_regs_write_address @[src/main/scala/riscv/core/fivestage/CPU.scala 357:24] + forwarding.io.reg_write_enable_mem <= ex2mem.io.output_regs_write_enable @[src/main/scala/riscv/core/fivestage/CPU.scala 358:38] + forwarding.io.rd_wb <= mem2wb.io.output_regs_write_address @[src/main/scala/riscv/core/fivestage/CPU.scala 359:23] + forwarding.io.reg_write_enable_wb <= mem2wb.io.output_regs_write_enable @[src/main/scala/riscv/core/fivestage/CPU.scala 360:37] + clint.io.instruction <= if2id.io.output_instruction @[src/main/scala/riscv/core/fivestage/CPU.scala 362:24] + clint.io.instruction_address_if <= inst_fetch.io.id_instruction_address @[src/main/scala/riscv/core/fivestage/CPU.scala 363:35] + clint.io.jump_flag <= id.io.if_jump_flag @[src/main/scala/riscv/core/fivestage/CPU.scala 364:22] + clint.io.jump_address <= id.io.clint_jump_address @[src/main/scala/riscv/core/fivestage/CPU.scala 365:25] + clint.io.csr_mepc <= csr_regs.io.clint_csr_mepc @[src/main/scala/riscv/core/fivestage/CPU.scala 366:21] + clint.io.csr_mtvec <= csr_regs.io.clint_csr_mtvec @[src/main/scala/riscv/core/fivestage/CPU.scala 367:22] + clint.io.csr_mstatus <= csr_regs.io.clint_csr_mstatus @[src/main/scala/riscv/core/fivestage/CPU.scala 368:24] + clint.io.interrupt_enable <= csr_regs.io.interrupt_enable @[src/main/scala/riscv/core/fivestage/CPU.scala 369:29] + clint.io.interrupt_flag <= if2id.io.output_interrupt_flag @[src/main/scala/riscv/core/fivestage/CPU.scala 370:27] + clint.io.exception_signal <= mmu.io.page_fault_signals @[src/main/scala/riscv/core/fivestage/CPU.scala 372:29] + clint.io.instruction_address_cause_exception <= mmu.io.epc @[src/main/scala/riscv/core/fivestage/CPU.scala 373:48] + clint.io.exception_val <= mmu.io.va_cause_page_fault @[src/main/scala/riscv/core/fivestage/CPU.scala 374:26] + clint.io.exception_cause <= mmu.io.ecause @[src/main/scala/riscv/core/fivestage/CPU.scala 375:28] + csr_regs.io.reg_write_enable_ex <= id2ex.io.output_csr_write_enable @[src/main/scala/riscv/core/fivestage/CPU.scala 377:35] + csr_regs.io.reg_write_address_ex <= id2ex.io.output_csr_address @[src/main/scala/riscv/core/fivestage/CPU.scala 378:36] + csr_regs.io.reg_write_data_ex <= ex.io.csr_write_data @[src/main/scala/riscv/core/fivestage/CPU.scala 379:33] + csr_regs.io.reg_read_address_id <= id.io.ex_csr_address @[src/main/scala/riscv/core/fivestage/CPU.scala 380:35] + csr_regs.io.reg_write_enable_clint <= clint.io.csr_reg_write_enable @[src/main/scala/riscv/core/fivestage/CPU.scala 381:38] + csr_regs.io.reg_write_address_clint <= clint.io.csr_reg_write_address @[src/main/scala/riscv/core/fivestage/CPU.scala 382:39] + csr_regs.io.reg_write_data_clint <= clint.io.csr_reg_write_data @[src/main/scala/riscv/core/fivestage/CPU.scala 383:36] + csr_regs.io.reg_read_address_clint <= UInt<1>("h0") @[src/main/scala/riscv/core/fivestage/CPU.scala 384:38] + + module CPU_1 : + input clock : Clock + input reset : Reset + output io : { axi4_channels : { write_address_channel : { AWVALID : UInt<1>, flip AWREADY : UInt<1>, AWADDR : UInt<32>, AWPROT : UInt<3>}, write_data_channel : { WVALID : UInt<1>, flip WREADY : UInt<1>, WDATA : UInt<32>, WSTRB : UInt<4>}, write_response_channel : { flip BVALID : UInt<1>, BREADY : UInt<1>, flip BRESP : UInt<2>}, read_address_channel : { ARVALID : UInt<1>, flip ARREADY : UInt<1>, ARADDR : UInt<32>, ARPROT : UInt<3>}, read_data_channel : { flip RVALID : UInt<1>, RREADY : UInt<1>, flip RDATA : UInt<32>, flip RRESP : UInt<2>}}, bus_address : UInt<32>, flip interrupt_flag : UInt<32>, flip stall_flag_bus : UInt<1>, flip debug_read_address : UInt<5>, debug_read_data : UInt<32>, flip instruction_valid : UInt<1>, bus_busy : UInt<1>, debug : UInt<32>[6]} @[src/main/scala/riscv/core/CPU.scala 23:14] + + inst cpu of CPU @[src/main/scala/riscv/core/CPU.scala 29:23] + cpu.clock <= clock + cpu.reset <= reset + io.debug[0] <= cpu.io.debug[0] @[src/main/scala/riscv/core/CPU.scala 30:14] + io.debug[1] <= cpu.io.debug[1] @[src/main/scala/riscv/core/CPU.scala 30:14] + io.debug[2] <= cpu.io.debug[2] @[src/main/scala/riscv/core/CPU.scala 30:14] + io.debug[3] <= cpu.io.debug[3] @[src/main/scala/riscv/core/CPU.scala 30:14] + io.debug[4] <= cpu.io.debug[4] @[src/main/scala/riscv/core/CPU.scala 30:14] + io.debug[5] <= cpu.io.debug[5] @[src/main/scala/riscv/core/CPU.scala 30:14] + io.bus_busy <= cpu.io.bus_busy @[src/main/scala/riscv/core/CPU.scala 30:14] + cpu.io.instruction_valid <= io.instruction_valid @[src/main/scala/riscv/core/CPU.scala 30:14] + io.debug_read_data <= cpu.io.debug_read_data @[src/main/scala/riscv/core/CPU.scala 30:14] + cpu.io.debug_read_address <= io.debug_read_address @[src/main/scala/riscv/core/CPU.scala 30:14] + cpu.io.stall_flag_bus <= io.stall_flag_bus @[src/main/scala/riscv/core/CPU.scala 30:14] + cpu.io.interrupt_flag <= io.interrupt_flag @[src/main/scala/riscv/core/CPU.scala 30:14] + io.bus_address <= cpu.io.bus_address @[src/main/scala/riscv/core/CPU.scala 30:14] + cpu.io.axi4_channels.read_data_channel.RRESP <= io.axi4_channels.read_data_channel.RRESP @[src/main/scala/riscv/core/CPU.scala 30:14] + cpu.io.axi4_channels.read_data_channel.RDATA <= io.axi4_channels.read_data_channel.RDATA @[src/main/scala/riscv/core/CPU.scala 30:14] + io.axi4_channels.read_data_channel.RREADY <= cpu.io.axi4_channels.read_data_channel.RREADY @[src/main/scala/riscv/core/CPU.scala 30:14] + cpu.io.axi4_channels.read_data_channel.RVALID <= io.axi4_channels.read_data_channel.RVALID @[src/main/scala/riscv/core/CPU.scala 30:14] + io.axi4_channels.read_address_channel.ARPROT <= cpu.io.axi4_channels.read_address_channel.ARPROT @[src/main/scala/riscv/core/CPU.scala 30:14] + io.axi4_channels.read_address_channel.ARADDR <= cpu.io.axi4_channels.read_address_channel.ARADDR @[src/main/scala/riscv/core/CPU.scala 30:14] + cpu.io.axi4_channels.read_address_channel.ARREADY <= io.axi4_channels.read_address_channel.ARREADY @[src/main/scala/riscv/core/CPU.scala 30:14] + io.axi4_channels.read_address_channel.ARVALID <= cpu.io.axi4_channels.read_address_channel.ARVALID @[src/main/scala/riscv/core/CPU.scala 30:14] + cpu.io.axi4_channels.write_response_channel.BRESP <= io.axi4_channels.write_response_channel.BRESP @[src/main/scala/riscv/core/CPU.scala 30:14] + io.axi4_channels.write_response_channel.BREADY <= cpu.io.axi4_channels.write_response_channel.BREADY @[src/main/scala/riscv/core/CPU.scala 30:14] + cpu.io.axi4_channels.write_response_channel.BVALID <= io.axi4_channels.write_response_channel.BVALID @[src/main/scala/riscv/core/CPU.scala 30:14] + io.axi4_channels.write_data_channel.WSTRB <= cpu.io.axi4_channels.write_data_channel.WSTRB @[src/main/scala/riscv/core/CPU.scala 30:14] + io.axi4_channels.write_data_channel.WDATA <= cpu.io.axi4_channels.write_data_channel.WDATA @[src/main/scala/riscv/core/CPU.scala 30:14] + cpu.io.axi4_channels.write_data_channel.WREADY <= io.axi4_channels.write_data_channel.WREADY @[src/main/scala/riscv/core/CPU.scala 30:14] + io.axi4_channels.write_data_channel.WVALID <= cpu.io.axi4_channels.write_data_channel.WVALID @[src/main/scala/riscv/core/CPU.scala 30:14] + io.axi4_channels.write_address_channel.AWPROT <= cpu.io.axi4_channels.write_address_channel.AWPROT @[src/main/scala/riscv/core/CPU.scala 30:14] + io.axi4_channels.write_address_channel.AWADDR <= cpu.io.axi4_channels.write_address_channel.AWADDR @[src/main/scala/riscv/core/CPU.scala 30:14] + cpu.io.axi4_channels.write_address_channel.AWREADY <= io.axi4_channels.write_address_channel.AWREADY @[src/main/scala/riscv/core/CPU.scala 30:14] + io.axi4_channels.write_address_channel.AWVALID <= cpu.io.axi4_channels.write_address_channel.AWVALID @[src/main/scala/riscv/core/CPU.scala 30:14] + + module BlockRAM : + input clock : Clock + input reset : Reset + output io : { flip read_address : UInt<32>, flip write_address : UInt<32>, flip write_data : UInt<32>, flip write_enable : UInt<1>, flip write_strobe : UInt<1>[4], flip debug_read_address : UInt<32>, read_data : UInt<32>, debug_read_data : UInt<32>} @[src/main/scala/peripheral/Memory.scala 24:14] + + smem mem : UInt<8>[4] [8192] @[src/main/scala/peripheral/Memory.scala 36:24] + when io.write_enable : @[src/main/scala/peripheral/Memory.scala 37:25] + wire write_data_vec : UInt<8>[4] @[src/main/scala/peripheral/Memory.scala 38:30] + node _write_data_vec_0_T = bits(io.write_data, 7, 0) @[src/main/scala/peripheral/Memory.scala 40:41] + write_data_vec[0] <= _write_data_vec_0_T @[src/main/scala/peripheral/Memory.scala 40:25] + node _write_data_vec_1_T = bits(io.write_data, 15, 8) @[src/main/scala/peripheral/Memory.scala 40:41] + write_data_vec[1] <= _write_data_vec_1_T @[src/main/scala/peripheral/Memory.scala 40:25] + node _write_data_vec_2_T = bits(io.write_data, 23, 16) @[src/main/scala/peripheral/Memory.scala 40:41] + write_data_vec[2] <= _write_data_vec_2_T @[src/main/scala/peripheral/Memory.scala 40:25] + node _write_data_vec_3_T = bits(io.write_data, 31, 24) @[src/main/scala/peripheral/Memory.scala 40:41] + write_data_vec[3] <= _write_data_vec_3_T @[src/main/scala/peripheral/Memory.scala 40:25] + node _T = dshr(io.write_address, UInt<2>("h2")) @[src/main/scala/peripheral/Memory.scala 42:33] + node _T_1 = bits(_T, 12, 0) + write mport MPORT = mem[_T_1], clock + when io.write_strobe[0] : + MPORT[0] <= write_data_vec[0] + when io.write_strobe[1] : + MPORT[1] <= write_data_vec[1] + when io.write_strobe[2] : + MPORT[2] <= write_data_vec[2] + when io.write_strobe[3] : + MPORT[3] <= write_data_vec[3] + node _io_read_data_T = dshr(io.read_address, UInt<2>("h2")) @[src/main/scala/peripheral/Memory.scala 44:45] + wire _io_read_data_WIRE : UInt @[src/main/scala/peripheral/Memory.scala 44:27] + _io_read_data_WIRE is invalid @[src/main/scala/peripheral/Memory.scala 44:27] + when UInt<1>("h1") : @[src/main/scala/peripheral/Memory.scala 44:27] + _io_read_data_WIRE <= _io_read_data_T @[src/main/scala/peripheral/Memory.scala 44:27] + node _io_read_data_T_1 = or(_io_read_data_WIRE, UInt<13>("h0")) @[src/main/scala/peripheral/Memory.scala 44:27] + node _io_read_data_T_2 = bits(_io_read_data_T_1, 12, 0) @[src/main/scala/peripheral/Memory.scala 44:27] + read mport io_read_data_MPORT = mem[_io_read_data_T_2], clock @[src/main/scala/peripheral/Memory.scala 44:27] + node io_read_data_lo = cat(io_read_data_MPORT[1], io_read_data_MPORT[0]) @[src/main/scala/peripheral/Memory.scala 44:69] + node io_read_data_hi = cat(io_read_data_MPORT[3], io_read_data_MPORT[2]) @[src/main/scala/peripheral/Memory.scala 44:69] + node _io_read_data_T_3 = cat(io_read_data_hi, io_read_data_lo) @[src/main/scala/peripheral/Memory.scala 44:69] + io.read_data <= _io_read_data_T_3 @[src/main/scala/peripheral/Memory.scala 44:16] + node _io_debug_read_data_T = dshr(io.debug_read_address, UInt<2>("h2")) @[src/main/scala/peripheral/Memory.scala 45:57] + wire _io_debug_read_data_WIRE : UInt @[src/main/scala/peripheral/Memory.scala 45:33] + _io_debug_read_data_WIRE is invalid @[src/main/scala/peripheral/Memory.scala 45:33] + when UInt<1>("h1") : @[src/main/scala/peripheral/Memory.scala 45:33] + _io_debug_read_data_WIRE <= _io_debug_read_data_T @[src/main/scala/peripheral/Memory.scala 45:33] + node _io_debug_read_data_T_1 = or(_io_debug_read_data_WIRE, UInt<13>("h0")) @[src/main/scala/peripheral/Memory.scala 45:33] + node _io_debug_read_data_T_2 = bits(_io_debug_read_data_T_1, 12, 0) @[src/main/scala/peripheral/Memory.scala 45:33] + read mport io_debug_read_data_MPORT = mem[_io_debug_read_data_T_2], clock @[src/main/scala/peripheral/Memory.scala 45:33] + node io_debug_read_data_lo = cat(io_debug_read_data_MPORT[1], io_debug_read_data_MPORT[0]) @[src/main/scala/peripheral/Memory.scala 45:81] + node io_debug_read_data_hi = cat(io_debug_read_data_MPORT[3], io_debug_read_data_MPORT[2]) @[src/main/scala/peripheral/Memory.scala 45:81] + node _io_debug_read_data_T_3 = cat(io_debug_read_data_hi, io_debug_read_data_lo) @[src/main/scala/peripheral/Memory.scala 45:81] + io.debug_read_data <= _io_debug_read_data_T_3 @[src/main/scala/peripheral/Memory.scala 45:22] + + module AXI4LiteSlave_1 : + input clock : Clock + input reset : Reset + output io : { flip channels : { write_address_channel : { AWVALID : UInt<1>, flip AWREADY : UInt<1>, AWADDR : UInt<32>, AWPROT : UInt<3>}, write_data_channel : { WVALID : UInt<1>, flip WREADY : UInt<1>, WDATA : UInt<32>, WSTRB : UInt<4>}, write_response_channel : { flip BVALID : UInt<1>, BREADY : UInt<1>, flip BRESP : UInt<2>}, read_address_channel : { ARVALID : UInt<1>, flip ARREADY : UInt<1>, ARADDR : UInt<32>, ARPROT : UInt<3>}, read_data_channel : { flip RVALID : UInt<1>, RREADY : UInt<1>, flip RDATA : UInt<32>, flip RRESP : UInt<2>}}, bundle : { read : UInt<1>, write : UInt<1>, flip read_data : UInt<32>, flip read_valid : UInt<1>, write_data : UInt<32>, write_strobe : UInt<1>[4], address : UInt<32>}} @[src/main/scala/bus/AXI4Lite.scala 121:14] + + reg state : UInt<3>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 125:22] + reg addr : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[src/main/scala/bus/AXI4Lite.scala 126:21] + io.bundle.address <= addr @[src/main/scala/bus/AXI4Lite.scala 127:21] + reg read : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 128:21] + io.bundle.read <= read @[src/main/scala/bus/AXI4Lite.scala 129:18] + reg write : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 130:22] + io.bundle.write <= write @[src/main/scala/bus/AXI4Lite.scala 131:19] + reg write_data : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[src/main/scala/bus/AXI4Lite.scala 132:27] + io.bundle.write_data <= write_data @[src/main/scala/bus/AXI4Lite.scala 133:24] + wire _write_strobe_WIRE : UInt<1>[4] @[src/main/scala/bus/AXI4Lite.scala 134:37] + _write_strobe_WIRE[0] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 134:37] + _write_strobe_WIRE[1] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 134:37] + _write_strobe_WIRE[2] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 134:37] + _write_strobe_WIRE[3] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 134:37] + reg write_strobe : UInt<1>[4], clock with : + reset => (reset, _write_strobe_WIRE) @[src/main/scala/bus/AXI4Lite.scala 134:29] + io.bundle.write_strobe <= write_strobe @[src/main/scala/bus/AXI4Lite.scala 135:26] + reg ARREADY : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 137:24] + io.channels.read_address_channel.ARREADY <= ARREADY @[src/main/scala/bus/AXI4Lite.scala 138:44] + reg RVALID : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 139:23] + io.channels.read_data_channel.RVALID <= RVALID @[src/main/scala/bus/AXI4Lite.scala 140:40] + reg RRESP : UInt<2>, clock with : + reset => (reset, UInt<2>("h0")) @[src/main/scala/bus/AXI4Lite.scala 141:22] + io.channels.read_data_channel.RRESP <= RRESP @[src/main/scala/bus/AXI4Lite.scala 142:39] + io.channels.read_data_channel.RDATA <= io.bundle.read_data @[src/main/scala/bus/AXI4Lite.scala 144:39] + reg AWREADY : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 146:24] + io.channels.write_address_channel.AWREADY <= AWREADY @[src/main/scala/bus/AXI4Lite.scala 147:45] + reg WREADY : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 148:23] + io.channels.write_data_channel.WREADY <= WREADY @[src/main/scala/bus/AXI4Lite.scala 149:41] + write_data <= io.channels.write_data_channel.WDATA @[src/main/scala/bus/AXI4Lite.scala 150:14] + reg BVALID : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 151:23] + io.channels.write_response_channel.BVALID <= BVALID @[src/main/scala/bus/AXI4Lite.scala 152:45] + wire BRESP : UInt<2> @[src/main/scala/bus/AXI4Lite.scala 153:23] + BRESP <= UInt<2>("h0") @[src/main/scala/bus/AXI4Lite.scala 153:23] + io.channels.write_response_channel.BRESP <= BRESP @[src/main/scala/bus/AXI4Lite.scala 154:44] + node _T = asUInt(UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_1 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_2 = eq(_T, _T_1) @[src/main/scala/bus/AXI4Lite.scala 156:17] + when _T_2 : @[src/main/scala/bus/AXI4Lite.scala 156:17] + read <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 158:12] + write <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 159:13] + RVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 160:14] + BVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 161:14] + when io.channels.write_address_channel.AWVALID : @[src/main/scala/bus/AXI4Lite.scala 162:55] + state <= UInt<2>("h3") @[src/main/scala/bus/AXI4Lite.scala 163:15] + else : + when io.channels.read_address_channel.ARVALID : @[src/main/scala/bus/AXI4Lite.scala 164:60] + state <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 165:15] + else : + node _T_3 = asUInt(UInt<1>("h1")) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_4 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_5 = eq(_T_3, _T_4) @[src/main/scala/bus/AXI4Lite.scala 156:17] + when _T_5 : @[src/main/scala/bus/AXI4Lite.scala 156:17] + ARREADY <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 169:15] + node _T_6 = and(io.channels.read_address_channel.ARVALID, ARREADY) @[src/main/scala/bus/AXI4Lite.scala 170:53] + when _T_6 : @[src/main/scala/bus/AXI4Lite.scala 170:65] + state <= UInt<2>("h2") @[src/main/scala/bus/AXI4Lite.scala 171:15] + addr <= io.channels.read_address_channel.ARADDR @[src/main/scala/bus/AXI4Lite.scala 172:14] + read <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 173:14] + ARREADY <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 174:17] + else : + node _T_7 = asUInt(UInt<2>("h2")) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_8 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_9 = eq(_T_7, _T_8) @[src/main/scala/bus/AXI4Lite.scala 156:17] + when _T_9 : @[src/main/scala/bus/AXI4Lite.scala 156:17] + RVALID <= io.bundle.read_valid @[src/main/scala/bus/AXI4Lite.scala 178:14] + node _T_10 = and(io.channels.read_data_channel.RREADY, RVALID) @[src/main/scala/bus/AXI4Lite.scala 179:49] + when _T_10 : @[src/main/scala/bus/AXI4Lite.scala 179:60] + state <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 180:15] + RVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 181:16] + else : + node _T_11 = asUInt(UInt<2>("h3")) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_12 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_13 = eq(_T_11, _T_12) @[src/main/scala/bus/AXI4Lite.scala 156:17] + when _T_13 : @[src/main/scala/bus/AXI4Lite.scala 156:17] + AWREADY <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 185:15] + node _T_14 = and(io.channels.write_address_channel.AWVALID, AWREADY) @[src/main/scala/bus/AXI4Lite.scala 186:54] + when _T_14 : @[src/main/scala/bus/AXI4Lite.scala 186:66] + addr <= io.channels.write_address_channel.AWADDR @[src/main/scala/bus/AXI4Lite.scala 187:14] + state <= UInt<3>("h4") @[src/main/scala/bus/AXI4Lite.scala 188:15] + AWREADY <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 189:17] + else : + node _T_15 = asUInt(UInt<3>("h4")) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_16 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_17 = eq(_T_15, _T_16) @[src/main/scala/bus/AXI4Lite.scala 156:17] + when _T_17 : @[src/main/scala/bus/AXI4Lite.scala 156:17] + WREADY <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 193:14] + node _T_18 = and(io.channels.write_data_channel.WVALID, WREADY) @[src/main/scala/bus/AXI4Lite.scala 194:50] + when _T_18 : @[src/main/scala/bus/AXI4Lite.scala 194:61] + state <= UInt<3>("h5") @[src/main/scala/bus/AXI4Lite.scala 195:15] + write_data <= io.channels.write_data_channel.WDATA @[src/main/scala/bus/AXI4Lite.scala 196:20] + node _T_19 = bits(io.channels.write_data_channel.WSTRB, 0, 0) @[src/main/scala/bus/AXI4Lite.scala 197:62] + node _T_20 = bits(io.channels.write_data_channel.WSTRB, 1, 1) @[src/main/scala/bus/AXI4Lite.scala 197:62] + node _T_21 = bits(io.channels.write_data_channel.WSTRB, 2, 2) @[src/main/scala/bus/AXI4Lite.scala 197:62] + node _T_22 = bits(io.channels.write_data_channel.WSTRB, 3, 3) @[src/main/scala/bus/AXI4Lite.scala 197:62] + write_strobe[0] <= _T_19 @[src/main/scala/bus/AXI4Lite.scala 197:22] + write_strobe[1] <= _T_20 @[src/main/scala/bus/AXI4Lite.scala 197:22] + write_strobe[2] <= _T_21 @[src/main/scala/bus/AXI4Lite.scala 197:22] + write_strobe[3] <= _T_22 @[src/main/scala/bus/AXI4Lite.scala 197:22] + write <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 198:15] + WREADY <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 199:16] + else : + node _T_23 = asUInt(UInt<3>("h5")) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_24 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_25 = eq(_T_23, _T_24) @[src/main/scala/bus/AXI4Lite.scala 156:17] + when _T_25 : @[src/main/scala/bus/AXI4Lite.scala 156:17] + WREADY <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 203:14] + BVALID <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 204:14] + node _T_26 = and(io.channels.write_response_channel.BREADY, BVALID) @[src/main/scala/bus/AXI4Lite.scala 205:54] + when _T_26 : @[src/main/scala/bus/AXI4Lite.scala 205:65] + state <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 206:15] + write <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 207:15] + BVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 208:16] + + + module Memory : + input clock : Clock + input reset : Reset + output io : { flip channels : { write_address_channel : { AWVALID : UInt<1>, flip AWREADY : UInt<1>, AWADDR : UInt<32>, AWPROT : UInt<3>}, write_data_channel : { WVALID : UInt<1>, flip WREADY : UInt<1>, WDATA : UInt<32>, WSTRB : UInt<4>}, write_response_channel : { flip BVALID : UInt<1>, BREADY : UInt<1>, flip BRESP : UInt<2>}, read_address_channel : { ARVALID : UInt<1>, flip ARREADY : UInt<1>, ARADDR : UInt<32>, ARPROT : UInt<3>}, read_data_channel : { flip RVALID : UInt<1>, RREADY : UInt<1>, flip RDATA : UInt<32>, flip RRESP : UInt<2>}}, flip debug_read_address : UInt<32>, debug_read_data : UInt<32>} @[src/main/scala/peripheral/Memory.scala 50:14] + + inst mem of BlockRAM @[src/main/scala/peripheral/Memory.scala 57:19] + mem.clock <= clock + mem.reset <= reset + inst slave of AXI4LiteSlave_1 @[src/main/scala/peripheral/Memory.scala 58:21] + slave.clock <= clock + slave.reset <= reset + slave.io.channels <= io.channels @[src/main/scala/peripheral/Memory.scala 59:21] + slave.io.bundle.read_valid <= UInt<1>("h1") @[src/main/scala/peripheral/Memory.scala 60:30] + mem.io.write_enable <= slave.io.bundle.write @[src/main/scala/peripheral/Memory.scala 62:23] + mem.io.write_data <= slave.io.bundle.write_data @[src/main/scala/peripheral/Memory.scala 63:21] + mem.io.write_address <= slave.io.bundle.address @[src/main/scala/peripheral/Memory.scala 64:24] + mem.io.write_strobe[0] <= slave.io.bundle.write_strobe[0] @[src/main/scala/peripheral/Memory.scala 65:23] + mem.io.write_strobe[1] <= slave.io.bundle.write_strobe[1] @[src/main/scala/peripheral/Memory.scala 65:23] + mem.io.write_strobe[2] <= slave.io.bundle.write_strobe[2] @[src/main/scala/peripheral/Memory.scala 65:23] + mem.io.write_strobe[3] <= slave.io.bundle.write_strobe[3] @[src/main/scala/peripheral/Memory.scala 65:23] + mem.io.read_address <= slave.io.bundle.address @[src/main/scala/peripheral/Memory.scala 67:23] + slave.io.bundle.read_data <= mem.io.read_data @[src/main/scala/peripheral/Memory.scala 68:29] + mem.io.debug_read_address <= io.debug_read_address @[src/main/scala/peripheral/Memory.scala 70:29] + io.debug_read_data <= mem.io.debug_read_data @[src/main/scala/peripheral/Memory.scala 71:22] + + module AXI4LiteSlave_2 : + input clock : Clock + input reset : Reset + output io : { flip channels : { write_address_channel : { AWVALID : UInt<1>, flip AWREADY : UInt<1>, AWADDR : UInt<8>, AWPROT : UInt<3>}, write_data_channel : { WVALID : UInt<1>, flip WREADY : UInt<1>, WDATA : UInt<32>, WSTRB : UInt<4>}, write_response_channel : { flip BVALID : UInt<1>, BREADY : UInt<1>, flip BRESP : UInt<2>}, read_address_channel : { ARVALID : UInt<1>, flip ARREADY : UInt<1>, ARADDR : UInt<8>, ARPROT : UInt<3>}, read_data_channel : { flip RVALID : UInt<1>, RREADY : UInt<1>, flip RDATA : UInt<32>, flip RRESP : UInt<2>}}, bundle : { read : UInt<1>, write : UInt<1>, flip read_data : UInt<32>, flip read_valid : UInt<1>, write_data : UInt<32>, write_strobe : UInt<1>[4], address : UInt<8>}} @[src/main/scala/bus/AXI4Lite.scala 121:14] + + reg state : UInt<3>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 125:22] + reg addr : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[src/main/scala/bus/AXI4Lite.scala 126:21] + io.bundle.address <= addr @[src/main/scala/bus/AXI4Lite.scala 127:21] + reg read : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 128:21] + io.bundle.read <= read @[src/main/scala/bus/AXI4Lite.scala 129:18] + reg write : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 130:22] + io.bundle.write <= write @[src/main/scala/bus/AXI4Lite.scala 131:19] + reg write_data : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[src/main/scala/bus/AXI4Lite.scala 132:27] + io.bundle.write_data <= write_data @[src/main/scala/bus/AXI4Lite.scala 133:24] + wire _write_strobe_WIRE : UInt<1>[4] @[src/main/scala/bus/AXI4Lite.scala 134:37] + _write_strobe_WIRE[0] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 134:37] + _write_strobe_WIRE[1] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 134:37] + _write_strobe_WIRE[2] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 134:37] + _write_strobe_WIRE[3] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 134:37] + reg write_strobe : UInt<1>[4], clock with : + reset => (reset, _write_strobe_WIRE) @[src/main/scala/bus/AXI4Lite.scala 134:29] + io.bundle.write_strobe <= write_strobe @[src/main/scala/bus/AXI4Lite.scala 135:26] + reg ARREADY : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 137:24] + io.channels.read_address_channel.ARREADY <= ARREADY @[src/main/scala/bus/AXI4Lite.scala 138:44] + reg RVALID : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 139:23] + io.channels.read_data_channel.RVALID <= RVALID @[src/main/scala/bus/AXI4Lite.scala 140:40] + reg RRESP : UInt<2>, clock with : + reset => (reset, UInt<2>("h0")) @[src/main/scala/bus/AXI4Lite.scala 141:22] + io.channels.read_data_channel.RRESP <= RRESP @[src/main/scala/bus/AXI4Lite.scala 142:39] + io.channels.read_data_channel.RDATA <= io.bundle.read_data @[src/main/scala/bus/AXI4Lite.scala 144:39] + reg AWREADY : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 146:24] + io.channels.write_address_channel.AWREADY <= AWREADY @[src/main/scala/bus/AXI4Lite.scala 147:45] + reg WREADY : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 148:23] + io.channels.write_data_channel.WREADY <= WREADY @[src/main/scala/bus/AXI4Lite.scala 149:41] + write_data <= io.channels.write_data_channel.WDATA @[src/main/scala/bus/AXI4Lite.scala 150:14] + reg BVALID : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 151:23] + io.channels.write_response_channel.BVALID <= BVALID @[src/main/scala/bus/AXI4Lite.scala 152:45] + wire BRESP : UInt<2> @[src/main/scala/bus/AXI4Lite.scala 153:23] + BRESP <= UInt<2>("h0") @[src/main/scala/bus/AXI4Lite.scala 153:23] + io.channels.write_response_channel.BRESP <= BRESP @[src/main/scala/bus/AXI4Lite.scala 154:44] + node _T = asUInt(UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_1 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_2 = eq(_T, _T_1) @[src/main/scala/bus/AXI4Lite.scala 156:17] + when _T_2 : @[src/main/scala/bus/AXI4Lite.scala 156:17] + read <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 158:12] + write <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 159:13] + RVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 160:14] + BVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 161:14] + when io.channels.write_address_channel.AWVALID : @[src/main/scala/bus/AXI4Lite.scala 162:55] + state <= UInt<2>("h3") @[src/main/scala/bus/AXI4Lite.scala 163:15] + else : + when io.channels.read_address_channel.ARVALID : @[src/main/scala/bus/AXI4Lite.scala 164:60] + state <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 165:15] + else : + node _T_3 = asUInt(UInt<1>("h1")) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_4 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_5 = eq(_T_3, _T_4) @[src/main/scala/bus/AXI4Lite.scala 156:17] + when _T_5 : @[src/main/scala/bus/AXI4Lite.scala 156:17] + ARREADY <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 169:15] + node _T_6 = and(io.channels.read_address_channel.ARVALID, ARREADY) @[src/main/scala/bus/AXI4Lite.scala 170:53] + when _T_6 : @[src/main/scala/bus/AXI4Lite.scala 170:65] + state <= UInt<2>("h2") @[src/main/scala/bus/AXI4Lite.scala 171:15] + addr <= io.channels.read_address_channel.ARADDR @[src/main/scala/bus/AXI4Lite.scala 172:14] + read <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 173:14] + ARREADY <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 174:17] + else : + node _T_7 = asUInt(UInt<2>("h2")) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_8 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_9 = eq(_T_7, _T_8) @[src/main/scala/bus/AXI4Lite.scala 156:17] + when _T_9 : @[src/main/scala/bus/AXI4Lite.scala 156:17] + RVALID <= io.bundle.read_valid @[src/main/scala/bus/AXI4Lite.scala 178:14] + node _T_10 = and(io.channels.read_data_channel.RREADY, RVALID) @[src/main/scala/bus/AXI4Lite.scala 179:49] + when _T_10 : @[src/main/scala/bus/AXI4Lite.scala 179:60] + state <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 180:15] + RVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 181:16] + else : + node _T_11 = asUInt(UInt<2>("h3")) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_12 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_13 = eq(_T_11, _T_12) @[src/main/scala/bus/AXI4Lite.scala 156:17] + when _T_13 : @[src/main/scala/bus/AXI4Lite.scala 156:17] + AWREADY <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 185:15] + node _T_14 = and(io.channels.write_address_channel.AWVALID, AWREADY) @[src/main/scala/bus/AXI4Lite.scala 186:54] + when _T_14 : @[src/main/scala/bus/AXI4Lite.scala 186:66] + addr <= io.channels.write_address_channel.AWADDR @[src/main/scala/bus/AXI4Lite.scala 187:14] + state <= UInt<3>("h4") @[src/main/scala/bus/AXI4Lite.scala 188:15] + AWREADY <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 189:17] + else : + node _T_15 = asUInt(UInt<3>("h4")) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_16 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_17 = eq(_T_15, _T_16) @[src/main/scala/bus/AXI4Lite.scala 156:17] + when _T_17 : @[src/main/scala/bus/AXI4Lite.scala 156:17] + WREADY <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 193:14] + node _T_18 = and(io.channels.write_data_channel.WVALID, WREADY) @[src/main/scala/bus/AXI4Lite.scala 194:50] + when _T_18 : @[src/main/scala/bus/AXI4Lite.scala 194:61] + state <= UInt<3>("h5") @[src/main/scala/bus/AXI4Lite.scala 195:15] + write_data <= io.channels.write_data_channel.WDATA @[src/main/scala/bus/AXI4Lite.scala 196:20] + node _T_19 = bits(io.channels.write_data_channel.WSTRB, 0, 0) @[src/main/scala/bus/AXI4Lite.scala 197:62] + node _T_20 = bits(io.channels.write_data_channel.WSTRB, 1, 1) @[src/main/scala/bus/AXI4Lite.scala 197:62] + node _T_21 = bits(io.channels.write_data_channel.WSTRB, 2, 2) @[src/main/scala/bus/AXI4Lite.scala 197:62] + node _T_22 = bits(io.channels.write_data_channel.WSTRB, 3, 3) @[src/main/scala/bus/AXI4Lite.scala 197:62] + write_strobe[0] <= _T_19 @[src/main/scala/bus/AXI4Lite.scala 197:22] + write_strobe[1] <= _T_20 @[src/main/scala/bus/AXI4Lite.scala 197:22] + write_strobe[2] <= _T_21 @[src/main/scala/bus/AXI4Lite.scala 197:22] + write_strobe[3] <= _T_22 @[src/main/scala/bus/AXI4Lite.scala 197:22] + write <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 198:15] + WREADY <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 199:16] + else : + node _T_23 = asUInt(UInt<3>("h5")) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_24 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_25 = eq(_T_23, _T_24) @[src/main/scala/bus/AXI4Lite.scala 156:17] + when _T_25 : @[src/main/scala/bus/AXI4Lite.scala 156:17] + WREADY <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 203:14] + BVALID <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 204:14] + node _T_26 = and(io.channels.write_response_channel.BREADY, BVALID) @[src/main/scala/bus/AXI4Lite.scala 205:54] + when _T_26 : @[src/main/scala/bus/AXI4Lite.scala 205:65] + state <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 206:15] + write <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 207:15] + BVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 208:16] + + + module Timer : + input clock : Clock + input reset : Reset + output io : { flip channels : { write_address_channel : { AWVALID : UInt<1>, flip AWREADY : UInt<1>, AWADDR : UInt<8>, AWPROT : UInt<3>}, write_data_channel : { WVALID : UInt<1>, flip WREADY : UInt<1>, WDATA : UInt<32>, WSTRB : UInt<4>}, write_response_channel : { flip BVALID : UInt<1>, BREADY : UInt<1>, flip BRESP : UInt<2>}, read_address_channel : { ARVALID : UInt<1>, flip ARREADY : UInt<1>, ARADDR : UInt<8>, ARPROT : UInt<3>}, read_data_channel : { flip RVALID : UInt<1>, RREADY : UInt<1>, flip RDATA : UInt<32>, flip RRESP : UInt<2>}}, signal_interrupt : UInt<1>, debug_limit : UInt<32>, debug_enabled : UInt<1>} @[src/main/scala/peripheral/Timer.scala 23:14] + + inst slave of AXI4LiteSlave_2 @[src/main/scala/peripheral/Timer.scala 30:21] + slave.clock <= clock + slave.reset <= reset + slave.io.channels <= io.channels @[src/main/scala/peripheral/Timer.scala 31:21] + reg count : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[src/main/scala/peripheral/Timer.scala 33:22] + reg limit : UInt<32>, clock with : + reset => (reset, UInt<32>("h5f5e100")) @[src/main/scala/peripheral/Timer.scala 34:22] + io.debug_limit <= limit @[src/main/scala/peripheral/Timer.scala 35:18] + reg enabled : UInt<1>, clock with : + reset => (reset, UInt<1>("h1")) @[src/main/scala/peripheral/Timer.scala 36:24] + io.debug_enabled <= enabled @[src/main/scala/peripheral/Timer.scala 37:20] + slave.io.bundle.read_data <= UInt<1>("h0") @[src/main/scala/peripheral/Timer.scala 39:29] + slave.io.bundle.read_valid <= UInt<1>("h1") @[src/main/scala/peripheral/Timer.scala 40:30] + when slave.io.bundle.read : @[src/main/scala/peripheral/Timer.scala 41:30] + node _slave_io_bundle_read_data_T = eq(UInt<3>("h4"), slave.io.bundle.address) @[src/main/scala/peripheral/Timer.scala 42:73] + node _slave_io_bundle_read_data_T_1 = mux(_slave_io_bundle_read_data_T, limit, UInt<1>("h0")) @[src/main/scala/peripheral/Timer.scala 42:73] + node _slave_io_bundle_read_data_T_2 = eq(UInt<4>("h8"), slave.io.bundle.address) @[src/main/scala/peripheral/Timer.scala 42:73] + node _slave_io_bundle_read_data_T_3 = mux(_slave_io_bundle_read_data_T_2, enabled, _slave_io_bundle_read_data_T_1) @[src/main/scala/peripheral/Timer.scala 42:73] + slave.io.bundle.read_data <= _slave_io_bundle_read_data_T_3 @[src/main/scala/peripheral/Timer.scala 42:31] + when slave.io.bundle.write : @[src/main/scala/peripheral/Timer.scala 49:31] + node _T = eq(slave.io.bundle.address, UInt<3>("h4")) @[src/main/scala/peripheral/Timer.scala 50:34] + when _T : @[src/main/scala/peripheral/Timer.scala 50:45] + limit <= slave.io.bundle.write_data @[src/main/scala/peripheral/Timer.scala 51:13] + count <= UInt<1>("h0") @[src/main/scala/peripheral/Timer.scala 52:13] + else : + node _T_1 = eq(slave.io.bundle.address, UInt<4>("h8")) @[src/main/scala/peripheral/Timer.scala 53:40] + when _T_1 : @[src/main/scala/peripheral/Timer.scala 53:51] + node _enabled_T = neq(slave.io.bundle.write_data, UInt<1>("h0")) @[src/main/scala/peripheral/Timer.scala 54:45] + enabled <= _enabled_T @[src/main/scala/peripheral/Timer.scala 54:15] + node _io_signal_interrupt_T = sub(limit, UInt<4>("ha")) @[src/main/scala/peripheral/Timer.scala 58:54] + node _io_signal_interrupt_T_1 = tail(_io_signal_interrupt_T, 1) @[src/main/scala/peripheral/Timer.scala 58:54] + node _io_signal_interrupt_T_2 = geq(count, _io_signal_interrupt_T_1) @[src/main/scala/peripheral/Timer.scala 58:44] + node _io_signal_interrupt_T_3 = and(enabled, _io_signal_interrupt_T_2) @[src/main/scala/peripheral/Timer.scala 58:34] + io.signal_interrupt <= _io_signal_interrupt_T_3 @[src/main/scala/peripheral/Timer.scala 58:23] + node _T_2 = geq(count, limit) @[src/main/scala/peripheral/Timer.scala 60:14] + when _T_2 : @[src/main/scala/peripheral/Timer.scala 60:24] + count <= UInt<1>("h0") @[src/main/scala/peripheral/Timer.scala 61:11] + else : + node _count_T = add(count, UInt<1>("h1")) @[src/main/scala/peripheral/Timer.scala 63:20] + node _count_T_1 = tail(_count_T, 1) @[src/main/scala/peripheral/Timer.scala 63:20] + count <= _count_T_1 @[src/main/scala/peripheral/Timer.scala 63:11] + + + module AXI4LiteSlave_3 : + input clock : Clock + input reset : Reset + output io : { flip channels : { write_address_channel : { AWVALID : UInt<1>, flip AWREADY : UInt<1>, AWADDR : UInt<32>, AWPROT : UInt<3>}, write_data_channel : { WVALID : UInt<1>, flip WREADY : UInt<1>, WDATA : UInt<32>, WSTRB : UInt<4>}, write_response_channel : { flip BVALID : UInt<1>, BREADY : UInt<1>, flip BRESP : UInt<2>}, read_address_channel : { ARVALID : UInt<1>, flip ARREADY : UInt<1>, ARADDR : UInt<32>, ARPROT : UInt<3>}, read_data_channel : { flip RVALID : UInt<1>, RREADY : UInt<1>, flip RDATA : UInt<32>, flip RRESP : UInt<2>}}, bundle : { read : UInt<1>, write : UInt<1>, flip read_data : UInt<32>, flip read_valid : UInt<1>, write_data : UInt<32>, write_strobe : UInt<1>[4], address : UInt<32>}} @[src/main/scala/bus/AXI4Lite.scala 121:14] + + reg state : UInt<3>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 125:22] + reg addr : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[src/main/scala/bus/AXI4Lite.scala 126:21] + io.bundle.address <= addr @[src/main/scala/bus/AXI4Lite.scala 127:21] + reg read : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 128:21] + io.bundle.read <= read @[src/main/scala/bus/AXI4Lite.scala 129:18] + reg write : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 130:22] + io.bundle.write <= write @[src/main/scala/bus/AXI4Lite.scala 131:19] + reg write_data : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[src/main/scala/bus/AXI4Lite.scala 132:27] + io.bundle.write_data <= write_data @[src/main/scala/bus/AXI4Lite.scala 133:24] + wire _write_strobe_WIRE : UInt<1>[4] @[src/main/scala/bus/AXI4Lite.scala 134:37] + _write_strobe_WIRE[0] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 134:37] + _write_strobe_WIRE[1] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 134:37] + _write_strobe_WIRE[2] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 134:37] + _write_strobe_WIRE[3] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 134:37] + reg write_strobe : UInt<1>[4], clock with : + reset => (reset, _write_strobe_WIRE) @[src/main/scala/bus/AXI4Lite.scala 134:29] + io.bundle.write_strobe <= write_strobe @[src/main/scala/bus/AXI4Lite.scala 135:26] + reg ARREADY : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 137:24] + io.channels.read_address_channel.ARREADY <= ARREADY @[src/main/scala/bus/AXI4Lite.scala 138:44] + reg RVALID : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 139:23] + io.channels.read_data_channel.RVALID <= RVALID @[src/main/scala/bus/AXI4Lite.scala 140:40] + reg RRESP : UInt<2>, clock with : + reset => (reset, UInt<2>("h0")) @[src/main/scala/bus/AXI4Lite.scala 141:22] + io.channels.read_data_channel.RRESP <= RRESP @[src/main/scala/bus/AXI4Lite.scala 142:39] + io.channels.read_data_channel.RDATA <= io.bundle.read_data @[src/main/scala/bus/AXI4Lite.scala 144:39] + reg AWREADY : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 146:24] + io.channels.write_address_channel.AWREADY <= AWREADY @[src/main/scala/bus/AXI4Lite.scala 147:45] + reg WREADY : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 148:23] + io.channels.write_data_channel.WREADY <= WREADY @[src/main/scala/bus/AXI4Lite.scala 149:41] + write_data <= io.channels.write_data_channel.WDATA @[src/main/scala/bus/AXI4Lite.scala 150:14] + reg BVALID : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 151:23] + io.channels.write_response_channel.BVALID <= BVALID @[src/main/scala/bus/AXI4Lite.scala 152:45] + wire BRESP : UInt<2> @[src/main/scala/bus/AXI4Lite.scala 153:23] + BRESP <= UInt<2>("h0") @[src/main/scala/bus/AXI4Lite.scala 153:23] + io.channels.write_response_channel.BRESP <= BRESP @[src/main/scala/bus/AXI4Lite.scala 154:44] + node _T = asUInt(UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_1 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_2 = eq(_T, _T_1) @[src/main/scala/bus/AXI4Lite.scala 156:17] + when _T_2 : @[src/main/scala/bus/AXI4Lite.scala 156:17] + read <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 158:12] + write <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 159:13] + RVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 160:14] + BVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 161:14] + when io.channels.write_address_channel.AWVALID : @[src/main/scala/bus/AXI4Lite.scala 162:55] + state <= UInt<2>("h3") @[src/main/scala/bus/AXI4Lite.scala 163:15] + else : + when io.channels.read_address_channel.ARVALID : @[src/main/scala/bus/AXI4Lite.scala 164:60] + state <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 165:15] + else : + node _T_3 = asUInt(UInt<1>("h1")) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_4 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_5 = eq(_T_3, _T_4) @[src/main/scala/bus/AXI4Lite.scala 156:17] + when _T_5 : @[src/main/scala/bus/AXI4Lite.scala 156:17] + ARREADY <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 169:15] + node _T_6 = and(io.channels.read_address_channel.ARVALID, ARREADY) @[src/main/scala/bus/AXI4Lite.scala 170:53] + when _T_6 : @[src/main/scala/bus/AXI4Lite.scala 170:65] + state <= UInt<2>("h2") @[src/main/scala/bus/AXI4Lite.scala 171:15] + addr <= io.channels.read_address_channel.ARADDR @[src/main/scala/bus/AXI4Lite.scala 172:14] + read <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 173:14] + ARREADY <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 174:17] + else : + node _T_7 = asUInt(UInt<2>("h2")) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_8 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_9 = eq(_T_7, _T_8) @[src/main/scala/bus/AXI4Lite.scala 156:17] + when _T_9 : @[src/main/scala/bus/AXI4Lite.scala 156:17] + RVALID <= io.bundle.read_valid @[src/main/scala/bus/AXI4Lite.scala 178:14] + node _T_10 = and(io.channels.read_data_channel.RREADY, RVALID) @[src/main/scala/bus/AXI4Lite.scala 179:49] + when _T_10 : @[src/main/scala/bus/AXI4Lite.scala 179:60] + state <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 180:15] + RVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 181:16] + else : + node _T_11 = asUInt(UInt<2>("h3")) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_12 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_13 = eq(_T_11, _T_12) @[src/main/scala/bus/AXI4Lite.scala 156:17] + when _T_13 : @[src/main/scala/bus/AXI4Lite.scala 156:17] + AWREADY <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 185:15] + node _T_14 = and(io.channels.write_address_channel.AWVALID, AWREADY) @[src/main/scala/bus/AXI4Lite.scala 186:54] + when _T_14 : @[src/main/scala/bus/AXI4Lite.scala 186:66] + addr <= io.channels.write_address_channel.AWADDR @[src/main/scala/bus/AXI4Lite.scala 187:14] + state <= UInt<3>("h4") @[src/main/scala/bus/AXI4Lite.scala 188:15] + AWREADY <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 189:17] + else : + node _T_15 = asUInt(UInt<3>("h4")) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_16 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_17 = eq(_T_15, _T_16) @[src/main/scala/bus/AXI4Lite.scala 156:17] + when _T_17 : @[src/main/scala/bus/AXI4Lite.scala 156:17] + WREADY <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 193:14] + node _T_18 = and(io.channels.write_data_channel.WVALID, WREADY) @[src/main/scala/bus/AXI4Lite.scala 194:50] + when _T_18 : @[src/main/scala/bus/AXI4Lite.scala 194:61] + state <= UInt<3>("h5") @[src/main/scala/bus/AXI4Lite.scala 195:15] + write_data <= io.channels.write_data_channel.WDATA @[src/main/scala/bus/AXI4Lite.scala 196:20] + node _T_19 = bits(io.channels.write_data_channel.WSTRB, 0, 0) @[src/main/scala/bus/AXI4Lite.scala 197:62] + node _T_20 = bits(io.channels.write_data_channel.WSTRB, 1, 1) @[src/main/scala/bus/AXI4Lite.scala 197:62] + node _T_21 = bits(io.channels.write_data_channel.WSTRB, 2, 2) @[src/main/scala/bus/AXI4Lite.scala 197:62] + node _T_22 = bits(io.channels.write_data_channel.WSTRB, 3, 3) @[src/main/scala/bus/AXI4Lite.scala 197:62] + write_strobe[0] <= _T_19 @[src/main/scala/bus/AXI4Lite.scala 197:22] + write_strobe[1] <= _T_20 @[src/main/scala/bus/AXI4Lite.scala 197:22] + write_strobe[2] <= _T_21 @[src/main/scala/bus/AXI4Lite.scala 197:22] + write_strobe[3] <= _T_22 @[src/main/scala/bus/AXI4Lite.scala 197:22] + write <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 198:15] + WREADY <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 199:16] + else : + node _T_23 = asUInt(UInt<3>("h5")) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_24 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 156:17] + node _T_25 = eq(_T_23, _T_24) @[src/main/scala/bus/AXI4Lite.scala 156:17] + when _T_25 : @[src/main/scala/bus/AXI4Lite.scala 156:17] + WREADY <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 203:14] + BVALID <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 204:14] + node _T_26 = and(io.channels.write_response_channel.BREADY, BVALID) @[src/main/scala/bus/AXI4Lite.scala 205:54] + when _T_26 : @[src/main/scala/bus/AXI4Lite.scala 205:65] + state <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 206:15] + write <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 207:15] + BVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 208:16] + + + module DummySlave : + input clock : Clock + input reset : Reset + output io : { flip channels : { write_address_channel : { AWVALID : UInt<1>, flip AWREADY : UInt<1>, AWADDR : UInt<4>, AWPROT : UInt<3>}, write_data_channel : { WVALID : UInt<1>, flip WREADY : UInt<1>, WDATA : UInt<32>, WSTRB : UInt<4>}, write_response_channel : { flip BVALID : UInt<1>, BREADY : UInt<1>, flip BRESP : UInt<2>}, read_address_channel : { ARVALID : UInt<1>, flip ARREADY : UInt<1>, ARADDR : UInt<4>, ARPROT : UInt<3>}, read_data_channel : { flip RVALID : UInt<1>, RREADY : UInt<1>, flip RDATA : UInt<32>, flip RRESP : UInt<2>}}} @[src/main/scala/peripheral/DummySlave.scala 24:14] + + inst slave of AXI4LiteSlave_3 @[src/main/scala/peripheral/DummySlave.scala 28:21] + slave.clock <= clock + slave.reset <= reset + slave.io.channels <= io.channels @[src/main/scala/peripheral/DummySlave.scala 29:21] + slave.io.bundle.read_valid <= UInt<1>("h1") @[src/main/scala/peripheral/DummySlave.scala 30:30] + slave.io.bundle.read_data <= UInt<32>("hdeadbeef") @[src/main/scala/peripheral/DummySlave.scala 31:29] + + module BusArbiter : + input clock : Clock + input reset : Reset + output io : { flip bus_request : UInt<1>[1], bus_granted : UInt<1>[1], ctrl_stall_flag : UInt<1>} @[src/main/scala/bus/BusArbiter.scala 21:14] + + wire granted : UInt @[src/main/scala/bus/BusArbiter.scala 27:21] + granted <= UInt<1>("h0") @[src/main/scala/bus/BusArbiter.scala 30:11] + when io.bus_request[UInt<1>("h0")] : @[src/main/scala/bus/BusArbiter.scala 32:31] + granted <= UInt<1>("h0") @[src/main/scala/bus/BusArbiter.scala 33:15] + node _io_bus_granted_0_T = eq(UInt<1>("h0"), granted) @[src/main/scala/bus/BusArbiter.scala 37:32] + io.bus_granted[UInt<1>("h0")] <= _io_bus_granted_0_T @[src/main/scala/bus/BusArbiter.scala 37:25] + node _io_ctrl_stall_flag_T = eq(io.bus_granted[UInt<1>("h0")], UInt<1>("h0")) @[src/main/scala/bus/BusArbiter.scala 39:25] + io.ctrl_stall_flag <= _io_ctrl_stall_flag_T @[src/main/scala/bus/BusArbiter.scala 39:22] + + module AXI4LiteMaster_1 : + input clock : Clock + input reset : Reset + output io : { channels : { write_address_channel : { AWVALID : UInt<1>, flip AWREADY : UInt<1>, AWADDR : UInt<32>, AWPROT : UInt<3>}, write_data_channel : { WVALID : UInt<1>, flip WREADY : UInt<1>, WDATA : UInt<32>, WSTRB : UInt<4>}, write_response_channel : { flip BVALID : UInt<1>, BREADY : UInt<1>, flip BRESP : UInt<2>}, read_address_channel : { ARVALID : UInt<1>, flip ARREADY : UInt<1>, ARADDR : UInt<32>, ARPROT : UInt<3>}, read_data_channel : { flip RVALID : UInt<1>, RREADY : UInt<1>, flip RDATA : UInt<32>, flip RRESP : UInt<2>}}, bundle : { flip read : UInt<1>, flip write : UInt<1>, read_data : UInt<32>, flip write_data : UInt<32>, flip write_strobe : UInt<1>[4], flip address : UInt<32>, busy : UInt<1>, read_valid : UInt<1>, write_valid : UInt<1>}} @[src/main/scala/bus/AXI4Lite.scala 215:14] + + reg state : UInt<3>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 219:22] + node _io_bundle_busy_T = neq(state, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 220:27] + io.bundle.busy <= _io_bundle_busy_T @[src/main/scala/bus/AXI4Lite.scala 220:18] + reg addr : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[src/main/scala/bus/AXI4Lite.scala 222:21] + reg read_valid : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 223:27] + io.bundle.read_valid <= read_valid @[src/main/scala/bus/AXI4Lite.scala 224:24] + reg write_valid : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 225:28] + io.bundle.write_valid <= write_valid @[src/main/scala/bus/AXI4Lite.scala 226:25] + reg write_data : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[src/main/scala/bus/AXI4Lite.scala 227:27] + wire _write_strobe_WIRE : UInt<1>[4] @[src/main/scala/bus/AXI4Lite.scala 228:37] + _write_strobe_WIRE[0] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 228:37] + _write_strobe_WIRE[1] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 228:37] + _write_strobe_WIRE[2] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 228:37] + _write_strobe_WIRE[3] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 228:37] + reg write_strobe : UInt<1>[4], clock with : + reset => (reset, _write_strobe_WIRE) @[src/main/scala/bus/AXI4Lite.scala 228:29] + reg read_data : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[src/main/scala/bus/AXI4Lite.scala 229:26] + io.channels.read_address_channel.ARADDR <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 231:43] + reg ARVALID : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 232:24] + io.channels.read_address_channel.ARVALID <= ARVALID @[src/main/scala/bus/AXI4Lite.scala 233:44] + io.channels.read_address_channel.ARPROT <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 234:43] + reg RREADY : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 235:23] + io.channels.read_data_channel.RREADY <= RREADY @[src/main/scala/bus/AXI4Lite.scala 236:40] + io.bundle.read_data <= io.channels.read_data_channel.RDATA @[src/main/scala/bus/AXI4Lite.scala 238:23] + reg AWVALID : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 239:24] + io.channels.write_address_channel.AWADDR <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 240:44] + io.channels.write_address_channel.AWVALID <= AWVALID @[src/main/scala/bus/AXI4Lite.scala 241:45] + reg WVALID : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 242:23] + io.channels.write_data_channel.WVALID <= WVALID @[src/main/scala/bus/AXI4Lite.scala 243:41] + io.channels.write_data_channel.WDATA <= write_data @[src/main/scala/bus/AXI4Lite.scala 244:40] + io.channels.write_address_channel.AWPROT <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 245:44] + node io_channels_write_data_channel_WSTRB_lo = cat(write_strobe[1], write_strobe[0]) @[src/main/scala/bus/AXI4Lite.scala 246:56] + node io_channels_write_data_channel_WSTRB_hi = cat(write_strobe[3], write_strobe[2]) @[src/main/scala/bus/AXI4Lite.scala 246:56] + node _io_channels_write_data_channel_WSTRB_T = cat(io_channels_write_data_channel_WSTRB_hi, io_channels_write_data_channel_WSTRB_lo) @[src/main/scala/bus/AXI4Lite.scala 246:56] + io.channels.write_data_channel.WSTRB <= _io_channels_write_data_channel_WSTRB_T @[src/main/scala/bus/AXI4Lite.scala 246:40] + reg BREADY : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 247:23] + io.channels.write_response_channel.BREADY <= BREADY @[src/main/scala/bus/AXI4Lite.scala 248:45] + node _T = asUInt(UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_1 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_2 = eq(_T, _T_1) @[src/main/scala/bus/AXI4Lite.scala 250:17] + when _T_2 : @[src/main/scala/bus/AXI4Lite.scala 250:17] + WVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 252:14] + AWVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 253:15] + ARVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 254:15] + RREADY <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 255:14] + read_valid <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 256:18] + write_valid <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 257:19] + when io.bundle.write : @[src/main/scala/bus/AXI4Lite.scala 258:29] + state <= UInt<2>("h3") @[src/main/scala/bus/AXI4Lite.scala 259:15] + addr <= io.bundle.address @[src/main/scala/bus/AXI4Lite.scala 260:14] + write_data <= io.bundle.write_data @[src/main/scala/bus/AXI4Lite.scala 261:20] + write_strobe <= io.bundle.write_strobe @[src/main/scala/bus/AXI4Lite.scala 262:22] + else : + when io.bundle.read : @[src/main/scala/bus/AXI4Lite.scala 263:34] + state <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 264:15] + addr <= io.bundle.address @[src/main/scala/bus/AXI4Lite.scala 265:14] + else : + node _T_3 = asUInt(UInt<1>("h1")) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_4 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_5 = eq(_T_3, _T_4) @[src/main/scala/bus/AXI4Lite.scala 250:17] + when _T_5 : @[src/main/scala/bus/AXI4Lite.scala 250:17] + ARVALID <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 269:15] + io.channels.read_address_channel.ARADDR <= addr @[src/main/scala/bus/AXI4Lite.scala 270:47] + node _T_6 = and(io.channels.read_address_channel.ARREADY, ARVALID) @[src/main/scala/bus/AXI4Lite.scala 271:53] + when _T_6 : @[src/main/scala/bus/AXI4Lite.scala 271:65] + state <= UInt<2>("h2") @[src/main/scala/bus/AXI4Lite.scala 272:15] + io.channels.read_address_channel.ARADDR <= addr @[src/main/scala/bus/AXI4Lite.scala 273:49] + ARVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 274:17] + else : + node _T_7 = asUInt(UInt<2>("h2")) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_8 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_9 = eq(_T_7, _T_8) @[src/main/scala/bus/AXI4Lite.scala 250:17] + when _T_9 : @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_10 = eq(io.channels.read_data_channel.RRESP, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 278:88] + node _T_11 = and(io.channels.read_data_channel.RVALID, _T_10) @[src/main/scala/bus/AXI4Lite.scala 278:49] + when _T_11 : @[src/main/scala/bus/AXI4Lite.scala 278:97] + state <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 279:15] + read_valid <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 280:20] + RREADY <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 281:16] + read_data <= io.channels.read_data_channel.RDATA @[src/main/scala/bus/AXI4Lite.scala 282:19] + else : + node _T_12 = asUInt(UInt<2>("h3")) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_13 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_14 = eq(_T_12, _T_13) @[src/main/scala/bus/AXI4Lite.scala 250:17] + when _T_14 : @[src/main/scala/bus/AXI4Lite.scala 250:17] + AWVALID <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 286:15] + io.channels.write_address_channel.AWADDR <= addr @[src/main/scala/bus/AXI4Lite.scala 287:48] + node _T_15 = and(io.channels.write_address_channel.AWREADY, AWVALID) @[src/main/scala/bus/AXI4Lite.scala 288:54] + when _T_15 : @[src/main/scala/bus/AXI4Lite.scala 288:66] + state <= UInt<3>("h4") @[src/main/scala/bus/AXI4Lite.scala 289:15] + io.channels.write_address_channel.AWADDR <= addr @[src/main/scala/bus/AXI4Lite.scala 290:50] + AWVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 291:17] + else : + node _T_16 = asUInt(UInt<3>("h4")) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_17 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_18 = eq(_T_16, _T_17) @[src/main/scala/bus/AXI4Lite.scala 250:17] + when _T_18 : @[src/main/scala/bus/AXI4Lite.scala 250:17] + WVALID <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 295:14] + io.channels.write_address_channel.AWADDR <= addr @[src/main/scala/bus/AXI4Lite.scala 296:48] + node _T_19 = and(io.channels.write_data_channel.WREADY, WVALID) @[src/main/scala/bus/AXI4Lite.scala 297:50] + when _T_19 : @[src/main/scala/bus/AXI4Lite.scala 297:61] + io.channels.write_address_channel.AWADDR <= addr @[src/main/scala/bus/AXI4Lite.scala 298:50] + state <= UInt<3>("h5") @[src/main/scala/bus/AXI4Lite.scala 299:15] + WVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 300:16] + else : + node _T_20 = asUInt(UInt<3>("h5")) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_21 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_22 = eq(_T_20, _T_21) @[src/main/scala/bus/AXI4Lite.scala 250:17] + when _T_22 : @[src/main/scala/bus/AXI4Lite.scala 250:17] + BREADY <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 304:14] + node _T_23 = and(io.channels.write_response_channel.BVALID, BREADY) @[src/main/scala/bus/AXI4Lite.scala 305:54] + when _T_23 : @[src/main/scala/bus/AXI4Lite.scala 305:65] + state <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 306:15] + write_valid <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 307:21] + BREADY <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 308:16] + + + module DummyMaster : + input clock : Clock + input reset : Reset + output io : { channels : { write_address_channel : { AWVALID : UInt<1>, flip AWREADY : UInt<1>, AWADDR : UInt<32>, AWPROT : UInt<3>}, write_data_channel : { WVALID : UInt<1>, flip WREADY : UInt<1>, WDATA : UInt<32>, WSTRB : UInt<4>}, write_response_channel : { flip BVALID : UInt<1>, BREADY : UInt<1>, flip BRESP : UInt<2>}, read_address_channel : { ARVALID : UInt<1>, flip ARREADY : UInt<1>, ARADDR : UInt<32>, ARPROT : UInt<3>}, read_data_channel : { flip RVALID : UInt<1>, RREADY : UInt<1>, flip RDATA : UInt<32>, flip RRESP : UInt<2>}}} @[src/main/scala/peripheral/DummyMaster.scala 23:14] + + inst master of AXI4LiteMaster_1 @[src/main/scala/peripheral/DummyMaster.scala 26:22] + master.clock <= clock + master.reset <= reset + master.io.channels.read_data_channel.RRESP <= io.channels.read_data_channel.RRESP @[src/main/scala/peripheral/DummyMaster.scala 27:22] + master.io.channels.read_data_channel.RDATA <= io.channels.read_data_channel.RDATA @[src/main/scala/peripheral/DummyMaster.scala 27:22] + io.channels.read_data_channel.RREADY <= master.io.channels.read_data_channel.RREADY @[src/main/scala/peripheral/DummyMaster.scala 27:22] + master.io.channels.read_data_channel.RVALID <= io.channels.read_data_channel.RVALID @[src/main/scala/peripheral/DummyMaster.scala 27:22] + io.channels.read_address_channel.ARPROT <= master.io.channels.read_address_channel.ARPROT @[src/main/scala/peripheral/DummyMaster.scala 27:22] + io.channels.read_address_channel.ARADDR <= master.io.channels.read_address_channel.ARADDR @[src/main/scala/peripheral/DummyMaster.scala 27:22] + master.io.channels.read_address_channel.ARREADY <= io.channels.read_address_channel.ARREADY @[src/main/scala/peripheral/DummyMaster.scala 27:22] + io.channels.read_address_channel.ARVALID <= master.io.channels.read_address_channel.ARVALID @[src/main/scala/peripheral/DummyMaster.scala 27:22] + master.io.channels.write_response_channel.BRESP <= io.channels.write_response_channel.BRESP @[src/main/scala/peripheral/DummyMaster.scala 27:22] + io.channels.write_response_channel.BREADY <= master.io.channels.write_response_channel.BREADY @[src/main/scala/peripheral/DummyMaster.scala 27:22] + master.io.channels.write_response_channel.BVALID <= io.channels.write_response_channel.BVALID @[src/main/scala/peripheral/DummyMaster.scala 27:22] + io.channels.write_data_channel.WSTRB <= master.io.channels.write_data_channel.WSTRB @[src/main/scala/peripheral/DummyMaster.scala 27:22] + io.channels.write_data_channel.WDATA <= master.io.channels.write_data_channel.WDATA @[src/main/scala/peripheral/DummyMaster.scala 27:22] + master.io.channels.write_data_channel.WREADY <= io.channels.write_data_channel.WREADY @[src/main/scala/peripheral/DummyMaster.scala 27:22] + io.channels.write_data_channel.WVALID <= master.io.channels.write_data_channel.WVALID @[src/main/scala/peripheral/DummyMaster.scala 27:22] + io.channels.write_address_channel.AWPROT <= master.io.channels.write_address_channel.AWPROT @[src/main/scala/peripheral/DummyMaster.scala 27:22] + io.channels.write_address_channel.AWADDR <= master.io.channels.write_address_channel.AWADDR @[src/main/scala/peripheral/DummyMaster.scala 27:22] + master.io.channels.write_address_channel.AWREADY <= io.channels.write_address_channel.AWREADY @[src/main/scala/peripheral/DummyMaster.scala 27:22] + io.channels.write_address_channel.AWVALID <= master.io.channels.write_address_channel.AWVALID @[src/main/scala/peripheral/DummyMaster.scala 27:22] + wire _WIRE : UInt<1>[4] @[src/main/scala/peripheral/DummyMaster.scala 28:43] + _WIRE[0] <= UInt<1>("h0") @[src/main/scala/peripheral/DummyMaster.scala 28:43] + _WIRE[1] <= UInt<1>("h0") @[src/main/scala/peripheral/DummyMaster.scala 28:43] + _WIRE[2] <= UInt<1>("h0") @[src/main/scala/peripheral/DummyMaster.scala 28:43] + _WIRE[3] <= UInt<1>("h0") @[src/main/scala/peripheral/DummyMaster.scala 28:43] + master.io.bundle.write_strobe[0] <= _WIRE[0] @[src/main/scala/peripheral/DummyMaster.scala 28:33] + master.io.bundle.write_strobe[1] <= _WIRE[1] @[src/main/scala/peripheral/DummyMaster.scala 28:33] + master.io.bundle.write_strobe[2] <= _WIRE[2] @[src/main/scala/peripheral/DummyMaster.scala 28:33] + master.io.bundle.write_strobe[3] <= _WIRE[3] @[src/main/scala/peripheral/DummyMaster.scala 28:33] + master.io.bundle.write_data <= UInt<1>("h0") @[src/main/scala/peripheral/DummyMaster.scala 29:31] + master.io.bundle.write <= UInt<1>("h0") @[src/main/scala/peripheral/DummyMaster.scala 30:26] + master.io.bundle.read <= UInt<1>("h0") @[src/main/scala/peripheral/DummyMaster.scala 31:25] + master.io.bundle.address <= UInt<1>("h0") @[src/main/scala/peripheral/DummyMaster.scala 32:28] + + module BusSwitch : + input clock : Clock + input reset : Reset + output io : { flip address : UInt<32>, slaves : { write_address_channel : { AWVALID : UInt<1>, flip AWREADY : UInt<1>, AWADDR : UInt<32>, AWPROT : UInt<3>}, write_data_channel : { WVALID : UInt<1>, flip WREADY : UInt<1>, WDATA : UInt<32>, WSTRB : UInt<4>}, write_response_channel : { flip BVALID : UInt<1>, BREADY : UInt<1>, flip BRESP : UInt<2>}, read_address_channel : { ARVALID : UInt<1>, flip ARREADY : UInt<1>, ARADDR : UInt<32>, ARPROT : UInt<3>}, read_data_channel : { flip RVALID : UInt<1>, RREADY : UInt<1>, flip RDATA : UInt<32>, flip RRESP : UInt<2>}}[8], flip master : { write_address_channel : { AWVALID : UInt<1>, flip AWREADY : UInt<1>, AWADDR : UInt<32>, AWPROT : UInt<3>}, write_data_channel : { WVALID : UInt<1>, flip WREADY : UInt<1>, WDATA : UInt<32>, WSTRB : UInt<4>}, write_response_channel : { flip BVALID : UInt<1>, BREADY : UInt<1>, flip BRESP : UInt<2>}, read_address_channel : { ARVALID : UInt<1>, flip ARREADY : UInt<1>, ARADDR : UInt<32>, ARPROT : UInt<3>}, read_data_channel : { flip RVALID : UInt<1>, RREADY : UInt<1>, flip RDATA : UInt<32>, flip RRESP : UInt<2>}}} @[src/main/scala/bus/BusSwitch.scala 22:14] + + inst dummy of DummyMaster @[src/main/scala/bus/BusSwitch.scala 27:21] + dummy.clock <= clock + dummy.reset <= reset + node index = bits(io.address, 31, 29) @[src/main/scala/bus/BusSwitch.scala 28:25] + dummy.io.channels.read_data_channel.RRESP <= io.slaves[0].read_data_channel.RRESP @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_data_channel.RDATA <= io.slaves[0].read_data_channel.RDATA @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[0].read_data_channel.RREADY <= dummy.io.channels.read_data_channel.RREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_data_channel.RVALID <= io.slaves[0].read_data_channel.RVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[0].read_address_channel.ARPROT <= dummy.io.channels.read_address_channel.ARPROT @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[0].read_address_channel.ARADDR <= dummy.io.channels.read_address_channel.ARADDR @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_address_channel.ARREADY <= io.slaves[0].read_address_channel.ARREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[0].read_address_channel.ARVALID <= dummy.io.channels.read_address_channel.ARVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_response_channel.BRESP <= io.slaves[0].write_response_channel.BRESP @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[0].write_response_channel.BREADY <= dummy.io.channels.write_response_channel.BREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_response_channel.BVALID <= io.slaves[0].write_response_channel.BVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[0].write_data_channel.WSTRB <= dummy.io.channels.write_data_channel.WSTRB @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[0].write_data_channel.WDATA <= dummy.io.channels.write_data_channel.WDATA @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_data_channel.WREADY <= io.slaves[0].write_data_channel.WREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[0].write_data_channel.WVALID <= dummy.io.channels.write_data_channel.WVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[0].write_address_channel.AWPROT <= dummy.io.channels.write_address_channel.AWPROT @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[0].write_address_channel.AWADDR <= dummy.io.channels.write_address_channel.AWADDR @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_address_channel.AWREADY <= io.slaves[0].write_address_channel.AWREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[0].write_address_channel.AWVALID <= dummy.io.channels.write_address_channel.AWVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_data_channel.RRESP <= io.slaves[1].read_data_channel.RRESP @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_data_channel.RDATA <= io.slaves[1].read_data_channel.RDATA @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[1].read_data_channel.RREADY <= dummy.io.channels.read_data_channel.RREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_data_channel.RVALID <= io.slaves[1].read_data_channel.RVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[1].read_address_channel.ARPROT <= dummy.io.channels.read_address_channel.ARPROT @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[1].read_address_channel.ARADDR <= dummy.io.channels.read_address_channel.ARADDR @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_address_channel.ARREADY <= io.slaves[1].read_address_channel.ARREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[1].read_address_channel.ARVALID <= dummy.io.channels.read_address_channel.ARVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_response_channel.BRESP <= io.slaves[1].write_response_channel.BRESP @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[1].write_response_channel.BREADY <= dummy.io.channels.write_response_channel.BREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_response_channel.BVALID <= io.slaves[1].write_response_channel.BVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[1].write_data_channel.WSTRB <= dummy.io.channels.write_data_channel.WSTRB @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[1].write_data_channel.WDATA <= dummy.io.channels.write_data_channel.WDATA @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_data_channel.WREADY <= io.slaves[1].write_data_channel.WREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[1].write_data_channel.WVALID <= dummy.io.channels.write_data_channel.WVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[1].write_address_channel.AWPROT <= dummy.io.channels.write_address_channel.AWPROT @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[1].write_address_channel.AWADDR <= dummy.io.channels.write_address_channel.AWADDR @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_address_channel.AWREADY <= io.slaves[1].write_address_channel.AWREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[1].write_address_channel.AWVALID <= dummy.io.channels.write_address_channel.AWVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_data_channel.RRESP <= io.slaves[2].read_data_channel.RRESP @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_data_channel.RDATA <= io.slaves[2].read_data_channel.RDATA @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[2].read_data_channel.RREADY <= dummy.io.channels.read_data_channel.RREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_data_channel.RVALID <= io.slaves[2].read_data_channel.RVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[2].read_address_channel.ARPROT <= dummy.io.channels.read_address_channel.ARPROT @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[2].read_address_channel.ARADDR <= dummy.io.channels.read_address_channel.ARADDR @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_address_channel.ARREADY <= io.slaves[2].read_address_channel.ARREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[2].read_address_channel.ARVALID <= dummy.io.channels.read_address_channel.ARVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_response_channel.BRESP <= io.slaves[2].write_response_channel.BRESP @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[2].write_response_channel.BREADY <= dummy.io.channels.write_response_channel.BREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_response_channel.BVALID <= io.slaves[2].write_response_channel.BVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[2].write_data_channel.WSTRB <= dummy.io.channels.write_data_channel.WSTRB @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[2].write_data_channel.WDATA <= dummy.io.channels.write_data_channel.WDATA @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_data_channel.WREADY <= io.slaves[2].write_data_channel.WREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[2].write_data_channel.WVALID <= dummy.io.channels.write_data_channel.WVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[2].write_address_channel.AWPROT <= dummy.io.channels.write_address_channel.AWPROT @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[2].write_address_channel.AWADDR <= dummy.io.channels.write_address_channel.AWADDR @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_address_channel.AWREADY <= io.slaves[2].write_address_channel.AWREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[2].write_address_channel.AWVALID <= dummy.io.channels.write_address_channel.AWVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_data_channel.RRESP <= io.slaves[3].read_data_channel.RRESP @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_data_channel.RDATA <= io.slaves[3].read_data_channel.RDATA @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[3].read_data_channel.RREADY <= dummy.io.channels.read_data_channel.RREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_data_channel.RVALID <= io.slaves[3].read_data_channel.RVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[3].read_address_channel.ARPROT <= dummy.io.channels.read_address_channel.ARPROT @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[3].read_address_channel.ARADDR <= dummy.io.channels.read_address_channel.ARADDR @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_address_channel.ARREADY <= io.slaves[3].read_address_channel.ARREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[3].read_address_channel.ARVALID <= dummy.io.channels.read_address_channel.ARVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_response_channel.BRESP <= io.slaves[3].write_response_channel.BRESP @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[3].write_response_channel.BREADY <= dummy.io.channels.write_response_channel.BREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_response_channel.BVALID <= io.slaves[3].write_response_channel.BVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[3].write_data_channel.WSTRB <= dummy.io.channels.write_data_channel.WSTRB @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[3].write_data_channel.WDATA <= dummy.io.channels.write_data_channel.WDATA @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_data_channel.WREADY <= io.slaves[3].write_data_channel.WREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[3].write_data_channel.WVALID <= dummy.io.channels.write_data_channel.WVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[3].write_address_channel.AWPROT <= dummy.io.channels.write_address_channel.AWPROT @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[3].write_address_channel.AWADDR <= dummy.io.channels.write_address_channel.AWADDR @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_address_channel.AWREADY <= io.slaves[3].write_address_channel.AWREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[3].write_address_channel.AWVALID <= dummy.io.channels.write_address_channel.AWVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_data_channel.RRESP <= io.slaves[4].read_data_channel.RRESP @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_data_channel.RDATA <= io.slaves[4].read_data_channel.RDATA @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[4].read_data_channel.RREADY <= dummy.io.channels.read_data_channel.RREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_data_channel.RVALID <= io.slaves[4].read_data_channel.RVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[4].read_address_channel.ARPROT <= dummy.io.channels.read_address_channel.ARPROT @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[4].read_address_channel.ARADDR <= dummy.io.channels.read_address_channel.ARADDR @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_address_channel.ARREADY <= io.slaves[4].read_address_channel.ARREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[4].read_address_channel.ARVALID <= dummy.io.channels.read_address_channel.ARVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_response_channel.BRESP <= io.slaves[4].write_response_channel.BRESP @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[4].write_response_channel.BREADY <= dummy.io.channels.write_response_channel.BREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_response_channel.BVALID <= io.slaves[4].write_response_channel.BVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[4].write_data_channel.WSTRB <= dummy.io.channels.write_data_channel.WSTRB @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[4].write_data_channel.WDATA <= dummy.io.channels.write_data_channel.WDATA @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_data_channel.WREADY <= io.slaves[4].write_data_channel.WREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[4].write_data_channel.WVALID <= dummy.io.channels.write_data_channel.WVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[4].write_address_channel.AWPROT <= dummy.io.channels.write_address_channel.AWPROT @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[4].write_address_channel.AWADDR <= dummy.io.channels.write_address_channel.AWADDR @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_address_channel.AWREADY <= io.slaves[4].write_address_channel.AWREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[4].write_address_channel.AWVALID <= dummy.io.channels.write_address_channel.AWVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_data_channel.RRESP <= io.slaves[5].read_data_channel.RRESP @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_data_channel.RDATA <= io.slaves[5].read_data_channel.RDATA @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[5].read_data_channel.RREADY <= dummy.io.channels.read_data_channel.RREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_data_channel.RVALID <= io.slaves[5].read_data_channel.RVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[5].read_address_channel.ARPROT <= dummy.io.channels.read_address_channel.ARPROT @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[5].read_address_channel.ARADDR <= dummy.io.channels.read_address_channel.ARADDR @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_address_channel.ARREADY <= io.slaves[5].read_address_channel.ARREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[5].read_address_channel.ARVALID <= dummy.io.channels.read_address_channel.ARVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_response_channel.BRESP <= io.slaves[5].write_response_channel.BRESP @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[5].write_response_channel.BREADY <= dummy.io.channels.write_response_channel.BREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_response_channel.BVALID <= io.slaves[5].write_response_channel.BVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[5].write_data_channel.WSTRB <= dummy.io.channels.write_data_channel.WSTRB @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[5].write_data_channel.WDATA <= dummy.io.channels.write_data_channel.WDATA @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_data_channel.WREADY <= io.slaves[5].write_data_channel.WREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[5].write_data_channel.WVALID <= dummy.io.channels.write_data_channel.WVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[5].write_address_channel.AWPROT <= dummy.io.channels.write_address_channel.AWPROT @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[5].write_address_channel.AWADDR <= dummy.io.channels.write_address_channel.AWADDR @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_address_channel.AWREADY <= io.slaves[5].write_address_channel.AWREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[5].write_address_channel.AWVALID <= dummy.io.channels.write_address_channel.AWVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_data_channel.RRESP <= io.slaves[6].read_data_channel.RRESP @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_data_channel.RDATA <= io.slaves[6].read_data_channel.RDATA @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[6].read_data_channel.RREADY <= dummy.io.channels.read_data_channel.RREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_data_channel.RVALID <= io.slaves[6].read_data_channel.RVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[6].read_address_channel.ARPROT <= dummy.io.channels.read_address_channel.ARPROT @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[6].read_address_channel.ARADDR <= dummy.io.channels.read_address_channel.ARADDR @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_address_channel.ARREADY <= io.slaves[6].read_address_channel.ARREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[6].read_address_channel.ARVALID <= dummy.io.channels.read_address_channel.ARVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_response_channel.BRESP <= io.slaves[6].write_response_channel.BRESP @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[6].write_response_channel.BREADY <= dummy.io.channels.write_response_channel.BREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_response_channel.BVALID <= io.slaves[6].write_response_channel.BVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[6].write_data_channel.WSTRB <= dummy.io.channels.write_data_channel.WSTRB @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[6].write_data_channel.WDATA <= dummy.io.channels.write_data_channel.WDATA @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_data_channel.WREADY <= io.slaves[6].write_data_channel.WREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[6].write_data_channel.WVALID <= dummy.io.channels.write_data_channel.WVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[6].write_address_channel.AWPROT <= dummy.io.channels.write_address_channel.AWPROT @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[6].write_address_channel.AWADDR <= dummy.io.channels.write_address_channel.AWADDR @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_address_channel.AWREADY <= io.slaves[6].write_address_channel.AWREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[6].write_address_channel.AWVALID <= dummy.io.channels.write_address_channel.AWVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_data_channel.RRESP <= io.slaves[7].read_data_channel.RRESP @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_data_channel.RDATA <= io.slaves[7].read_data_channel.RDATA @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[7].read_data_channel.RREADY <= dummy.io.channels.read_data_channel.RREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_data_channel.RVALID <= io.slaves[7].read_data_channel.RVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[7].read_address_channel.ARPROT <= dummy.io.channels.read_address_channel.ARPROT @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[7].read_address_channel.ARADDR <= dummy.io.channels.read_address_channel.ARADDR @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.read_address_channel.ARREADY <= io.slaves[7].read_address_channel.ARREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[7].read_address_channel.ARVALID <= dummy.io.channels.read_address_channel.ARVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_response_channel.BRESP <= io.slaves[7].write_response_channel.BRESP @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[7].write_response_channel.BREADY <= dummy.io.channels.write_response_channel.BREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_response_channel.BVALID <= io.slaves[7].write_response_channel.BVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[7].write_data_channel.WSTRB <= dummy.io.channels.write_data_channel.WSTRB @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[7].write_data_channel.WDATA <= dummy.io.channels.write_data_channel.WDATA @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_data_channel.WREADY <= io.slaves[7].write_data_channel.WREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[7].write_data_channel.WVALID <= dummy.io.channels.write_data_channel.WVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[7].write_address_channel.AWPROT <= dummy.io.channels.write_address_channel.AWPROT @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[7].write_address_channel.AWADDR <= dummy.io.channels.write_address_channel.AWADDR @[src/main/scala/bus/BusSwitch.scala 30:18] + dummy.io.channels.write_address_channel.AWREADY <= io.slaves[7].write_address_channel.AWREADY @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[7].write_address_channel.AWVALID <= dummy.io.channels.write_address_channel.AWVALID @[src/main/scala/bus/BusSwitch.scala 30:18] + io.slaves[index] <= io.master @[src/main/scala/bus/BusSwitch.scala 32:13] + + module InstructionROM : + input clock : Clock + input reset : Reset + output io : { flip address : UInt<32>, data : UInt<32>} @[src/main/scala/peripheral/InstructionROM.scala 28:14] + + smem mem : UInt<32> [1051] @[src/main/scala/peripheral/InstructionROM.scala 34:24] + wire _io_data_WIRE : UInt @[src/main/scala/peripheral/InstructionROM.scala 40:22] + _io_data_WIRE is invalid @[src/main/scala/peripheral/InstructionROM.scala 40:22] + when UInt<1>("h1") : @[src/main/scala/peripheral/InstructionROM.scala 40:22] + _io_data_WIRE <= io.address @[src/main/scala/peripheral/InstructionROM.scala 40:22] + node _io_data_T = or(_io_data_WIRE, UInt<11>("h0")) @[src/main/scala/peripheral/InstructionROM.scala 40:22] + node _io_data_T_1 = bits(_io_data_T, 10, 0) @[src/main/scala/peripheral/InstructionROM.scala 40:22] + read mport io_data_MPORT = mem[_io_data_T_1], clock @[src/main/scala/peripheral/InstructionROM.scala 40:22] + io.data <= io_data_MPORT @[src/main/scala/peripheral/InstructionROM.scala 40:11] + + module AXI4LiteMaster_2 : + input clock : Clock + input reset : Reset + output io : { channels : { write_address_channel : { AWVALID : UInt<1>, flip AWREADY : UInt<1>, AWADDR : UInt<32>, AWPROT : UInt<3>}, write_data_channel : { WVALID : UInt<1>, flip WREADY : UInt<1>, WDATA : UInt<32>, WSTRB : UInt<4>}, write_response_channel : { flip BVALID : UInt<1>, BREADY : UInt<1>, flip BRESP : UInt<2>}, read_address_channel : { ARVALID : UInt<1>, flip ARREADY : UInt<1>, ARADDR : UInt<32>, ARPROT : UInt<3>}, read_data_channel : { flip RVALID : UInt<1>, RREADY : UInt<1>, flip RDATA : UInt<32>, flip RRESP : UInt<2>}}, bundle : { flip read : UInt<1>, flip write : UInt<1>, read_data : UInt<32>, flip write_data : UInt<32>, flip write_strobe : UInt<1>[4], flip address : UInt<32>, busy : UInt<1>, read_valid : UInt<1>, write_valid : UInt<1>}} @[src/main/scala/bus/AXI4Lite.scala 215:14] + + reg state : UInt<3>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 219:22] + node _io_bundle_busy_T = neq(state, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 220:27] + io.bundle.busy <= _io_bundle_busy_T @[src/main/scala/bus/AXI4Lite.scala 220:18] + reg addr : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[src/main/scala/bus/AXI4Lite.scala 222:21] + reg read_valid : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 223:27] + io.bundle.read_valid <= read_valid @[src/main/scala/bus/AXI4Lite.scala 224:24] + reg write_valid : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 225:28] + io.bundle.write_valid <= write_valid @[src/main/scala/bus/AXI4Lite.scala 226:25] + reg write_data : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[src/main/scala/bus/AXI4Lite.scala 227:27] + wire _write_strobe_WIRE : UInt<1>[4] @[src/main/scala/bus/AXI4Lite.scala 228:37] + _write_strobe_WIRE[0] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 228:37] + _write_strobe_WIRE[1] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 228:37] + _write_strobe_WIRE[2] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 228:37] + _write_strobe_WIRE[3] <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 228:37] + reg write_strobe : UInt<1>[4], clock with : + reset => (reset, _write_strobe_WIRE) @[src/main/scala/bus/AXI4Lite.scala 228:29] + reg read_data : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[src/main/scala/bus/AXI4Lite.scala 229:26] + io.channels.read_address_channel.ARADDR <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 231:43] + reg ARVALID : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 232:24] + io.channels.read_address_channel.ARVALID <= ARVALID @[src/main/scala/bus/AXI4Lite.scala 233:44] + io.channels.read_address_channel.ARPROT <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 234:43] + reg RREADY : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 235:23] + io.channels.read_data_channel.RREADY <= RREADY @[src/main/scala/bus/AXI4Lite.scala 236:40] + io.bundle.read_data <= io.channels.read_data_channel.RDATA @[src/main/scala/bus/AXI4Lite.scala 238:23] + reg AWVALID : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 239:24] + io.channels.write_address_channel.AWADDR <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 240:44] + io.channels.write_address_channel.AWVALID <= AWVALID @[src/main/scala/bus/AXI4Lite.scala 241:45] + reg WVALID : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 242:23] + io.channels.write_data_channel.WVALID <= WVALID @[src/main/scala/bus/AXI4Lite.scala 243:41] + io.channels.write_data_channel.WDATA <= write_data @[src/main/scala/bus/AXI4Lite.scala 244:40] + io.channels.write_address_channel.AWPROT <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 245:44] + node io_channels_write_data_channel_WSTRB_lo = cat(write_strobe[1], write_strobe[0]) @[src/main/scala/bus/AXI4Lite.scala 246:56] + node io_channels_write_data_channel_WSTRB_hi = cat(write_strobe[3], write_strobe[2]) @[src/main/scala/bus/AXI4Lite.scala 246:56] + node _io_channels_write_data_channel_WSTRB_T = cat(io_channels_write_data_channel_WSTRB_hi, io_channels_write_data_channel_WSTRB_lo) @[src/main/scala/bus/AXI4Lite.scala 246:56] + io.channels.write_data_channel.WSTRB <= _io_channels_write_data_channel_WSTRB_T @[src/main/scala/bus/AXI4Lite.scala 246:40] + reg BREADY : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 247:23] + io.channels.write_response_channel.BREADY <= BREADY @[src/main/scala/bus/AXI4Lite.scala 248:45] + node _T = asUInt(UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_1 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_2 = eq(_T, _T_1) @[src/main/scala/bus/AXI4Lite.scala 250:17] + when _T_2 : @[src/main/scala/bus/AXI4Lite.scala 250:17] + WVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 252:14] + AWVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 253:15] + ARVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 254:15] + RREADY <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 255:14] + read_valid <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 256:18] + write_valid <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 257:19] + when io.bundle.write : @[src/main/scala/bus/AXI4Lite.scala 258:29] + state <= UInt<2>("h3") @[src/main/scala/bus/AXI4Lite.scala 259:15] + addr <= io.bundle.address @[src/main/scala/bus/AXI4Lite.scala 260:14] + write_data <= io.bundle.write_data @[src/main/scala/bus/AXI4Lite.scala 261:20] + write_strobe <= io.bundle.write_strobe @[src/main/scala/bus/AXI4Lite.scala 262:22] + else : + when io.bundle.read : @[src/main/scala/bus/AXI4Lite.scala 263:34] + state <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 264:15] + addr <= io.bundle.address @[src/main/scala/bus/AXI4Lite.scala 265:14] + else : + node _T_3 = asUInt(UInt<1>("h1")) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_4 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_5 = eq(_T_3, _T_4) @[src/main/scala/bus/AXI4Lite.scala 250:17] + when _T_5 : @[src/main/scala/bus/AXI4Lite.scala 250:17] + ARVALID <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 269:15] + io.channels.read_address_channel.ARADDR <= addr @[src/main/scala/bus/AXI4Lite.scala 270:47] + node _T_6 = and(io.channels.read_address_channel.ARREADY, ARVALID) @[src/main/scala/bus/AXI4Lite.scala 271:53] + when _T_6 : @[src/main/scala/bus/AXI4Lite.scala 271:65] + state <= UInt<2>("h2") @[src/main/scala/bus/AXI4Lite.scala 272:15] + io.channels.read_address_channel.ARADDR <= addr @[src/main/scala/bus/AXI4Lite.scala 273:49] + ARVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 274:17] + else : + node _T_7 = asUInt(UInt<2>("h2")) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_8 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_9 = eq(_T_7, _T_8) @[src/main/scala/bus/AXI4Lite.scala 250:17] + when _T_9 : @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_10 = eq(io.channels.read_data_channel.RRESP, UInt<1>("h0")) @[src/main/scala/bus/AXI4Lite.scala 278:88] + node _T_11 = and(io.channels.read_data_channel.RVALID, _T_10) @[src/main/scala/bus/AXI4Lite.scala 278:49] + when _T_11 : @[src/main/scala/bus/AXI4Lite.scala 278:97] + state <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 279:15] + read_valid <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 280:20] + RREADY <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 281:16] + read_data <= io.channels.read_data_channel.RDATA @[src/main/scala/bus/AXI4Lite.scala 282:19] + else : + node _T_12 = asUInt(UInt<2>("h3")) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_13 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_14 = eq(_T_12, _T_13) @[src/main/scala/bus/AXI4Lite.scala 250:17] + when _T_14 : @[src/main/scala/bus/AXI4Lite.scala 250:17] + AWVALID <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 286:15] + io.channels.write_address_channel.AWADDR <= addr @[src/main/scala/bus/AXI4Lite.scala 287:48] + node _T_15 = and(io.channels.write_address_channel.AWREADY, AWVALID) @[src/main/scala/bus/AXI4Lite.scala 288:54] + when _T_15 : @[src/main/scala/bus/AXI4Lite.scala 288:66] + state <= UInt<3>("h4") @[src/main/scala/bus/AXI4Lite.scala 289:15] + io.channels.write_address_channel.AWADDR <= addr @[src/main/scala/bus/AXI4Lite.scala 290:50] + AWVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 291:17] + else : + node _T_16 = asUInt(UInt<3>("h4")) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_17 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_18 = eq(_T_16, _T_17) @[src/main/scala/bus/AXI4Lite.scala 250:17] + when _T_18 : @[src/main/scala/bus/AXI4Lite.scala 250:17] + WVALID <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 295:14] + io.channels.write_address_channel.AWADDR <= addr @[src/main/scala/bus/AXI4Lite.scala 296:48] + node _T_19 = and(io.channels.write_data_channel.WREADY, WVALID) @[src/main/scala/bus/AXI4Lite.scala 297:50] + when _T_19 : @[src/main/scala/bus/AXI4Lite.scala 297:61] + io.channels.write_address_channel.AWADDR <= addr @[src/main/scala/bus/AXI4Lite.scala 298:50] + state <= UInt<3>("h5") @[src/main/scala/bus/AXI4Lite.scala 299:15] + WVALID <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 300:16] + else : + node _T_20 = asUInt(UInt<3>("h5")) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_21 = asUInt(state) @[src/main/scala/bus/AXI4Lite.scala 250:17] + node _T_22 = eq(_T_20, _T_21) @[src/main/scala/bus/AXI4Lite.scala 250:17] + when _T_22 : @[src/main/scala/bus/AXI4Lite.scala 250:17] + BREADY <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 304:14] + node _T_23 = and(io.channels.write_response_channel.BVALID, BREADY) @[src/main/scala/bus/AXI4Lite.scala 305:54] + when _T_23 : @[src/main/scala/bus/AXI4Lite.scala 305:65] + state <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 306:15] + write_valid <= UInt<1>("h1") @[src/main/scala/bus/AXI4Lite.scala 307:21] + BREADY <= UInt<1>("h0") @[src/main/scala/bus/AXI4Lite.scala 308:16] + + + module ROMLoader : + input clock : Clock + input reset : Reset + output io : { channels : { write_address_channel : { AWVALID : UInt<1>, flip AWREADY : UInt<1>, AWADDR : UInt<32>, AWPROT : UInt<3>}, write_data_channel : { WVALID : UInt<1>, flip WREADY : UInt<1>, WDATA : UInt<32>, WSTRB : UInt<4>}, write_response_channel : { flip BVALID : UInt<1>, BREADY : UInt<1>, flip BRESP : UInt<2>}, read_address_channel : { ARVALID : UInt<1>, flip ARREADY : UInt<1>, ARADDR : UInt<32>, ARPROT : UInt<3>}, read_data_channel : { flip RVALID : UInt<1>, RREADY : UInt<1>, flip RDATA : UInt<32>, flip RRESP : UInt<2>}}, rom_address : UInt<32>, flip rom_data : UInt<32>, flip load_start : UInt<1>, flip load_address : UInt<32>, load_finished : UInt<1>} @[src/main/scala/peripheral/ROMLoader.scala 22:14] + + inst master of AXI4LiteMaster_2 @[src/main/scala/peripheral/ROMLoader.scala 32:22] + master.clock <= clock + master.reset <= reset + master.io.channels.read_data_channel.RRESP <= io.channels.read_data_channel.RRESP @[src/main/scala/peripheral/ROMLoader.scala 33:22] + master.io.channels.read_data_channel.RDATA <= io.channels.read_data_channel.RDATA @[src/main/scala/peripheral/ROMLoader.scala 33:22] + io.channels.read_data_channel.RREADY <= master.io.channels.read_data_channel.RREADY @[src/main/scala/peripheral/ROMLoader.scala 33:22] + master.io.channels.read_data_channel.RVALID <= io.channels.read_data_channel.RVALID @[src/main/scala/peripheral/ROMLoader.scala 33:22] + io.channels.read_address_channel.ARPROT <= master.io.channels.read_address_channel.ARPROT @[src/main/scala/peripheral/ROMLoader.scala 33:22] + io.channels.read_address_channel.ARADDR <= master.io.channels.read_address_channel.ARADDR @[src/main/scala/peripheral/ROMLoader.scala 33:22] + master.io.channels.read_address_channel.ARREADY <= io.channels.read_address_channel.ARREADY @[src/main/scala/peripheral/ROMLoader.scala 33:22] + io.channels.read_address_channel.ARVALID <= master.io.channels.read_address_channel.ARVALID @[src/main/scala/peripheral/ROMLoader.scala 33:22] + master.io.channels.write_response_channel.BRESP <= io.channels.write_response_channel.BRESP @[src/main/scala/peripheral/ROMLoader.scala 33:22] + io.channels.write_response_channel.BREADY <= master.io.channels.write_response_channel.BREADY @[src/main/scala/peripheral/ROMLoader.scala 33:22] + master.io.channels.write_response_channel.BVALID <= io.channels.write_response_channel.BVALID @[src/main/scala/peripheral/ROMLoader.scala 33:22] + io.channels.write_data_channel.WSTRB <= master.io.channels.write_data_channel.WSTRB @[src/main/scala/peripheral/ROMLoader.scala 33:22] + io.channels.write_data_channel.WDATA <= master.io.channels.write_data_channel.WDATA @[src/main/scala/peripheral/ROMLoader.scala 33:22] + master.io.channels.write_data_channel.WREADY <= io.channels.write_data_channel.WREADY @[src/main/scala/peripheral/ROMLoader.scala 33:22] + io.channels.write_data_channel.WVALID <= master.io.channels.write_data_channel.WVALID @[src/main/scala/peripheral/ROMLoader.scala 33:22] + io.channels.write_address_channel.AWPROT <= master.io.channels.write_address_channel.AWPROT @[src/main/scala/peripheral/ROMLoader.scala 33:22] + io.channels.write_address_channel.AWADDR <= master.io.channels.write_address_channel.AWADDR @[src/main/scala/peripheral/ROMLoader.scala 33:22] + master.io.channels.write_address_channel.AWREADY <= io.channels.write_address_channel.AWREADY @[src/main/scala/peripheral/ROMLoader.scala 33:22] + io.channels.write_address_channel.AWVALID <= master.io.channels.write_address_channel.AWVALID @[src/main/scala/peripheral/ROMLoader.scala 33:22] + reg address : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[src/main/scala/peripheral/ROMLoader.scala 35:24] + reg valid : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/peripheral/ROMLoader.scala 36:22] + reg loading : UInt<1>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/peripheral/ROMLoader.scala 37:24] + master.io.bundle.read <= UInt<1>("h0") @[src/main/scala/peripheral/ROMLoader.scala 39:25] + io.load_finished <= UInt<1>("h0") @[src/main/scala/peripheral/ROMLoader.scala 40:20] + when io.load_start : @[src/main/scala/peripheral/ROMLoader.scala 42:23] + valid <= UInt<1>("h0") @[src/main/scala/peripheral/ROMLoader.scala 43:11] + loading <= UInt<1>("h1") @[src/main/scala/peripheral/ROMLoader.scala 44:13] + address <= UInt<1>("h0") @[src/main/scala/peripheral/ROMLoader.scala 45:13] + master.io.bundle.write <= UInt<1>("h0") @[src/main/scala/peripheral/ROMLoader.scala 48:26] + master.io.bundle.write_data <= UInt<1>("h0") @[src/main/scala/peripheral/ROMLoader.scala 49:31] + wire _WIRE : UInt<1>[4] @[src/main/scala/peripheral/ROMLoader.scala 50:43] + _WIRE[0] <= UInt<1>("h0") @[src/main/scala/peripheral/ROMLoader.scala 50:43] + _WIRE[1] <= UInt<1>("h0") @[src/main/scala/peripheral/ROMLoader.scala 50:43] + _WIRE[2] <= UInt<1>("h0") @[src/main/scala/peripheral/ROMLoader.scala 50:43] + _WIRE[3] <= UInt<1>("h0") @[src/main/scala/peripheral/ROMLoader.scala 50:43] + master.io.bundle.write_strobe[0] <= _WIRE[0] @[src/main/scala/peripheral/ROMLoader.scala 50:33] + master.io.bundle.write_strobe[1] <= _WIRE[1] @[src/main/scala/peripheral/ROMLoader.scala 50:33] + master.io.bundle.write_strobe[2] <= _WIRE[2] @[src/main/scala/peripheral/ROMLoader.scala 50:33] + master.io.bundle.write_strobe[3] <= _WIRE[3] @[src/main/scala/peripheral/ROMLoader.scala 50:33] + master.io.bundle.address <= UInt<1>("h0") @[src/main/scala/peripheral/ROMLoader.scala 51:28] + node _T = eq(loading, UInt<1>("h0")) @[src/main/scala/peripheral/ROMLoader.scala 53:8] + node _T_1 = eq(master.io.bundle.busy, UInt<1>("h0")) @[src/main/scala/peripheral/ROMLoader.scala 53:20] + node _T_2 = and(_T, _T_1) @[src/main/scala/peripheral/ROMLoader.scala 53:17] + node _T_3 = geq(address, UInt<11>("h41a")) @[src/main/scala/peripheral/ROMLoader.scala 53:54] + node _T_4 = and(_T_2, _T_3) @[src/main/scala/peripheral/ROMLoader.scala 53:43] + when _T_4 : @[src/main/scala/peripheral/ROMLoader.scala 53:75] + io.load_finished <= UInt<1>("h1") @[src/main/scala/peripheral/ROMLoader.scala 54:22] + when loading : @[src/main/scala/peripheral/ROMLoader.scala 56:17] + valid <= UInt<1>("h1") @[src/main/scala/peripheral/ROMLoader.scala 57:11] + node _T_5 = eq(master.io.bundle.busy, UInt<1>("h0")) @[src/main/scala/peripheral/ROMLoader.scala 58:10] + node _T_6 = eq(master.io.bundle.write_valid, UInt<1>("h0")) @[src/main/scala/peripheral/ROMLoader.scala 58:36] + node _T_7 = and(_T_5, _T_6) @[src/main/scala/peripheral/ROMLoader.scala 58:33] + when _T_7 : @[src/main/scala/peripheral/ROMLoader.scala 58:67] + when valid : @[src/main/scala/peripheral/ROMLoader.scala 59:19] + master.io.bundle.write <= UInt<1>("h1") @[src/main/scala/peripheral/ROMLoader.scala 60:32] + master.io.bundle.write_data <= io.rom_data @[src/main/scala/peripheral/ROMLoader.scala 61:37] + wire _WIRE_1 : UInt<1>[4] @[src/main/scala/peripheral/ROMLoader.scala 62:49] + _WIRE_1[0] <= UInt<1>("h1") @[src/main/scala/peripheral/ROMLoader.scala 62:49] + _WIRE_1[1] <= UInt<1>("h1") @[src/main/scala/peripheral/ROMLoader.scala 62:49] + _WIRE_1[2] <= UInt<1>("h1") @[src/main/scala/peripheral/ROMLoader.scala 62:49] + _WIRE_1[3] <= UInt<1>("h1") @[src/main/scala/peripheral/ROMLoader.scala 62:49] + master.io.bundle.write_strobe[0] <= _WIRE_1[0] @[src/main/scala/peripheral/ROMLoader.scala 62:39] + master.io.bundle.write_strobe[1] <= _WIRE_1[1] @[src/main/scala/peripheral/ROMLoader.scala 62:39] + master.io.bundle.write_strobe[2] <= _WIRE_1[2] @[src/main/scala/peripheral/ROMLoader.scala 62:39] + master.io.bundle.write_strobe[3] <= _WIRE_1[3] @[src/main/scala/peripheral/ROMLoader.scala 62:39] + node _master_io_bundle_address_T = dshl(address, UInt<2>("h2")) @[src/main/scala/peripheral/ROMLoader.scala 63:46] + node _master_io_bundle_address_T_1 = add(_master_io_bundle_address_T, io.load_address) @[src/main/scala/peripheral/ROMLoader.scala 63:61] + node _master_io_bundle_address_T_2 = tail(_master_io_bundle_address_T_1, 1) @[src/main/scala/peripheral/ROMLoader.scala 63:61] + master.io.bundle.address <= _master_io_bundle_address_T_2 @[src/main/scala/peripheral/ROMLoader.scala 63:34] + when master.io.bundle.write_valid : @[src/main/scala/peripheral/ROMLoader.scala 66:40] + node _T_8 = geq(address, UInt<11>("h41a")) @[src/main/scala/peripheral/ROMLoader.scala 67:20] + when _T_8 : @[src/main/scala/peripheral/ROMLoader.scala 67:41] + loading <= UInt<1>("h0") @[src/main/scala/peripheral/ROMLoader.scala 68:17] + else : + loading <= UInt<1>("h1") @[src/main/scala/peripheral/ROMLoader.scala 70:17] + node _address_T = add(address, UInt<1>("h1")) @[src/main/scala/peripheral/ROMLoader.scala 71:28] + node _address_T_1 = tail(_address_T, 1) @[src/main/scala/peripheral/ROMLoader.scala 71:28] + address <= _address_T_1 @[src/main/scala/peripheral/ROMLoader.scala 71:17] + valid <= UInt<1>("h0") @[src/main/scala/peripheral/ROMLoader.scala 72:15] + else : + address <= address @[src/main/scala/peripheral/ROMLoader.scala 75:15] + io.rom_address <= address @[src/main/scala/peripheral/ROMLoader.scala 78:18] + + module Top : + input clock : Clock + input reset : UInt<1> + output io : { led : UInt<1>, tx : UInt<1>, flip rx : UInt<1>} @[src/main/scala/board/z710/z710/Top.scala 26:14] + + reg boot_state : UInt<2>, clock with : + reset => (reset, UInt<1>("h0")) @[src/main/scala/board/z710/z710/Top.scala 37:27] + inst uart of Uart @[src/main/scala/board/z710/z710/Top.scala 39:20] + uart.clock <= clock + uart.reset <= reset + io.tx <= uart.io.txd @[src/main/scala/board/z710/z710/Top.scala 40:9] + uart.io.rxd <= io.rx @[src/main/scala/board/z710/z710/Top.scala 41:15] + inst cpu of CPU_1 @[src/main/scala/board/z710/z710/Top.scala 43:19] + cpu.clock <= clock + cpu.reset <= reset + inst mem of Memory @[src/main/scala/board/z710/z710/Top.scala 44:19] + mem.clock <= clock + mem.reset <= reset + inst timer of Timer @[src/main/scala/board/z710/z710/Top.scala 45:21] + timer.clock <= clock + timer.reset <= reset + inst dummy of DummySlave @[src/main/scala/board/z710/z710/Top.scala 46:21] + dummy.clock <= clock + dummy.reset <= reset + inst bus_arbiter of BusArbiter @[src/main/scala/board/z710/z710/Top.scala 47:27] + bus_arbiter.clock <= clock + bus_arbiter.reset <= reset + inst bus_switch of BusSwitch @[src/main/scala/board/z710/z710/Top.scala 48:26] + bus_switch.clock <= clock + bus_switch.reset <= reset + inst instruction_rom of InstructionROM @[src/main/scala/board/z710/z710/Top.scala 50:31] + instruction_rom.clock <= clock + instruction_rom.reset <= reset + inst rom_loader of ROMLoader @[src/main/scala/board/z710/z710/Top.scala 51:26] + rom_loader.clock <= clock + rom_loader.reset <= reset + bus_arbiter.io.bus_request[0] <= UInt<1>("h1") @[src/main/scala/board/z710/z710/Top.scala 53:33] + bus_switch.io.master <= cpu.io.axi4_channels @[src/main/scala/board/z710/z710/Top.scala 55:24] + bus_switch.io.address <= cpu.io.bus_address @[src/main/scala/board/z710/z710/Top.scala 56:25] + dummy.io.channels <= bus_switch.io.slaves[0] @[src/main/scala/board/z710/z710/Top.scala 58:29] + dummy.io.channels <= bus_switch.io.slaves[1] @[src/main/scala/board/z710/z710/Top.scala 58:29] + dummy.io.channels <= bus_switch.io.slaves[2] @[src/main/scala/board/z710/z710/Top.scala 58:29] + dummy.io.channels <= bus_switch.io.slaves[3] @[src/main/scala/board/z710/z710/Top.scala 58:29] + dummy.io.channels <= bus_switch.io.slaves[4] @[src/main/scala/board/z710/z710/Top.scala 58:29] + dummy.io.channels <= bus_switch.io.slaves[5] @[src/main/scala/board/z710/z710/Top.scala 58:29] + dummy.io.channels <= bus_switch.io.slaves[6] @[src/main/scala/board/z710/z710/Top.scala 58:29] + dummy.io.channels <= bus_switch.io.slaves[7] @[src/main/scala/board/z710/z710/Top.scala 58:29] + rom_loader.io.load_address <= UInt<32>("h1000") @[src/main/scala/board/z710/z710/Top.scala 60:30] + rom_loader.io.load_start <= UInt<1>("h0") @[src/main/scala/board/z710/z710/Top.scala 61:28] + rom_loader.io.rom_data <= instruction_rom.io.data @[src/main/scala/board/z710/z710/Top.scala 62:26] + instruction_rom.io.address <= rom_loader.io.rom_address @[src/main/scala/board/z710/z710/Top.scala 63:30] + cpu.io.stall_flag_bus <= UInt<1>("h1") @[src/main/scala/board/z710/z710/Top.scala 64:25] + cpu.io.instruction_valid <= UInt<1>("h0") @[src/main/scala/board/z710/z710/Top.scala 65:28] + mem.io.channels <= bus_switch.io.slaves[0] @[src/main/scala/board/z710/z710/Top.scala 66:27] + dummy.io.channels <= rom_loader.io.channels @[src/main/scala/board/z710/z710/Top.scala 67:26] + node _T = asUInt(UInt<1>("h0")) @[src/main/scala/board/z710/z710/Top.scala 68:22] + node _T_1 = asUInt(boot_state) @[src/main/scala/board/z710/z710/Top.scala 68:22] + node _T_2 = eq(_T, _T_1) @[src/main/scala/board/z710/z710/Top.scala 68:22] + when _T_2 : @[src/main/scala/board/z710/z710/Top.scala 68:22] + rom_loader.io.load_start <= UInt<1>("h1") @[src/main/scala/board/z710/z710/Top.scala 70:32] + boot_state <= UInt<1>("h1") @[src/main/scala/board/z710/z710/Top.scala 71:18] + mem.io.channels <= rom_loader.io.channels @[src/main/scala/board/z710/z710/Top.scala 72:30] + else : + node _T_3 = asUInt(UInt<1>("h1")) @[src/main/scala/board/z710/z710/Top.scala 68:22] + node _T_4 = asUInt(boot_state) @[src/main/scala/board/z710/z710/Top.scala 68:22] + node _T_5 = eq(_T_3, _T_4) @[src/main/scala/board/z710/z710/Top.scala 68:22] + when _T_5 : @[src/main/scala/board/z710/z710/Top.scala 68:22] + rom_loader.io.load_start <= UInt<1>("h0") @[src/main/scala/board/z710/z710/Top.scala 75:32] + mem.io.channels <= rom_loader.io.channels @[src/main/scala/board/z710/z710/Top.scala 76:30] + when rom_loader.io.load_finished : @[src/main/scala/board/z710/z710/Top.scala 77:41] + boot_state <= UInt<2>("h3") @[src/main/scala/board/z710/z710/Top.scala 78:20] + else : + node _T_6 = asUInt(UInt<2>("h3")) @[src/main/scala/board/z710/z710/Top.scala 68:22] + node _T_7 = asUInt(boot_state) @[src/main/scala/board/z710/z710/Top.scala 68:22] + node _T_8 = eq(_T_6, _T_7) @[src/main/scala/board/z710/z710/Top.scala 68:22] + when _T_8 : @[src/main/scala/board/z710/z710/Top.scala 68:22] + cpu.io.stall_flag_bus <= UInt<1>("h0") @[src/main/scala/board/z710/z710/Top.scala 82:29] + cpu.io.instruction_valid <= UInt<1>("h1") @[src/main/scala/board/z710/z710/Top.scala 83:32] + uart.io.channels <= bus_switch.io.slaves[2] @[src/main/scala/board/z710/z710/Top.scala 87:27] + timer.io.channels <= bus_switch.io.slaves[4] @[src/main/scala/board/z710/z710/Top.scala 88:27] + node _cpu_io_interrupt_flag_T = cat(uart.io.signal_interrupt, timer.io.signal_interrupt) @[src/main/scala/board/z710/z710/Top.scala 90:31] + cpu.io.interrupt_flag <= _cpu_io_interrupt_flag_T @[src/main/scala/board/z710/z710/Top.scala 90:25] + cpu.io.debug_read_address <= UInt<1>("h0") @[src/main/scala/board/z710/z710/Top.scala 92:29] + mem.io.debug_read_address <= UInt<1>("h0") @[src/main/scala/board/z710/z710/Top.scala 93:29] + reg led_count : UInt<32>, clock with : + reset => (reset, UInt<32>("h0")) @[src/main/scala/board/z710/z710/Top.scala 99:26] + node _T_9 = geq(led_count, UInt<27>("h5f5e100")) @[src/main/scala/board/z710/z710/Top.scala 100:19] + when _T_9 : @[src/main/scala/board/z710/z710/Top.scala 100:34] + led_count <= UInt<1>("h0") @[src/main/scala/board/z710/z710/Top.scala 101:15] + else : + node _led_count_T = add(led_count, UInt<1>("h1")) @[src/main/scala/board/z710/z710/Top.scala 103:28] + node _led_count_T_1 = tail(_led_count_T, 1) @[src/main/scala/board/z710/z710/Top.scala 103:28] + led_count <= _led_count_T_1 @[src/main/scala/board/z710/z710/Top.scala 103:15] + node _io_led_T = shr(UInt<27>("h5f5e100"), 1) @[src/main/scala/board/z710/z710/Top.scala 106:39] + node _io_led_T_1 = geq(led_count, _io_led_T) @[src/main/scala/board/z710/z710/Top.scala 106:24] + io.led <= _io_led_T_1 @[src/main/scala/board/z710/z710/Top.scala 106:10] + diff --git a/mini-yatcpu/verilog/z710/Top.v b/mini-yatcpu/verilog/z710/Top.v new file mode 100644 index 0000000..c67cf4b --- /dev/null +++ b/mini-yatcpu/verilog/z710/Top.v @@ -0,0 +1,7795 @@ +module AXI4LiteSlave( + input clock, + input reset, + input io_channels_write_address_channel_AWVALID, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + output io_channels_write_address_channel_AWREADY, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + input [7:0] io_channels_write_address_channel_AWADDR, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + input io_channels_write_data_channel_WVALID, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + output io_channels_write_data_channel_WREADY, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + input [31:0] io_channels_write_data_channel_WDATA, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + output io_channels_write_response_channel_BVALID, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + input io_channels_write_response_channel_BREADY, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + input io_channels_read_address_channel_ARVALID, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + output io_channels_read_address_channel_ARREADY, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + input [7:0] io_channels_read_address_channel_ARADDR, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + output io_channels_read_data_channel_RVALID, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + input io_channels_read_data_channel_RREADY, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + output [31:0] io_channels_read_data_channel_RDATA, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + output io_bundle_read, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + output io_bundle_write, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + input [31:0] io_bundle_read_data, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + output [31:0] io_bundle_write_data, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + output [7:0] io_bundle_address // @[src/main/scala/bus/AXI4Lite.scala 121:14] +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; +`endif // RANDOMIZE_REG_INIT + reg [2:0] state; // @[src/main/scala/bus/AXI4Lite.scala 125:22] + reg [31:0] addr; // @[src/main/scala/bus/AXI4Lite.scala 126:21] + reg read; // @[src/main/scala/bus/AXI4Lite.scala 128:21] + reg write; // @[src/main/scala/bus/AXI4Lite.scala 130:22] + reg [31:0] write_data; // @[src/main/scala/bus/AXI4Lite.scala 132:27] + reg ARREADY; // @[src/main/scala/bus/AXI4Lite.scala 137:24] + reg RVALID; // @[src/main/scala/bus/AXI4Lite.scala 139:23] + reg AWREADY; // @[src/main/scala/bus/AXI4Lite.scala 146:24] + reg WREADY; // @[src/main/scala/bus/AXI4Lite.scala 148:23] + reg BVALID; // @[src/main/scala/bus/AXI4Lite.scala 151:23] + wire _GEN_4 = io_channels_read_address_channel_ARVALID & ARREADY | read; // @[src/main/scala/bus/AXI4Lite.scala 170:65 173:14 128:21] + wire [2:0] _GEN_6 = io_channels_read_data_channel_RREADY & RVALID ? 3'h0 : state; // @[src/main/scala/bus/AXI4Lite.scala 179:60 180:15 125:22] + wire _GEN_7 = io_channels_read_data_channel_RREADY & RVALID ? 1'h0 : 1'h1; // @[src/main/scala/bus/AXI4Lite.scala 178:14 179:60 181:16] + wire [31:0] _GEN_8 = io_channels_write_address_channel_AWVALID & AWREADY ? {{24'd0}, + io_channels_write_address_channel_AWADDR} : addr; // @[src/main/scala/bus/AXI4Lite.scala 186:66 187:14 126:21] + wire [2:0] _GEN_9 = io_channels_write_address_channel_AWVALID & AWREADY ? 3'h4 : state; // @[src/main/scala/bus/AXI4Lite.scala 186:66 188:15 125:22] + wire _GEN_10 = io_channels_write_address_channel_AWVALID & AWREADY ? 1'h0 : 1'h1; // @[src/main/scala/bus/AXI4Lite.scala 185:15 186:66 189:17] + wire [2:0] _GEN_11 = io_channels_write_data_channel_WVALID & WREADY ? 3'h5 : state; // @[src/main/scala/bus/AXI4Lite.scala 194:61 195:15 125:22] + wire _GEN_17 = io_channels_write_data_channel_WVALID & WREADY | write; // @[src/main/scala/bus/AXI4Lite.scala 194:61 198:15 130:22] + wire _GEN_18 = io_channels_write_data_channel_WVALID & WREADY ? 1'h0 : 1'h1; // @[src/main/scala/bus/AXI4Lite.scala 193:14 194:61 199:16] + wire [2:0] _GEN_19 = io_channels_write_response_channel_BREADY & BVALID ? 3'h0 : state; // @[src/main/scala/bus/AXI4Lite.scala 205:65 206:15 125:22] + wire _GEN_20 = io_channels_write_response_channel_BREADY & BVALID ? 1'h0 : write; // @[src/main/scala/bus/AXI4Lite.scala 205:65 207:15 130:22] + wire _GEN_21 = io_channels_write_response_channel_BREADY & BVALID ? 1'h0 : 1'h1; // @[src/main/scala/bus/AXI4Lite.scala 204:14 205:65 208:16] + wire _GEN_22 = 3'h5 == state ? 1'h0 : WREADY; // @[src/main/scala/bus/AXI4Lite.scala 156:17 203:14 148:23] + wire _GEN_23 = 3'h5 == state ? _GEN_21 : BVALID; // @[src/main/scala/bus/AXI4Lite.scala 156:17 151:23] + wire [2:0] _GEN_24 = 3'h5 == state ? _GEN_19 : state; // @[src/main/scala/bus/AXI4Lite.scala 156:17 125:22] + wire _GEN_25 = 3'h5 == state ? _GEN_20 : write; // @[src/main/scala/bus/AXI4Lite.scala 156:17 130:22] + wire _GEN_26 = 3'h4 == state ? _GEN_18 : _GEN_22; // @[src/main/scala/bus/AXI4Lite.scala 156:17] + wire [2:0] _GEN_27 = 3'h4 == state ? _GEN_11 : _GEN_24; // @[src/main/scala/bus/AXI4Lite.scala 156:17] + wire _GEN_33 = 3'h4 == state ? _GEN_17 : _GEN_25; // @[src/main/scala/bus/AXI4Lite.scala 156:17] + wire _GEN_34 = 3'h4 == state ? BVALID : _GEN_23; // @[src/main/scala/bus/AXI4Lite.scala 156:17 151:23] + wire _GEN_35 = 3'h3 == state ? _GEN_10 : AWREADY; // @[src/main/scala/bus/AXI4Lite.scala 156:17 146:24] + wire [31:0] _GEN_36 = 3'h3 == state ? _GEN_8 : addr; // @[src/main/scala/bus/AXI4Lite.scala 156:17 126:21] + wire [2:0] _GEN_37 = 3'h3 == state ? _GEN_9 : _GEN_27; // @[src/main/scala/bus/AXI4Lite.scala 156:17] + wire _GEN_38 = 3'h3 == state ? WREADY : _GEN_26; // @[src/main/scala/bus/AXI4Lite.scala 156:17 148:23] + wire _GEN_44 = 3'h3 == state ? write : _GEN_33; // @[src/main/scala/bus/AXI4Lite.scala 156:17 130:22] + wire _GEN_45 = 3'h3 == state ? BVALID : _GEN_34; // @[src/main/scala/bus/AXI4Lite.scala 156:17 151:23] + assign io_channels_write_address_channel_AWREADY = AWREADY; // @[src/main/scala/bus/AXI4Lite.scala 147:45] + assign io_channels_write_data_channel_WREADY = WREADY; // @[src/main/scala/bus/AXI4Lite.scala 149:41] + assign io_channels_write_response_channel_BVALID = BVALID; // @[src/main/scala/bus/AXI4Lite.scala 152:45] + assign io_channels_read_address_channel_ARREADY = ARREADY; // @[src/main/scala/bus/AXI4Lite.scala 138:44] + assign io_channels_read_data_channel_RVALID = RVALID; // @[src/main/scala/bus/AXI4Lite.scala 140:40] + assign io_channels_read_data_channel_RDATA = io_bundle_read_data; // @[src/main/scala/bus/AXI4Lite.scala 144:39] + assign io_bundle_read = read; // @[src/main/scala/bus/AXI4Lite.scala 129:18] + assign io_bundle_write = write; // @[src/main/scala/bus/AXI4Lite.scala 131:19] + assign io_bundle_write_data = write_data; // @[src/main/scala/bus/AXI4Lite.scala 133:24] + assign io_bundle_address = addr[7:0]; // @[src/main/scala/bus/AXI4Lite.scala 127:21] + always @(posedge clock) begin + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 125:22] + state <= 3'h0; // @[src/main/scala/bus/AXI4Lite.scala 125:22] + end else if (3'h0 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (io_channels_write_address_channel_AWVALID) begin // @[src/main/scala/bus/AXI4Lite.scala 162:55] + state <= 3'h3; // @[src/main/scala/bus/AXI4Lite.scala 163:15] + end else if (io_channels_read_address_channel_ARVALID) begin // @[src/main/scala/bus/AXI4Lite.scala 164:60] + state <= 3'h1; // @[src/main/scala/bus/AXI4Lite.scala 165:15] + end + end else if (3'h1 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (io_channels_read_address_channel_ARVALID & ARREADY) begin // @[src/main/scala/bus/AXI4Lite.scala 170:65] + state <= 3'h2; // @[src/main/scala/bus/AXI4Lite.scala 171:15] + end + end else if (3'h2 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + state <= _GEN_6; + end else begin + state <= _GEN_37; + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 126:21] + addr <= 32'h0; // @[src/main/scala/bus/AXI4Lite.scala 126:21] + end else if (!(3'h0 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (3'h1 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (io_channels_read_address_channel_ARVALID & ARREADY) begin // @[src/main/scala/bus/AXI4Lite.scala 170:65] + addr <= {{24'd0}, io_channels_read_address_channel_ARADDR}; // @[src/main/scala/bus/AXI4Lite.scala 172:14] + end + end else if (!(3'h2 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + addr <= _GEN_36; + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 128:21] + read <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 128:21] + end else if (3'h0 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + read <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 158:12] + end else if (3'h1 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + read <= _GEN_4; + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 130:22] + write <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 130:22] + end else if (3'h0 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + write <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 159:13] + end else if (!(3'h1 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (!(3'h2 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + write <= _GEN_44; + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 132:27] + write_data <= 32'h0; // @[src/main/scala/bus/AXI4Lite.scala 132:27] + end else begin + write_data <= io_channels_write_data_channel_WDATA; + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 137:24] + ARREADY <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 137:24] + end else if (!(3'h0 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (3'h1 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (io_channels_read_address_channel_ARVALID & ARREADY) begin // @[src/main/scala/bus/AXI4Lite.scala 170:65] + ARREADY <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 174:17] + end else begin + ARREADY <= 1'h1; // @[src/main/scala/bus/AXI4Lite.scala 169:15] + end + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 139:23] + RVALID <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 139:23] + end else if (3'h0 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + RVALID <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 160:14] + end else if (!(3'h1 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (3'h2 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + RVALID <= _GEN_7; + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 146:24] + AWREADY <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 146:24] + end else if (!(3'h0 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (!(3'h1 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (!(3'h2 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + AWREADY <= _GEN_35; + end + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 148:23] + WREADY <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 148:23] + end else if (!(3'h0 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (!(3'h1 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (!(3'h2 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + WREADY <= _GEN_38; + end + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 151:23] + BVALID <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 151:23] + end else if (3'h0 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + BVALID <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 161:14] + end else if (!(3'h1 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (!(3'h2 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + BVALID <= _GEN_45; + end + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + state = _RAND_0[2:0]; + _RAND_1 = {1{`RANDOM}}; + addr = _RAND_1[31:0]; + _RAND_2 = {1{`RANDOM}}; + read = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + write = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + write_data = _RAND_4[31:0]; + _RAND_5 = {1{`RANDOM}}; + ARREADY = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + RVALID = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + AWREADY = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + WREADY = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + BVALID = _RAND_9[0:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module Tx( + input clock, + input reset, + output io_txd, // @[src/main/scala/peripheral/UART.scala 32:14] + output io_channel_ready, // @[src/main/scala/peripheral/UART.scala 32:14] + input io_channel_valid, // @[src/main/scala/peripheral/UART.scala 32:14] + input [7:0] io_channel_bits // @[src/main/scala/peripheral/UART.scala 32:14] +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; +`endif // RANDOMIZE_REG_INIT + reg [10:0] shiftReg; // @[src/main/scala/peripheral/UART.scala 40:25] + reg [19:0] cntReg; // @[src/main/scala/peripheral/UART.scala 41:23] + reg [3:0] bitsReg; // @[src/main/scala/peripheral/UART.scala 42:24] + wire _io_channel_ready_T = cntReg == 20'h0; // @[src/main/scala/peripheral/UART.scala 44:31] + wire [9:0] shift = shiftReg[10:1]; // @[src/main/scala/peripheral/UART.scala 51:28] + wire [10:0] _shiftReg_T_1 = {1'h1,shift}; // @[src/main/scala/peripheral/UART.scala 52:22] + wire [3:0] _bitsReg_T_1 = bitsReg - 4'h1; // @[src/main/scala/peripheral/UART.scala 53:26] + wire [10:0] _shiftReg_T_3 = {2'h3,io_channel_bits,1'h0}; // @[src/main/scala/peripheral/UART.scala 56:24] + wire [19:0] _cntReg_T_1 = cntReg - 20'h1; // @[src/main/scala/peripheral/UART.scala 64:22] + assign io_txd = shiftReg[0]; // @[src/main/scala/peripheral/UART.scala 45:21] + assign io_channel_ready = cntReg == 20'h0 & bitsReg == 4'h0; // @[src/main/scala/peripheral/UART.scala 44:40] + always @(posedge clock) begin + if (reset) begin // @[src/main/scala/peripheral/UART.scala 40:25] + shiftReg <= 11'h7ff; // @[src/main/scala/peripheral/UART.scala 40:25] + end else if (_io_channel_ready_T) begin // @[src/main/scala/peripheral/UART.scala 47:24] + if (bitsReg != 4'h0) begin // @[src/main/scala/peripheral/UART.scala 50:27] + shiftReg <= _shiftReg_T_1; // @[src/main/scala/peripheral/UART.scala 52:16] + end else if (io_channel_valid) begin // @[src/main/scala/peripheral/UART.scala 55:30] + shiftReg <= _shiftReg_T_3; // @[src/main/scala/peripheral/UART.scala 56:18] + end else begin + shiftReg <= 11'h7ff; // @[src/main/scala/peripheral/UART.scala 59:18] + end + end + if (reset) begin // @[src/main/scala/peripheral/UART.scala 41:23] + cntReg <= 20'h0; // @[src/main/scala/peripheral/UART.scala 41:23] + end else if (_io_channel_ready_T) begin // @[src/main/scala/peripheral/UART.scala 47:24] + cntReg <= 20'h43c; // @[src/main/scala/peripheral/UART.scala 49:12] + end else begin + cntReg <= _cntReg_T_1; // @[src/main/scala/peripheral/UART.scala 64:12] + end + if (reset) begin // @[src/main/scala/peripheral/UART.scala 42:24] + bitsReg <= 4'h0; // @[src/main/scala/peripheral/UART.scala 42:24] + end else if (_io_channel_ready_T) begin // @[src/main/scala/peripheral/UART.scala 47:24] + if (bitsReg != 4'h0) begin // @[src/main/scala/peripheral/UART.scala 50:27] + bitsReg <= _bitsReg_T_1; // @[src/main/scala/peripheral/UART.scala 53:15] + end else if (io_channel_valid) begin // @[src/main/scala/peripheral/UART.scala 55:30] + bitsReg <= 4'hb; // @[src/main/scala/peripheral/UART.scala 57:17] + end + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + shiftReg = _RAND_0[10:0]; + _RAND_1 = {1{`RANDOM}}; + cntReg = _RAND_1[19:0]; + _RAND_2 = {1{`RANDOM}}; + bitsReg = _RAND_2[3:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module Buffer( + input clock, + input reset, + input io_in_valid, // @[src/main/scala/peripheral/UART.scala 121:14] + input [7:0] io_in_bits, // @[src/main/scala/peripheral/UART.scala 121:14] + input io_out_ready, // @[src/main/scala/peripheral/UART.scala 121:14] + output io_out_valid, // @[src/main/scala/peripheral/UART.scala 121:14] + output [7:0] io_out_bits // @[src/main/scala/peripheral/UART.scala 121:14] +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; +`endif // RANDOMIZE_REG_INIT + reg stateReg; // @[src/main/scala/peripheral/UART.scala 127:25] + reg [7:0] dataReg; // @[src/main/scala/peripheral/UART.scala 128:24] + wire _io_in_ready_T = ~stateReg; // @[src/main/scala/peripheral/UART.scala 130:27] + wire _GEN_1 = io_in_valid | stateReg; // @[src/main/scala/peripheral/UART.scala 134:23 136:16 127:25] + assign io_out_valid = stateReg; // @[src/main/scala/peripheral/UART.scala 131:28] + assign io_out_bits = dataReg; // @[src/main/scala/peripheral/UART.scala 143:15] + always @(posedge clock) begin + if (reset) begin // @[src/main/scala/peripheral/UART.scala 127:25] + stateReg <= 1'h0; // @[src/main/scala/peripheral/UART.scala 127:25] + end else if (_io_in_ready_T) begin // @[src/main/scala/peripheral/UART.scala 133:28] + stateReg <= _GEN_1; + end else if (io_out_ready) begin // @[src/main/scala/peripheral/UART.scala 139:24] + stateReg <= 1'h0; // @[src/main/scala/peripheral/UART.scala 140:16] + end + if (reset) begin // @[src/main/scala/peripheral/UART.scala 128:24] + dataReg <= 8'h0; // @[src/main/scala/peripheral/UART.scala 128:24] + end else if (_io_in_ready_T) begin // @[src/main/scala/peripheral/UART.scala 133:28] + if (io_in_valid) begin // @[src/main/scala/peripheral/UART.scala 134:23] + dataReg <= io_in_bits; // @[src/main/scala/peripheral/UART.scala 135:15] + end + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + stateReg = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + dataReg = _RAND_1[7:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module BufferedTx( + input clock, + input reset, + output io_txd, // @[src/main/scala/peripheral/UART.scala 150:14] + input io_channel_valid, // @[src/main/scala/peripheral/UART.scala 150:14] + input [7:0] io_channel_bits // @[src/main/scala/peripheral/UART.scala 150:14] +); + wire tx_clock; // @[src/main/scala/peripheral/UART.scala 155:18] + wire tx_reset; // @[src/main/scala/peripheral/UART.scala 155:18] + wire tx_io_txd; // @[src/main/scala/peripheral/UART.scala 155:18] + wire tx_io_channel_ready; // @[src/main/scala/peripheral/UART.scala 155:18] + wire tx_io_channel_valid; // @[src/main/scala/peripheral/UART.scala 155:18] + wire [7:0] tx_io_channel_bits; // @[src/main/scala/peripheral/UART.scala 155:18] + wire buf__clock; // @[src/main/scala/peripheral/UART.scala 156:19] + wire buf__reset; // @[src/main/scala/peripheral/UART.scala 156:19] + wire buf__io_in_valid; // @[src/main/scala/peripheral/UART.scala 156:19] + wire [7:0] buf__io_in_bits; // @[src/main/scala/peripheral/UART.scala 156:19] + wire buf__io_out_ready; // @[src/main/scala/peripheral/UART.scala 156:19] + wire buf__io_out_valid; // @[src/main/scala/peripheral/UART.scala 156:19] + wire [7:0] buf__io_out_bits; // @[src/main/scala/peripheral/UART.scala 156:19] + Tx tx ( // @[src/main/scala/peripheral/UART.scala 155:18] + .clock(tx_clock), + .reset(tx_reset), + .io_txd(tx_io_txd), + .io_channel_ready(tx_io_channel_ready), + .io_channel_valid(tx_io_channel_valid), + .io_channel_bits(tx_io_channel_bits) + ); + Buffer buf_ ( // @[src/main/scala/peripheral/UART.scala 156:19] + .clock(buf__clock), + .reset(buf__reset), + .io_in_valid(buf__io_in_valid), + .io_in_bits(buf__io_in_bits), + .io_out_ready(buf__io_out_ready), + .io_out_valid(buf__io_out_valid), + .io_out_bits(buf__io_out_bits) + ); + assign io_txd = tx_io_txd; // @[src/main/scala/peripheral/UART.scala 160:10] + assign tx_clock = clock; + assign tx_reset = reset; + assign tx_io_channel_valid = buf__io_out_valid; // @[src/main/scala/peripheral/UART.scala 159:17] + assign tx_io_channel_bits = buf__io_out_bits; // @[src/main/scala/peripheral/UART.scala 159:17] + assign buf__clock = clock; + assign buf__reset = reset; + assign buf__io_in_valid = io_channel_valid; // @[src/main/scala/peripheral/UART.scala 158:13] + assign buf__io_in_bits = io_channel_bits; // @[src/main/scala/peripheral/UART.scala 158:13] + assign buf__io_out_ready = tx_io_channel_ready; // @[src/main/scala/peripheral/UART.scala 159:17] +endmodule +module Rx( + input clock, + input reset, + input io_rxd, // @[src/main/scala/peripheral/UART.scala 77:14] + input io_channel_ready, // @[src/main/scala/peripheral/UART.scala 77:14] + output io_channel_valid, // @[src/main/scala/peripheral/UART.scala 77:14] + output [7:0] io_channel_bits // @[src/main/scala/peripheral/UART.scala 77:14] +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; +`endif // RANDOMIZE_REG_INIT + reg rxReg_REG; // @[src/main/scala/peripheral/UART.scala 87:30] + reg rxReg; // @[src/main/scala/peripheral/UART.scala 87:22] + reg [7:0] shiftReg; // @[src/main/scala/peripheral/UART.scala 89:25] + reg [19:0] cntReg; // @[src/main/scala/peripheral/UART.scala 90:23] + reg [3:0] bitsReg; // @[src/main/scala/peripheral/UART.scala 91:24] + reg valReg; // @[src/main/scala/peripheral/UART.scala 92:23] + wire [19:0] _cntReg_T_1 = cntReg - 20'h1; // @[src/main/scala/peripheral/UART.scala 95:22] + wire [7:0] _shiftReg_T_1 = {rxReg,shiftReg[7:1]}; // @[src/main/scala/peripheral/UART.scala 98:20] + wire [3:0] _bitsReg_T_1 = bitsReg - 4'h1; // @[src/main/scala/peripheral/UART.scala 99:24] + wire _GEN_0 = bitsReg == 4'h1 | valReg; // @[src/main/scala/peripheral/UART.scala 101:27 102:14 92:23] + assign io_channel_valid = valReg; // @[src/main/scala/peripheral/UART.scala 114:20] + assign io_channel_bits = shiftReg; // @[src/main/scala/peripheral/UART.scala 113:19] + always @(posedge clock) begin + rxReg_REG <= reset | io_rxd; // @[src/main/scala/peripheral/UART.scala 87:{30,30,30}] + rxReg <= reset | rxReg_REG; // @[src/main/scala/peripheral/UART.scala 87:{22,22,22}] + if (reset) begin // @[src/main/scala/peripheral/UART.scala 89:25] + shiftReg <= 8'h0; // @[src/main/scala/peripheral/UART.scala 89:25] + end else if (!(cntReg != 20'h0)) begin // @[src/main/scala/peripheral/UART.scala 94:24] + if (bitsReg != 4'h0) begin // @[src/main/scala/peripheral/UART.scala 96:31] + shiftReg <= _shiftReg_T_1; // @[src/main/scala/peripheral/UART.scala 98:14] + end + end + if (reset) begin // @[src/main/scala/peripheral/UART.scala 90:23] + cntReg <= 20'h0; // @[src/main/scala/peripheral/UART.scala 90:23] + end else if (cntReg != 20'h0) begin // @[src/main/scala/peripheral/UART.scala 94:24] + cntReg <= _cntReg_T_1; // @[src/main/scala/peripheral/UART.scala 95:12] + end else if (bitsReg != 4'h0) begin // @[src/main/scala/peripheral/UART.scala 96:31] + cntReg <= 20'h43c; // @[src/main/scala/peripheral/UART.scala 97:12] + end else if (~rxReg) begin // @[src/main/scala/peripheral/UART.scala 104:29] + cntReg <= 20'h65b; // @[src/main/scala/peripheral/UART.scala 105:12] + end + if (reset) begin // @[src/main/scala/peripheral/UART.scala 91:24] + bitsReg <= 4'h0; // @[src/main/scala/peripheral/UART.scala 91:24] + end else if (!(cntReg != 20'h0)) begin // @[src/main/scala/peripheral/UART.scala 94:24] + if (bitsReg != 4'h0) begin // @[src/main/scala/peripheral/UART.scala 96:31] + bitsReg <= _bitsReg_T_1; // @[src/main/scala/peripheral/UART.scala 99:13] + end else if (~rxReg) begin // @[src/main/scala/peripheral/UART.scala 104:29] + bitsReg <= 4'h8; // @[src/main/scala/peripheral/UART.scala 106:13] + end + end + if (reset) begin // @[src/main/scala/peripheral/UART.scala 92:23] + valReg <= 1'h0; // @[src/main/scala/peripheral/UART.scala 92:23] + end else if (valReg & io_channel_ready) begin // @[src/main/scala/peripheral/UART.scala 109:36] + valReg <= 1'h0; // @[src/main/scala/peripheral/UART.scala 110:12] + end else if (!(cntReg != 20'h0)) begin // @[src/main/scala/peripheral/UART.scala 94:24] + if (bitsReg != 4'h0) begin // @[src/main/scala/peripheral/UART.scala 96:31] + valReg <= _GEN_0; + end + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + rxReg_REG = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + rxReg = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + shiftReg = _RAND_2[7:0]; + _RAND_3 = {1{`RANDOM}}; + cntReg = _RAND_3[19:0]; + _RAND_4 = {1{`RANDOM}}; + bitsReg = _RAND_4[3:0]; + _RAND_5 = {1{`RANDOM}}; + valReg = _RAND_5[0:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module Uart( + input clock, + input reset, + input io_channels_write_address_channel_AWVALID, // @[src/main/scala/peripheral/UART.scala 164:14] + output io_channels_write_address_channel_AWREADY, // @[src/main/scala/peripheral/UART.scala 164:14] + input [7:0] io_channels_write_address_channel_AWADDR, // @[src/main/scala/peripheral/UART.scala 164:14] + input io_channels_write_data_channel_WVALID, // @[src/main/scala/peripheral/UART.scala 164:14] + output io_channels_write_data_channel_WREADY, // @[src/main/scala/peripheral/UART.scala 164:14] + input [31:0] io_channels_write_data_channel_WDATA, // @[src/main/scala/peripheral/UART.scala 164:14] + output io_channels_write_response_channel_BVALID, // @[src/main/scala/peripheral/UART.scala 164:14] + input io_channels_write_response_channel_BREADY, // @[src/main/scala/peripheral/UART.scala 164:14] + input io_channels_read_address_channel_ARVALID, // @[src/main/scala/peripheral/UART.scala 164:14] + output io_channels_read_address_channel_ARREADY, // @[src/main/scala/peripheral/UART.scala 164:14] + input [7:0] io_channels_read_address_channel_ARADDR, // @[src/main/scala/peripheral/UART.scala 164:14] + output io_channels_read_data_channel_RVALID, // @[src/main/scala/peripheral/UART.scala 164:14] + input io_channels_read_data_channel_RREADY, // @[src/main/scala/peripheral/UART.scala 164:14] + output [31:0] io_channels_read_data_channel_RDATA, // @[src/main/scala/peripheral/UART.scala 164:14] + input io_rxd, // @[src/main/scala/peripheral/UART.scala 164:14] + output io_txd, // @[src/main/scala/peripheral/UART.scala 164:14] + output io_signal_interrupt // @[src/main/scala/peripheral/UART.scala 164:14] +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; +`endif // RANDOMIZE_REG_INIT + wire slave_clock; // @[src/main/scala/peripheral/UART.scala 173:21] + wire slave_reset; // @[src/main/scala/peripheral/UART.scala 173:21] + wire slave_io_channels_write_address_channel_AWVALID; // @[src/main/scala/peripheral/UART.scala 173:21] + wire slave_io_channels_write_address_channel_AWREADY; // @[src/main/scala/peripheral/UART.scala 173:21] + wire [7:0] slave_io_channels_write_address_channel_AWADDR; // @[src/main/scala/peripheral/UART.scala 173:21] + wire slave_io_channels_write_data_channel_WVALID; // @[src/main/scala/peripheral/UART.scala 173:21] + wire slave_io_channels_write_data_channel_WREADY; // @[src/main/scala/peripheral/UART.scala 173:21] + wire [31:0] slave_io_channels_write_data_channel_WDATA; // @[src/main/scala/peripheral/UART.scala 173:21] + wire slave_io_channels_write_response_channel_BVALID; // @[src/main/scala/peripheral/UART.scala 173:21] + wire slave_io_channels_write_response_channel_BREADY; // @[src/main/scala/peripheral/UART.scala 173:21] + wire slave_io_channels_read_address_channel_ARVALID; // @[src/main/scala/peripheral/UART.scala 173:21] + wire slave_io_channels_read_address_channel_ARREADY; // @[src/main/scala/peripheral/UART.scala 173:21] + wire [7:0] slave_io_channels_read_address_channel_ARADDR; // @[src/main/scala/peripheral/UART.scala 173:21] + wire slave_io_channels_read_data_channel_RVALID; // @[src/main/scala/peripheral/UART.scala 173:21] + wire slave_io_channels_read_data_channel_RREADY; // @[src/main/scala/peripheral/UART.scala 173:21] + wire [31:0] slave_io_channels_read_data_channel_RDATA; // @[src/main/scala/peripheral/UART.scala 173:21] + wire slave_io_bundle_read; // @[src/main/scala/peripheral/UART.scala 173:21] + wire slave_io_bundle_write; // @[src/main/scala/peripheral/UART.scala 173:21] + wire [31:0] slave_io_bundle_read_data; // @[src/main/scala/peripheral/UART.scala 173:21] + wire [31:0] slave_io_bundle_write_data; // @[src/main/scala/peripheral/UART.scala 173:21] + wire [7:0] slave_io_bundle_address; // @[src/main/scala/peripheral/UART.scala 173:21] + wire tx_clock; // @[src/main/scala/peripheral/UART.scala 176:18] + wire tx_reset; // @[src/main/scala/peripheral/UART.scala 176:18] + wire tx_io_txd; // @[src/main/scala/peripheral/UART.scala 176:18] + wire tx_io_channel_valid; // @[src/main/scala/peripheral/UART.scala 176:18] + wire [7:0] tx_io_channel_bits; // @[src/main/scala/peripheral/UART.scala 176:18] + wire rx_clock; // @[src/main/scala/peripheral/UART.scala 177:18] + wire rx_reset; // @[src/main/scala/peripheral/UART.scala 177:18] + wire rx_io_rxd; // @[src/main/scala/peripheral/UART.scala 177:18] + wire rx_io_channel_ready; // @[src/main/scala/peripheral/UART.scala 177:18] + wire rx_io_channel_valid; // @[src/main/scala/peripheral/UART.scala 177:18] + wire [7:0] rx_io_channel_bits; // @[src/main/scala/peripheral/UART.scala 177:18] + reg interrupt; // @[src/main/scala/peripheral/UART.scala 171:26] + reg [7:0] rxData; // @[src/main/scala/peripheral/UART.scala 172:23] + wire [7:0] _GEN_0 = slave_io_bundle_address == 8'hc ? rxData : 8'h0; // @[src/main/scala/peripheral/UART.scala 179:29 184:51 185:33] + wire _GEN_1 = slave_io_bundle_address == 8'hc ? 1'h0 : interrupt; // @[src/main/scala/peripheral/UART.scala 184:51 186:17 171:26] + wire [16:0] _GEN_2 = slave_io_bundle_address == 8'h4 ? 17'h1c200 : {{9'd0}, _GEN_0}; // @[src/main/scala/peripheral/UART.scala 182:45 183:33] + wire _GEN_3 = slave_io_bundle_address == 8'h4 ? interrupt : _GEN_1; // @[src/main/scala/peripheral/UART.scala 171:26 182:45] + wire [16:0] _GEN_4 = slave_io_bundle_read ? _GEN_2 : 17'h0; // @[src/main/scala/peripheral/UART.scala 179:29 181:30] + wire _GEN_5 = slave_io_bundle_read ? _GEN_3 : interrupt; // @[src/main/scala/peripheral/UART.scala 171:26 181:30] + wire _T_3 = slave_io_bundle_address == 8'h10; // @[src/main/scala/peripheral/UART.scala 195:40] + wire [31:0] _GEN_7 = slave_io_bundle_address == 8'h10 ? slave_io_bundle_write_data : 32'h0; // @[src/main/scala/peripheral/UART.scala 191:22 195:52 197:26] + wire _GEN_8 = slave_io_bundle_address == 8'h8 ? slave_io_bundle_write_data != 32'h0 : _GEN_5; // @[src/main/scala/peripheral/UART.scala 193:45 194:17] + wire _GEN_9 = slave_io_bundle_address == 8'h8 ? 1'h0 : _T_3; // @[src/main/scala/peripheral/UART.scala 190:23 193:45] + wire [31:0] _GEN_10 = slave_io_bundle_address == 8'h8 ? 32'h0 : _GEN_7; // @[src/main/scala/peripheral/UART.scala 191:22 193:45] + wire _GEN_11 = slave_io_bundle_write ? _GEN_8 : _GEN_5; // @[src/main/scala/peripheral/UART.scala 192:31] + wire [31:0] _GEN_13 = slave_io_bundle_write ? _GEN_10 : 32'h0; // @[src/main/scala/peripheral/UART.scala 191:22 192:31] + wire _GEN_16 = rx_io_channel_valid | _GEN_11; // @[src/main/scala/peripheral/UART.scala 206:29 209:15] + AXI4LiteSlave slave ( // @[src/main/scala/peripheral/UART.scala 173:21] + .clock(slave_clock), + .reset(slave_reset), + .io_channels_write_address_channel_AWVALID(slave_io_channels_write_address_channel_AWVALID), + .io_channels_write_address_channel_AWREADY(slave_io_channels_write_address_channel_AWREADY), + .io_channels_write_address_channel_AWADDR(slave_io_channels_write_address_channel_AWADDR), + .io_channels_write_data_channel_WVALID(slave_io_channels_write_data_channel_WVALID), + .io_channels_write_data_channel_WREADY(slave_io_channels_write_data_channel_WREADY), + .io_channels_write_data_channel_WDATA(slave_io_channels_write_data_channel_WDATA), + .io_channels_write_response_channel_BVALID(slave_io_channels_write_response_channel_BVALID), + .io_channels_write_response_channel_BREADY(slave_io_channels_write_response_channel_BREADY), + .io_channels_read_address_channel_ARVALID(slave_io_channels_read_address_channel_ARVALID), + .io_channels_read_address_channel_ARREADY(slave_io_channels_read_address_channel_ARREADY), + .io_channels_read_address_channel_ARADDR(slave_io_channels_read_address_channel_ARADDR), + .io_channels_read_data_channel_RVALID(slave_io_channels_read_data_channel_RVALID), + .io_channels_read_data_channel_RREADY(slave_io_channels_read_data_channel_RREADY), + .io_channels_read_data_channel_RDATA(slave_io_channels_read_data_channel_RDATA), + .io_bundle_read(slave_io_bundle_read), + .io_bundle_write(slave_io_bundle_write), + .io_bundle_read_data(slave_io_bundle_read_data), + .io_bundle_write_data(slave_io_bundle_write_data), + .io_bundle_address(slave_io_bundle_address) + ); + BufferedTx tx ( // @[src/main/scala/peripheral/UART.scala 176:18] + .clock(tx_clock), + .reset(tx_reset), + .io_txd(tx_io_txd), + .io_channel_valid(tx_io_channel_valid), + .io_channel_bits(tx_io_channel_bits) + ); + Rx rx ( // @[src/main/scala/peripheral/UART.scala 177:18] + .clock(rx_clock), + .reset(rx_reset), + .io_rxd(rx_io_rxd), + .io_channel_ready(rx_io_channel_ready), + .io_channel_valid(rx_io_channel_valid), + .io_channel_bits(rx_io_channel_bits) + ); + assign io_channels_write_address_channel_AWREADY = slave_io_channels_write_address_channel_AWREADY; // @[src/main/scala/peripheral/UART.scala 174:21] + assign io_channels_write_data_channel_WREADY = slave_io_channels_write_data_channel_WREADY; // @[src/main/scala/peripheral/UART.scala 174:21] + assign io_channels_write_response_channel_BVALID = slave_io_channels_write_response_channel_BVALID; // @[src/main/scala/peripheral/UART.scala 174:21] + assign io_channels_read_address_channel_ARREADY = slave_io_channels_read_address_channel_ARREADY; // @[src/main/scala/peripheral/UART.scala 174:21] + assign io_channels_read_data_channel_RVALID = slave_io_channels_read_data_channel_RVALID; // @[src/main/scala/peripheral/UART.scala 174:21] + assign io_channels_read_data_channel_RDATA = slave_io_channels_read_data_channel_RDATA; // @[src/main/scala/peripheral/UART.scala 174:21] + assign io_txd = tx_io_txd; // @[src/main/scala/peripheral/UART.scala 201:10] + assign io_signal_interrupt = interrupt; // @[src/main/scala/peripheral/UART.scala 204:23] + assign slave_clock = clock; + assign slave_reset = reset; + assign slave_io_channels_write_address_channel_AWVALID = io_channels_write_address_channel_AWVALID; // @[src/main/scala/peripheral/UART.scala 174:21] + assign slave_io_channels_write_address_channel_AWADDR = io_channels_write_address_channel_AWADDR; // @[src/main/scala/peripheral/UART.scala 174:21] + assign slave_io_channels_write_data_channel_WVALID = io_channels_write_data_channel_WVALID; // @[src/main/scala/peripheral/UART.scala 174:21] + assign slave_io_channels_write_data_channel_WDATA = io_channels_write_data_channel_WDATA; // @[src/main/scala/peripheral/UART.scala 174:21] + assign slave_io_channels_write_response_channel_BREADY = io_channels_write_response_channel_BREADY; // @[src/main/scala/peripheral/UART.scala 174:21] + assign slave_io_channels_read_address_channel_ARVALID = io_channels_read_address_channel_ARVALID; // @[src/main/scala/peripheral/UART.scala 174:21] + assign slave_io_channels_read_address_channel_ARADDR = io_channels_read_address_channel_ARADDR; // @[src/main/scala/peripheral/UART.scala 174:21] + assign slave_io_channels_read_data_channel_RREADY = io_channels_read_data_channel_RREADY; // @[src/main/scala/peripheral/UART.scala 174:21] + assign slave_io_bundle_read_data = {{15'd0}, _GEN_4}; + assign tx_clock = clock; + assign tx_reset = reset; + assign tx_io_channel_valid = slave_io_bundle_write & _GEN_9; // @[src/main/scala/peripheral/UART.scala 190:23 192:31] + assign tx_io_channel_bits = _GEN_13[7:0]; + assign rx_clock = clock; + assign rx_reset = reset; + assign rx_io_rxd = io_rxd; // @[src/main/scala/peripheral/UART.scala 202:13] + assign rx_io_channel_ready = rx_io_channel_valid; // @[src/main/scala/peripheral/UART.scala 205:23 206:29 207:25] + always @(posedge clock) begin + if (reset) begin // @[src/main/scala/peripheral/UART.scala 171:26] + interrupt <= 1'h0; // @[src/main/scala/peripheral/UART.scala 171:26] + end else begin + interrupt <= _GEN_16; + end + if (reset) begin // @[src/main/scala/peripheral/UART.scala 172:23] + rxData <= 8'h0; // @[src/main/scala/peripheral/UART.scala 172:23] + end else if (rx_io_channel_valid) begin // @[src/main/scala/peripheral/UART.scala 206:29] + rxData <= rx_io_channel_bits; // @[src/main/scala/peripheral/UART.scala 208:12] + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + interrupt = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + rxData = _RAND_1[7:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module Control( + input io_jump_flag, // @[src/main/scala/riscv/core/fivestage/Control.scala 21:14] + input io_jump_instruction_id, // @[src/main/scala/riscv/core/fivestage/Control.scala 21:14] + input io_stall_flag_if, // @[src/main/scala/riscv/core/fivestage/Control.scala 21:14] + input io_stall_flag_mem, // @[src/main/scala/riscv/core/fivestage/Control.scala 21:14] + input io_stall_flag_clint, // @[src/main/scala/riscv/core/fivestage/Control.scala 21:14] + input io_stall_flag_bus, // @[src/main/scala/riscv/core/fivestage/Control.scala 21:14] + input [4:0] io_rs1_id, // @[src/main/scala/riscv/core/fivestage/Control.scala 21:14] + input [4:0] io_rs2_id, // @[src/main/scala/riscv/core/fivestage/Control.scala 21:14] + input io_memory_read_enable_ex, // @[src/main/scala/riscv/core/fivestage/Control.scala 21:14] + input [4:0] io_rd_ex, // @[src/main/scala/riscv/core/fivestage/Control.scala 21:14] + input io_memory_read_enable_mem, // @[src/main/scala/riscv/core/fivestage/Control.scala 21:14] + input [4:0] io_rd_mem, // @[src/main/scala/riscv/core/fivestage/Control.scala 21:14] + input io_csr_start_paging, // @[src/main/scala/riscv/core/fivestage/Control.scala 21:14] + output io_if_flush, // @[src/main/scala/riscv/core/fivestage/Control.scala 21:14] + output io_id_flush, // @[src/main/scala/riscv/core/fivestage/Control.scala 21:14] + output io_pc_stall, // @[src/main/scala/riscv/core/fivestage/Control.scala 21:14] + output io_if_stall, // @[src/main/scala/riscv/core/fivestage/Control.scala 21:14] + output io_id_stall, // @[src/main/scala/riscv/core/fivestage/Control.scala 21:14] + output io_ex_stall // @[src/main/scala/riscv/core/fivestage/Control.scala 21:14] +); + wire _id_hazard_T_3 = io_rd_ex == io_rs1_id; // @[src/main/scala/riscv/core/fivestage/Control.scala 44:105] + wire _id_hazard_T_5 = _id_hazard_T_3 | io_rd_ex == io_rs2_id; // @[src/main/scala/riscv/core/fivestage/Control.scala 45:5] + wire _id_hazard_T_6 = (io_memory_read_enable_ex | io_jump_instruction_id) & io_rd_ex != 5'h0 & _id_hazard_T_5; // @[src/main/scala/riscv/core/fivestage/Control.scala 44:92] + wire _id_hazard_T_11 = io_rd_mem == io_rs2_id; // @[src/main/scala/riscv/core/fivestage/Control.scala 47:7] + wire _id_hazard_T_13 = io_jump_instruction_id & io_memory_read_enable_mem & io_rd_mem != 5'h0 & (io_rd_mem == + io_rs1_id | _id_hazard_T_11); // @[src/main/scala/riscv/core/fivestage/Control.scala 46:78] + wire id_hazard = _id_hazard_T_6 | _id_hazard_T_13; // @[src/main/scala/riscv/core/fivestage/Control.scala 45:32] + wire _io_pc_stall_T = io_stall_flag_mem | io_stall_flag_clint; // @[src/main/scala/riscv/core/fivestage/Control.scala 51:36] + assign io_if_flush = io_jump_flag & ~id_hazard | io_csr_start_paging; // @[src/main/scala/riscv/core/fivestage/Control.scala 48:45] + assign io_id_flush = id_hazard | io_csr_start_paging; // @[src/main/scala/riscv/core/fivestage/Control.scala 49:28] + assign io_pc_stall = io_stall_flag_mem | io_stall_flag_clint | id_hazard | io_stall_flag_bus | io_stall_flag_if; // @[src/main/scala/riscv/core/fivestage/Control.scala 51:93] + assign io_if_stall = _io_pc_stall_T | id_hazard; // @[src/main/scala/riscv/core/fivestage/Control.scala 52:59] + assign io_id_stall = io_stall_flag_mem | io_stall_flag_clint; // @[src/main/scala/riscv/core/fivestage/Control.scala 53:36] + assign io_ex_stall = io_stall_flag_mem | io_stall_flag_clint; // @[src/main/scala/riscv/core/fivestage/Control.scala 54:36] +endmodule +module RegisterFile( + input clock, + input reset, + input io_write_enable, // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 33:14] + input [4:0] io_write_address, // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 33:14] + input [31:0] io_write_data, // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 33:14] + input [4:0] io_read_address1, // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 33:14] + input [4:0] io_read_address2, // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 33:14] + output [31:0] io_read_data1, // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 33:14] + output [31:0] io_read_data2 // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 33:14] +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; +`endif // RANDOMIZE_REG_INIT + reg [31:0] registers_0; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_1; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_2; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_3; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_4; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_5; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_6; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_7; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_8; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_9; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_10; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_11; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_12; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_13; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_14; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_15; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_16; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_17; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_18; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_19; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_20; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_21; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_22; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_23; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_24; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_25; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_26; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_27; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_28; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_29; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_30; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + reg [31:0] registers_31; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 46:22] + wire _io_read_data1_T = io_read_address1 == 5'h0; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 57:25] + wire _io_read_data1_T_2 = io_read_address1 == io_write_address & io_write_enable; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 58:46] + wire [31:0] _GEN_97 = 5'h1 == io_read_address1 ? registers_1 : registers_0; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_98 = 5'h2 == io_read_address1 ? registers_2 : _GEN_97; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_99 = 5'h3 == io_read_address1 ? registers_3 : _GEN_98; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_100 = 5'h4 == io_read_address1 ? registers_4 : _GEN_99; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_101 = 5'h5 == io_read_address1 ? registers_5 : _GEN_100; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_102 = 5'h6 == io_read_address1 ? registers_6 : _GEN_101; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_103 = 5'h7 == io_read_address1 ? registers_7 : _GEN_102; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_104 = 5'h8 == io_read_address1 ? registers_8 : _GEN_103; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_105 = 5'h9 == io_read_address1 ? registers_9 : _GEN_104; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_106 = 5'ha == io_read_address1 ? registers_10 : _GEN_105; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_107 = 5'hb == io_read_address1 ? registers_11 : _GEN_106; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_108 = 5'hc == io_read_address1 ? registers_12 : _GEN_107; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_109 = 5'hd == io_read_address1 ? registers_13 : _GEN_108; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_110 = 5'he == io_read_address1 ? registers_14 : _GEN_109; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_111 = 5'hf == io_read_address1 ? registers_15 : _GEN_110; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_112 = 5'h10 == io_read_address1 ? registers_16 : _GEN_111; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_113 = 5'h11 == io_read_address1 ? registers_17 : _GEN_112; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_114 = 5'h12 == io_read_address1 ? registers_18 : _GEN_113; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_115 = 5'h13 == io_read_address1 ? registers_19 : _GEN_114; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_116 = 5'h14 == io_read_address1 ? registers_20 : _GEN_115; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_117 = 5'h15 == io_read_address1 ? registers_21 : _GEN_116; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_118 = 5'h16 == io_read_address1 ? registers_22 : _GEN_117; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_119 = 5'h17 == io_read_address1 ? registers_23 : _GEN_118; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_120 = 5'h18 == io_read_address1 ? registers_24 : _GEN_119; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_121 = 5'h19 == io_read_address1 ? registers_25 : _GEN_120; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_122 = 5'h1a == io_read_address1 ? registers_26 : _GEN_121; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_123 = 5'h1b == io_read_address1 ? registers_27 : _GEN_122; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_124 = 5'h1c == io_read_address1 ? registers_28 : _GEN_123; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_125 = 5'h1d == io_read_address1 ? registers_29 : _GEN_124; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_126 = 5'h1e == io_read_address1 ? registers_30 : _GEN_125; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_127 = 5'h1f == io_read_address1 ? registers_31 : _GEN_126; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _io_read_data1_T_3 = _io_read_data1_T_2 ? io_write_data : _GEN_127; // @[src/main/scala/chisel3/util/Mux.scala 141:16] + wire _io_read_data2_T = io_read_address2 == 5'h0; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 65:25] + wire _io_read_data2_T_2 = io_read_address2 == io_write_address & io_write_enable; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 66:46] + wire [31:0] _GEN_129 = 5'h1 == io_read_address2 ? registers_1 : registers_0; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_130 = 5'h2 == io_read_address2 ? registers_2 : _GEN_129; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_131 = 5'h3 == io_read_address2 ? registers_3 : _GEN_130; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_132 = 5'h4 == io_read_address2 ? registers_4 : _GEN_131; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_133 = 5'h5 == io_read_address2 ? registers_5 : _GEN_132; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_134 = 5'h6 == io_read_address2 ? registers_6 : _GEN_133; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_135 = 5'h7 == io_read_address2 ? registers_7 : _GEN_134; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_136 = 5'h8 == io_read_address2 ? registers_8 : _GEN_135; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_137 = 5'h9 == io_read_address2 ? registers_9 : _GEN_136; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_138 = 5'ha == io_read_address2 ? registers_10 : _GEN_137; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_139 = 5'hb == io_read_address2 ? registers_11 : _GEN_138; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_140 = 5'hc == io_read_address2 ? registers_12 : _GEN_139; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_141 = 5'hd == io_read_address2 ? registers_13 : _GEN_140; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_142 = 5'he == io_read_address2 ? registers_14 : _GEN_141; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_143 = 5'hf == io_read_address2 ? registers_15 : _GEN_142; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_144 = 5'h10 == io_read_address2 ? registers_16 : _GEN_143; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_145 = 5'h11 == io_read_address2 ? registers_17 : _GEN_144; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_146 = 5'h12 == io_read_address2 ? registers_18 : _GEN_145; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_147 = 5'h13 == io_read_address2 ? registers_19 : _GEN_146; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_148 = 5'h14 == io_read_address2 ? registers_20 : _GEN_147; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_149 = 5'h15 == io_read_address2 ? registers_21 : _GEN_148; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_150 = 5'h16 == io_read_address2 ? registers_22 : _GEN_149; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_151 = 5'h17 == io_read_address2 ? registers_23 : _GEN_150; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_152 = 5'h18 == io_read_address2 ? registers_24 : _GEN_151; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_153 = 5'h19 == io_read_address2 ? registers_25 : _GEN_152; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_154 = 5'h1a == io_read_address2 ? registers_26 : _GEN_153; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_155 = 5'h1b == io_read_address2 ? registers_27 : _GEN_154; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_156 = 5'h1c == io_read_address2 ? registers_28 : _GEN_155; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_157 = 5'h1d == io_read_address2 ? registers_29 : _GEN_156; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_158 = 5'h1e == io_read_address2 ? registers_30 : _GEN_157; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _GEN_159 = 5'h1f == io_read_address2 ? registers_31 : _GEN_158; // @[src/main/scala/chisel3/util/Mux.scala 141:{16,16}] + wire [31:0] _io_read_data2_T_3 = _io_read_data2_T_2 ? io_write_data : _GEN_159; // @[src/main/scala/chisel3/util/Mux.scala 141:16] + assign io_read_data1 = _io_read_data1_T ? 32'h0 : _io_read_data1_T_3; // @[src/main/scala/chisel3/util/Mux.scala 141:16] + assign io_read_data2 = _io_read_data2_T ? 32'h0 : _io_read_data2_T_3; // @[src/main/scala/chisel3/util/Mux.scala 141:16] + always @(posedge clock) begin + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'h0 == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_0 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'h1 == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_1 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'h2 == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_2 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'h3 == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_3 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'h4 == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_4 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'h5 == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_5 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'h6 == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_6 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'h7 == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_7 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'h8 == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_8 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'h9 == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_9 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'ha == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_10 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'hb == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_11 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'hc == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_12 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'hd == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_13 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'he == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_14 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'hf == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_15 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'h10 == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_16 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'h11 == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_17 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'h12 == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_18 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'h13 == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_19 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'h14 == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_20 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'h15 == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_21 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'h16 == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_22 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'h17 == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_23 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'h18 == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_24 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'h19 == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_25 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'h1a == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_26 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'h1b == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_27 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'h1c == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_28 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'h1d == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_29 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'h1e == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_30 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + if (~reset) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 48:23] + if (io_write_enable & io_write_address != 5'h0) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 49:55] + if (5'h1f == io_write_address) begin // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + registers_31 <= io_write_data; // @[src/main/scala/riscv/core/fivestage/RegisterFile.scala 50:35] + end + end + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + registers_0 = _RAND_0[31:0]; + _RAND_1 = {1{`RANDOM}}; + registers_1 = _RAND_1[31:0]; + _RAND_2 = {1{`RANDOM}}; + registers_2 = _RAND_2[31:0]; + _RAND_3 = {1{`RANDOM}}; + registers_3 = _RAND_3[31:0]; + _RAND_4 = {1{`RANDOM}}; + registers_4 = _RAND_4[31:0]; + _RAND_5 = {1{`RANDOM}}; + registers_5 = _RAND_5[31:0]; + _RAND_6 = {1{`RANDOM}}; + registers_6 = _RAND_6[31:0]; + _RAND_7 = {1{`RANDOM}}; + registers_7 = _RAND_7[31:0]; + _RAND_8 = {1{`RANDOM}}; + registers_8 = _RAND_8[31:0]; + _RAND_9 = {1{`RANDOM}}; + registers_9 = _RAND_9[31:0]; + _RAND_10 = {1{`RANDOM}}; + registers_10 = _RAND_10[31:0]; + _RAND_11 = {1{`RANDOM}}; + registers_11 = _RAND_11[31:0]; + _RAND_12 = {1{`RANDOM}}; + registers_12 = _RAND_12[31:0]; + _RAND_13 = {1{`RANDOM}}; + registers_13 = _RAND_13[31:0]; + _RAND_14 = {1{`RANDOM}}; + registers_14 = _RAND_14[31:0]; + _RAND_15 = {1{`RANDOM}}; + registers_15 = _RAND_15[31:0]; + _RAND_16 = {1{`RANDOM}}; + registers_16 = _RAND_16[31:0]; + _RAND_17 = {1{`RANDOM}}; + registers_17 = _RAND_17[31:0]; + _RAND_18 = {1{`RANDOM}}; + registers_18 = _RAND_18[31:0]; + _RAND_19 = {1{`RANDOM}}; + registers_19 = _RAND_19[31:0]; + _RAND_20 = {1{`RANDOM}}; + registers_20 = _RAND_20[31:0]; + _RAND_21 = {1{`RANDOM}}; + registers_21 = _RAND_21[31:0]; + _RAND_22 = {1{`RANDOM}}; + registers_22 = _RAND_22[31:0]; + _RAND_23 = {1{`RANDOM}}; + registers_23 = _RAND_23[31:0]; + _RAND_24 = {1{`RANDOM}}; + registers_24 = _RAND_24[31:0]; + _RAND_25 = {1{`RANDOM}}; + registers_25 = _RAND_25[31:0]; + _RAND_26 = {1{`RANDOM}}; + registers_26 = _RAND_26[31:0]; + _RAND_27 = {1{`RANDOM}}; + registers_27 = _RAND_27[31:0]; + _RAND_28 = {1{`RANDOM}}; + registers_28 = _RAND_28[31:0]; + _RAND_29 = {1{`RANDOM}}; + registers_29 = _RAND_29[31:0]; + _RAND_30 = {1{`RANDOM}}; + registers_30 = _RAND_30[31:0]; + _RAND_31 = {1{`RANDOM}}; + registers_31 = _RAND_31[31:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module InstructionFetch( + input clock, + input reset, + input io_stall_flag_ctrl, // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 31:14] + input io_jump_flag_id, // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 31:14] + input [31:0] io_jump_address_id, // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 31:14] + input [31:0] io_physical_address, // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 31:14] + output io_ctrl_stall_flag, // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 31:14] + output [31:0] io_id_instruction_address, // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 31:14] + output [31:0] io_id_instruction, // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 31:14] + output io_pc_valid, // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 31:14] + output io_bus_read, // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 31:14] + output [31:0] io_bus_address, // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 31:14] + input [31:0] io_bus_read_data, // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 31:14] + input io_bus_read_valid, // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 31:14] + input io_bus_granted // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 31:14] +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; +`endif // RANDOMIZE_REG_INIT + reg pending_jump; // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 45:29] + reg [31:0] pc; // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 46:19] + reg state; // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 47:22] + reg pc_valid; // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 48:25] + wire _GEN_0 = ~pc_valid & pc == 32'h1000 | pc_valid; // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 58:57 59:14 48:25] + wire [31:0] _pc_T_1 = pc + 32'h4; // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 63:8] + wire _T_3 = ~io_bus_read_valid; // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 70:8] + wire _GEN_1 = io_jump_flag_id | pending_jump; // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 71:27 72:20 45:29] + wire _GEN_2 = ~io_bus_read_valid ? _GEN_1 : pending_jump; // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 70:28 45:29] + wire _T_4 = ~state; // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 83:16] + wire _GEN_5 = io_bus_read_valid ? 1'h0 : state; // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 90:31 91:15 47:22] + wire _GEN_8 = state ? _GEN_5 : state; // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 47:22 87:47] + wire _GEN_11 = ~state | _GEN_8; // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 83:41 86:13] + wire _io_id_instruction_T_3 = io_bus_read_valid & ~pending_jump & ~io_jump_flag_id; // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 97:40] + assign io_ctrl_stall_flag = _T_3 | pending_jump; // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 101:44] + assign io_id_instruction_address = pc; // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 102:29] + assign io_id_instruction = _io_id_instruction_T_3 ? io_bus_read_data : 32'h13; // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 96:27] + assign io_pc_valid = pc_valid; // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 56:15] + assign io_bus_read = io_bus_granted & _T_4; // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 51:15 82:24] + assign io_bus_address = io_physical_address; // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 103:18] + always @(posedge clock) begin + if (reset) begin // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 45:29] + pending_jump <= 1'h0; // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 45:29] + end else if (io_bus_read_valid) begin // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 76:27] + if (pending_jump) begin // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 77:24] + pending_jump <= 1'h0; // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 78:20] + end else begin + pending_jump <= _GEN_2; + end + end else begin + pending_jump <= _GEN_2; + end + if (reset) begin // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 46:19] + pc <= 32'h1000; // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 46:19] + end else if (io_jump_flag_id) begin // @[src/main/scala/chisel3/util/Mux.scala 141:16] + pc <= io_jump_address_id; + end else if (!(io_stall_flag_ctrl)) begin // @[src/main/scala/chisel3/util/Mux.scala 141:16] + pc <= _pc_T_1; + end + if (reset) begin // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 47:22] + state <= 1'h0; // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 47:22] + end else if (io_bus_granted) begin // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 82:24] + state <= _GEN_11; + end + if (reset) begin // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 48:25] + pc_valid <= 1'h0; // @[src/main/scala/riscv/core/fivestage/InstructionFetch.scala 48:25] + end else begin + pc_valid <= _GEN_0; + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + pending_jump = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + pc = _RAND_1[31:0]; + _RAND_2 = {1{`RANDOM}}; + state = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + pc_valid = _RAND_3[0:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module PipelineRegister( + input clock, + input reset, + input io_write_enable, // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + input io_flush_enable, // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + input [31:0] io_in, // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + output [31:0] io_out // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; +`endif // RANDOMIZE_REG_INIT + reg [31:0] reg_; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + assign io_out = reg_; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + always @(posedge clock) begin + if (reset) begin // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + reg_ <= 32'h13; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + end else if (io_write_enable) begin // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg_ <= io_in; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + end else if (io_flush_enable) begin // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg_ <= 32'h13; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + reg_ = _RAND_0[31:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module PipelineRegister_1( + input clock, + input reset, + input io_write_enable, // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + input io_flush_enable, // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + input [31:0] io_in, // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + output [31:0] io_out // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; +`endif // RANDOMIZE_REG_INIT + reg [31:0] reg_; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + assign io_out = reg_; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + always @(posedge clock) begin + if (reset) begin // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + reg_ <= 32'h1000; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + end else if (io_write_enable) begin // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg_ <= io_in; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + end else if (io_flush_enable) begin // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg_ <= 32'h1000; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + reg_ = _RAND_0[31:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module PipelineRegister_2( + input clock, + input reset, + input io_write_enable, // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + input io_flush_enable, // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + input [31:0] io_in, // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + output [31:0] io_out // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; +`endif // RANDOMIZE_REG_INIT + reg [31:0] reg_; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + assign io_out = reg_; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + always @(posedge clock) begin + if (reset) begin // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + reg_ <= 32'h0; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + end else if (io_write_enable) begin // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg_ <= io_in; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + end else if (io_flush_enable) begin // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg_ <= 32'h0; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + reg_ = _RAND_0[31:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module IF2ID( + input clock, + input reset, + input io_stall_flag, // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 21:14] + input io_flush_enable, // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 21:14] + input [31:0] io_instruction, // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 21:14] + input [31:0] io_instruction_address, // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 21:14] + input [31:0] io_interrupt_flag, // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 21:14] + output [31:0] io_output_instruction, // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 21:14] + output [31:0] io_output_instruction_address, // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 21:14] + output [31:0] io_output_interrupt_flag // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 21:14] +); + wire instruction_clock; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 35:27] + wire instruction_reset; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 35:27] + wire instruction_io_write_enable; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 35:27] + wire instruction_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 35:27] + wire [31:0] instruction_io_in; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 35:27] + wire [31:0] instruction_io_out; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 35:27] + wire instruction_address_clock; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 41:35] + wire instruction_address_reset; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 41:35] + wire instruction_address_io_write_enable; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 41:35] + wire instruction_address_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 41:35] + wire [31:0] instruction_address_io_in; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 41:35] + wire [31:0] instruction_address_io_out; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 41:35] + wire interrupt_flag_clock; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 47:30] + wire interrupt_flag_reset; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 47:30] + wire interrupt_flag_io_write_enable; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 47:30] + wire interrupt_flag_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 47:30] + wire [31:0] interrupt_flag_io_in; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 47:30] + wire [31:0] interrupt_flag_io_out; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 47:30] + PipelineRegister instruction ( // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 35:27] + .clock(instruction_clock), + .reset(instruction_reset), + .io_write_enable(instruction_io_write_enable), + .io_flush_enable(instruction_io_flush_enable), + .io_in(instruction_io_in), + .io_out(instruction_io_out) + ); + PipelineRegister_1 instruction_address ( // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 41:35] + .clock(instruction_address_clock), + .reset(instruction_address_reset), + .io_write_enable(instruction_address_io_write_enable), + .io_flush_enable(instruction_address_io_flush_enable), + .io_in(instruction_address_io_in), + .io_out(instruction_address_io_out) + ); + PipelineRegister_2 interrupt_flag ( // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 47:30] + .clock(interrupt_flag_clock), + .reset(interrupt_flag_reset), + .io_write_enable(interrupt_flag_io_write_enable), + .io_flush_enable(interrupt_flag_io_flush_enable), + .io_in(interrupt_flag_io_in), + .io_out(interrupt_flag_io_out) + ); + assign io_output_instruction = instruction_io_out; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 39:25] + assign io_output_instruction_address = instruction_address_io_out; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 45:33] + assign io_output_interrupt_flag = interrupt_flag_io_out; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 51:28] + assign instruction_clock = clock; + assign instruction_reset = reset; + assign instruction_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 33:22] + assign instruction_io_flush_enable = io_flush_enable; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 38:31] + assign instruction_io_in = io_instruction; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 36:21] + assign instruction_address_clock = clock; + assign instruction_address_reset = reset; + assign instruction_address_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 33:22] + assign instruction_address_io_flush_enable = io_flush_enable; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 44:39] + assign instruction_address_io_in = io_instruction_address; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 42:29] + assign interrupt_flag_clock = clock; + assign interrupt_flag_reset = reset; + assign interrupt_flag_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 33:22] + assign interrupt_flag_io_flush_enable = io_flush_enable; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 50:34] + assign interrupt_flag_io_in = io_interrupt_flag; // @[src/main/scala/riscv/core/fivestage/IF2ID.scala 48:24] +endmodule +module InstructionDecode( + input [31:0] io_instruction, // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 136:14] + input [31:0] io_instruction_address, // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 136:14] + input [31:0] io_reg1_data, // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 136:14] + input [31:0] io_reg2_data, // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 136:14] + input [31:0] io_forward_from_mem, // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 136:14] + input [31:0] io_forward_from_wb, // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 136:14] + input [1:0] io_reg1_forward, // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 136:14] + input [1:0] io_reg2_forward, // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 136:14] + input io_interrupt_assert, // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 136:14] + input [31:0] io_interrupt_handler_address, // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 136:14] + output [4:0] io_regs_reg1_read_address, // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 136:14] + output [4:0] io_regs_reg2_read_address, // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 136:14] + output [31:0] io_ex_immediate, // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 136:14] + output io_ex_aluop1_source, // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 136:14] + output io_ex_aluop2_source, // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 136:14] + output io_ex_memory_read_enable, // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 136:14] + output io_ex_memory_write_enable, // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 136:14] + output [1:0] io_ex_reg_write_source, // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 136:14] + output io_ex_reg_write_enable, // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 136:14] + output [4:0] io_ex_reg_write_address, // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 136:14] + output [11:0] io_ex_csr_address, // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 136:14] + output io_ex_csr_write_enable, // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 136:14] + output io_ctrl_jump_instruction, // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 136:14] + output [31:0] io_clint_jump_address, // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 136:14] + output io_if_jump_flag, // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 136:14] + output [31:0] io_if_jump_address // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 136:14] +); + wire [6:0] opcode = io_instruction[6:0]; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 168:30] + wire [2:0] funct3 = io_instruction[14:12]; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 169:30] + wire [4:0] rd = io_instruction[11:7]; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 171:26] + wire [4:0] rs1 = io_instruction[19:15]; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 172:27] + wire _io_regs_reg1_read_address_T = opcode == 7'h37; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 175:43] + wire [19:0] _io_ex_immediate_T_2 = io_instruction[31] ? 20'hfffff : 20'h0; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:48] + wire [31:0] _io_ex_immediate_T_4 = {_io_ex_immediate_T_2,io_instruction[31:20]}; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:43] + wire [20:0] _io_ex_immediate_T_7 = io_instruction[31] ? 21'h1fffff : 21'h0; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 181:37] + wire [31:0] _io_ex_immediate_T_9 = {_io_ex_immediate_T_7,io_instruction[30:20]}; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 181:32] + wire [31:0] _io_ex_immediate_T_25 = {_io_ex_immediate_T_7,io_instruction[30:25],rd}; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 184:32] + wire [31:0] _io_ex_immediate_T_32 = {_io_ex_immediate_T_2,io_instruction[7],io_instruction[30:25],io_instruction[11:8] + ,1'h0}; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 185:32] + wire [31:0] _io_ex_immediate_T_34 = {io_instruction[31:12],12'h0}; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 187:30] + wire [11:0] _io_ex_immediate_T_39 = io_instruction[31] ? 12'hfff : 12'h0; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 189:35] + wire [31:0] _io_ex_immediate_T_43 = {_io_ex_immediate_T_39,io_instruction[19:12],io_instruction[20],io_instruction[30: + 21],1'h0}; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 189:30] + wire [31:0] _io_ex_immediate_T_45 = 7'h13 == opcode ? _io_ex_immediate_T_9 : _io_ex_immediate_T_4; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:98] + wire _io_ex_immediate_T_46 = 7'h3 == opcode; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:98] + wire [31:0] _io_ex_immediate_T_47 = 7'h3 == opcode ? _io_ex_immediate_T_9 : _io_ex_immediate_T_45; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:98] + wire _io_ex_immediate_T_48 = 7'h67 == opcode; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:98] + wire [31:0] _io_ex_immediate_T_49 = 7'h67 == opcode ? _io_ex_immediate_T_9 : _io_ex_immediate_T_47; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:98] + wire [31:0] _io_ex_immediate_T_51 = 7'h23 == opcode ? _io_ex_immediate_T_25 : _io_ex_immediate_T_49; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:98] + wire [31:0] _io_ex_immediate_T_53 = 7'h63 == opcode ? _io_ex_immediate_T_32 : _io_ex_immediate_T_51; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:98] + wire [31:0] _io_ex_immediate_T_55 = 7'h37 == opcode ? _io_ex_immediate_T_34 : _io_ex_immediate_T_53; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:98] + wire [31:0] _io_ex_immediate_T_57 = 7'h17 == opcode ? _io_ex_immediate_T_34 : _io_ex_immediate_T_55; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:98] + wire _io_ex_immediate_T_58 = 7'h6f == opcode; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:98] + wire _io_ex_aluop1_source_T = opcode == 7'h17; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 194:12] + wire _io_ex_aluop1_source_T_1 = opcode == 7'h63; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 194:45] + wire _io_ex_aluop1_source_T_3 = opcode == 7'h6f; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 194:78] + wire _io_ex_aluop2_source_T = opcode == 7'h33; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 199:12] + wire _io_ex_memory_read_enable_T = opcode == 7'h3; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 203:38] + wire [1:0] _io_ex_reg_write_source_T_1 = _io_ex_immediate_T_46 ? 2'h1 : 2'h0; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 205:72] + wire [1:0] _io_ex_reg_write_source_T_3 = 7'h73 == opcode ? 2'h2 : _io_ex_reg_write_source_T_1; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 205:72] + wire [1:0] _io_ex_reg_write_source_T_5 = _io_ex_immediate_T_58 ? 2'h3 : _io_ex_reg_write_source_T_3; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 205:72] + wire _io_ex_reg_write_enable_T_4 = _io_ex_aluop2_source_T | opcode == 7'h13 | _io_ex_memory_read_enable_T; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 213:97] + wire _io_ex_reg_write_enable_T_10 = _io_ex_reg_write_enable_T_4 | _io_ex_aluop1_source_T | + _io_regs_reg1_read_address_T | _io_ex_aluop1_source_T_3; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 214:105] + wire _io_ex_reg_write_enable_T_11 = opcode == 7'h67; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 215:46] + wire _io_ex_reg_write_enable_T_13 = opcode == 7'h73; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 215:80] + wire _io_ex_csr_write_enable_T_4 = funct3 == 3'h2; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 220:14] + wire _io_ex_csr_write_enable_T_5 = funct3 == 3'h1 | funct3 == 3'h5 | _io_ex_csr_write_enable_T_4; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 219:83] + wire _io_ex_csr_write_enable_T_8 = funct3 == 3'h3; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 221:14] + wire _io_ex_csr_write_enable_T_9 = _io_ex_csr_write_enable_T_5 | funct3 == 3'h6 | _io_ex_csr_write_enable_T_8; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 220:85] + wire _io_ex_csr_write_enable_T_11 = _io_ex_csr_write_enable_T_9 | funct3 == 3'h7; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 221:44] + wire [31:0] _reg1_data_T_1 = 2'h1 == io_reg1_forward ? io_forward_from_mem : io_reg1_data; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 224:59] + wire [31:0] reg1_data = 2'h2 == io_reg1_forward ? io_forward_from_wb : _reg1_data_T_1; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 224:59] + wire [31:0] _reg2_data_T_1 = 2'h1 == io_reg2_forward ? io_forward_from_mem : io_reg2_data; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 230:59] + wire [31:0] reg2_data = 2'h2 == io_reg2_forward ? io_forward_from_wb : _reg2_data_T_1; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 230:59] + wire _io_ctrl_jump_instruction_T_2 = _io_ex_aluop1_source_T_3 | _io_ex_reg_write_enable_T_11; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 236:61] + wire _instruction_jump_flag_T_4 = reg1_data == reg2_data; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 242:45] + wire _instruction_jump_flag_T_5 = reg1_data != reg2_data; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 243:45] + wire [31:0] _instruction_jump_flag_T_6 = 2'h2 == io_reg1_forward ? io_forward_from_wb : _reg1_data_T_1; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 244:45] + wire [31:0] _instruction_jump_flag_T_7 = 2'h2 == io_reg2_forward ? io_forward_from_wb : _reg2_data_T_1; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 244:64] + wire _instruction_jump_flag_T_8 = $signed(_instruction_jump_flag_T_6) < $signed(_instruction_jump_flag_T_7); // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 244:52] + wire _instruction_jump_flag_T_11 = $signed(_instruction_jump_flag_T_6) >= $signed(_instruction_jump_flag_T_7); // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 245:52] + wire _instruction_jump_flag_T_12 = reg1_data < reg2_data; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 246:53] + wire _instruction_jump_flag_T_13 = reg1_data >= reg2_data; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 247:53] + wire _instruction_jump_flag_T_17 = 3'h1 == funct3 ? _instruction_jump_flag_T_5 : 3'h0 == funct3 & + _instruction_jump_flag_T_4; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 240:66] + wire _instruction_jump_flag_T_19 = 3'h4 == funct3 ? _instruction_jump_flag_T_8 : _instruction_jump_flag_T_17; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 240:66] + wire _instruction_jump_flag_T_21 = 3'h5 == funct3 ? _instruction_jump_flag_T_11 : _instruction_jump_flag_T_19; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 240:66] + wire _instruction_jump_flag_T_23 = 3'h6 == funct3 ? _instruction_jump_flag_T_12 : _instruction_jump_flag_T_21; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 240:66] + wire _instruction_jump_flag_T_25 = 3'h7 == funct3 ? _instruction_jump_flag_T_13 : _instruction_jump_flag_T_23; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 240:66] + wire _instruction_jump_flag_T_26 = _io_ex_aluop1_source_T_1 & _instruction_jump_flag_T_25; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 240:37] + wire instruction_jump_flag = _io_ctrl_jump_instruction_T_2 | _instruction_jump_flag_T_26; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 239:36] + wire [31:0] _instruction_jump_address_T_1 = _io_ex_reg_write_enable_T_11 ? reg1_data : io_instruction_address; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 250:55] + wire [31:0] instruction_jump_address = io_ex_immediate + _instruction_jump_address_T_1; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 250:50] + assign io_regs_reg1_read_address = opcode == 7'h37 ? 5'h0 : rs1; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 175:35] + assign io_regs_reg2_read_address = io_instruction[24:20]; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 173:27] + assign io_ex_immediate = 7'h6f == opcode ? _io_ex_immediate_T_43 : _io_ex_immediate_T_57; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 179:98] + assign io_ex_aluop1_source = opcode == 7'h17 | opcode == 7'h63 | opcode == 7'h6f; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 194:68] + assign io_ex_aluop2_source = _io_ex_aluop2_source_T ? 1'h0 : 1'h1; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 198:29] + assign io_ex_memory_read_enable = opcode == 7'h3; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 203:38] + assign io_ex_memory_write_enable = opcode == 7'h23; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 204:39] + assign io_ex_reg_write_source = _io_ex_immediate_T_48 ? 2'h3 : _io_ex_reg_write_source_T_5; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 205:72] + assign io_ex_reg_write_enable = _io_ex_reg_write_enable_T_10 | opcode == 7'h67 | opcode == 7'h73; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 215:69] + assign io_ex_reg_write_address = io_instruction[11:7]; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 216:44] + assign io_ex_csr_address = io_instruction[31:20]; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 217:38] + assign io_ex_csr_write_enable = _io_ex_reg_write_enable_T_13 & _io_ex_csr_write_enable_T_11; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 218:59] + assign io_ctrl_jump_instruction = _io_ctrl_jump_instruction_T_2 | _io_ex_aluop1_source_T_1; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 237:36] + assign io_clint_jump_address = io_ex_immediate + _instruction_jump_address_T_1; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 250:50] + assign io_if_jump_flag = io_interrupt_assert | instruction_jump_flag; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 253:42] + assign io_if_jump_address = io_interrupt_assert ? io_interrupt_handler_address : instruction_jump_address; // @[src/main/scala/riscv/core/fivestage/InstructionDecode.scala 254:28] +endmodule +module PipelineRegister_5( + input clock, + input reset, + input io_write_enable, // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + input io_flush_enable, // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + input io_in, // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + output io_out // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; +`endif // RANDOMIZE_REG_INIT + reg reg_; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + assign io_out = reg_; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + always @(posedge clock) begin + if (reset) begin // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + reg_ <= 1'h0; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + end else if (io_write_enable) begin // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg_ <= io_in; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + end else if (io_flush_enable) begin // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg_ <= 1'h0; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + reg_ = _RAND_0[0:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module PipelineRegister_6( + input clock, + input reset, + input io_write_enable, // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + input io_flush_enable, // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + input [4:0] io_in, // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + output [4:0] io_out // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; +`endif // RANDOMIZE_REG_INIT + reg [4:0] reg_; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + assign io_out = reg_; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + always @(posedge clock) begin + if (reset) begin // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + reg_ <= 5'h0; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + end else if (io_write_enable) begin // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg_ <= io_in; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + end else if (io_flush_enable) begin // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg_ <= 5'h0; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + reg_ = _RAND_0[4:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module PipelineRegister_7( + input clock, + input reset, + input io_write_enable, // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + input io_flush_enable, // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + input [1:0] io_in, // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + output [1:0] io_out // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; +`endif // RANDOMIZE_REG_INIT + reg [1:0] reg_; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + assign io_out = reg_; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + always @(posedge clock) begin + if (reset) begin // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + reg_ <= 2'h0; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + end else if (io_write_enable) begin // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg_ <= io_in; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + end else if (io_flush_enable) begin // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg_ <= 2'h0; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + reg_ = _RAND_0[1:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module PipelineRegister_14( + input clock, + input reset, + input io_write_enable, // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + input io_flush_enable, // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + input [11:0] io_in, // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] + output [11:0] io_out // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 21:14] +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; +`endif // RANDOMIZE_REG_INIT + reg [11:0] reg_; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + assign io_out = reg_; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 34:10] + always @(posedge clock) begin + if (reset) begin // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + reg_ <= 12'h0; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 28:20] + end else if (io_write_enable) begin // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 29:25] + reg_ <= io_in; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 30:9] + end else if (io_flush_enable) begin // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 31:31] + reg_ <= 12'h0; // @[src/main/scala/riscv/core/fivestage/PipelineRegister.scala 32:9] + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + reg_ = _RAND_0[11:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module ID2EX( + input clock, + input reset, + input io_stall_flag, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + input io_flush_enable, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + input [31:0] io_instruction, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + input [31:0] io_instruction_address, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + input io_regs_write_enable, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + input [4:0] io_regs_write_address, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + input [1:0] io_regs_write_source, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + input [31:0] io_reg1_data, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + input [31:0] io_reg2_data, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + input [31:0] io_immediate, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + input io_aluop1_source, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + input io_aluop2_source, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + input io_csr_write_enable, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + input [11:0] io_csr_address, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + input io_memory_read_enable, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + input io_memory_write_enable, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + input [31:0] io_csr_read_data, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + output [31:0] io_output_instruction, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + output [31:0] io_output_instruction_address, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + output io_output_regs_write_enable, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + output [4:0] io_output_regs_write_address, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + output [1:0] io_output_regs_write_source, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + output [31:0] io_output_reg1_data, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + output [31:0] io_output_reg2_data, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + output [31:0] io_output_immediate, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + output io_output_aluop1_source, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + output io_output_aluop2_source, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + output io_output_csr_write_enable, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + output [11:0] io_output_csr_address, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + output io_output_memory_read_enable, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + output io_output_memory_write_enable, // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] + output [31:0] io_output_csr_read_data // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 21:14] +); + wire instruction_clock; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 58:27] + wire instruction_reset; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 58:27] + wire instruction_io_write_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 58:27] + wire instruction_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 58:27] + wire [31:0] instruction_io_in; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 58:27] + wire [31:0] instruction_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 58:27] + wire instruction_address_clock; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 64:35] + wire instruction_address_reset; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 64:35] + wire instruction_address_io_write_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 64:35] + wire instruction_address_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 64:35] + wire [31:0] instruction_address_io_in; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 64:35] + wire [31:0] instruction_address_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 64:35] + wire regs_write_enable_clock; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 70:33] + wire regs_write_enable_reset; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 70:33] + wire regs_write_enable_io_write_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 70:33] + wire regs_write_enable_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 70:33] + wire regs_write_enable_io_in; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 70:33] + wire regs_write_enable_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 70:33] + wire regs_write_address_clock; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 76:34] + wire regs_write_address_reset; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 76:34] + wire regs_write_address_io_write_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 76:34] + wire regs_write_address_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 76:34] + wire [4:0] regs_write_address_io_in; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 76:34] + wire [4:0] regs_write_address_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 76:34] + wire regs_write_source_clock; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 82:33] + wire regs_write_source_reset; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 82:33] + wire regs_write_source_io_write_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 82:33] + wire regs_write_source_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 82:33] + wire [1:0] regs_write_source_io_in; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 82:33] + wire [1:0] regs_write_source_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 82:33] + wire reg1_data_clock; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 88:25] + wire reg1_data_reset; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 88:25] + wire reg1_data_io_write_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 88:25] + wire reg1_data_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 88:25] + wire [31:0] reg1_data_io_in; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 88:25] + wire [31:0] reg1_data_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 88:25] + wire reg2_data_clock; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 94:25] + wire reg2_data_reset; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 94:25] + wire reg2_data_io_write_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 94:25] + wire reg2_data_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 94:25] + wire [31:0] reg2_data_io_in; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 94:25] + wire [31:0] reg2_data_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 94:25] + wire immediate_clock; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 100:25] + wire immediate_reset; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 100:25] + wire immediate_io_write_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 100:25] + wire immediate_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 100:25] + wire [31:0] immediate_io_in; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 100:25] + wire [31:0] immediate_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 100:25] + wire aluop1_source_clock; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 106:29] + wire aluop1_source_reset; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 106:29] + wire aluop1_source_io_write_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 106:29] + wire aluop1_source_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 106:29] + wire aluop1_source_io_in; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 106:29] + wire aluop1_source_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 106:29] + wire aluop2_source_clock; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 112:29] + wire aluop2_source_reset; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 112:29] + wire aluop2_source_io_write_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 112:29] + wire aluop2_source_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 112:29] + wire aluop2_source_io_in; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 112:29] + wire aluop2_source_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 112:29] + wire csr_write_enable_clock; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 118:32] + wire csr_write_enable_reset; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 118:32] + wire csr_write_enable_io_write_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 118:32] + wire csr_write_enable_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 118:32] + wire csr_write_enable_io_in; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 118:32] + wire csr_write_enable_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 118:32] + wire csr_address_clock; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 124:27] + wire csr_address_reset; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 124:27] + wire csr_address_io_write_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 124:27] + wire csr_address_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 124:27] + wire [11:0] csr_address_io_in; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 124:27] + wire [11:0] csr_address_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 124:27] + wire memory_read_enable_clock; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 130:34] + wire memory_read_enable_reset; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 130:34] + wire memory_read_enable_io_write_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 130:34] + wire memory_read_enable_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 130:34] + wire memory_read_enable_io_in; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 130:34] + wire memory_read_enable_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 130:34] + wire memory_write_enable_clock; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 136:35] + wire memory_write_enable_reset; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 136:35] + wire memory_write_enable_io_write_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 136:35] + wire memory_write_enable_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 136:35] + wire memory_write_enable_io_in; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 136:35] + wire memory_write_enable_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 136:35] + wire csr_read_data_clock; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 142:29] + wire csr_read_data_reset; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 142:29] + wire csr_read_data_io_write_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 142:29] + wire csr_read_data_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 142:29] + wire [31:0] csr_read_data_io_in; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 142:29] + wire [31:0] csr_read_data_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 142:29] + PipelineRegister instruction ( // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 58:27] + .clock(instruction_clock), + .reset(instruction_reset), + .io_write_enable(instruction_io_write_enable), + .io_flush_enable(instruction_io_flush_enable), + .io_in(instruction_io_in), + .io_out(instruction_io_out) + ); + PipelineRegister_1 instruction_address ( // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 64:35] + .clock(instruction_address_clock), + .reset(instruction_address_reset), + .io_write_enable(instruction_address_io_write_enable), + .io_flush_enable(instruction_address_io_flush_enable), + .io_in(instruction_address_io_in), + .io_out(instruction_address_io_out) + ); + PipelineRegister_5 regs_write_enable ( // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 70:33] + .clock(regs_write_enable_clock), + .reset(regs_write_enable_reset), + .io_write_enable(regs_write_enable_io_write_enable), + .io_flush_enable(regs_write_enable_io_flush_enable), + .io_in(regs_write_enable_io_in), + .io_out(regs_write_enable_io_out) + ); + PipelineRegister_6 regs_write_address ( // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 76:34] + .clock(regs_write_address_clock), + .reset(regs_write_address_reset), + .io_write_enable(regs_write_address_io_write_enable), + .io_flush_enable(regs_write_address_io_flush_enable), + .io_in(regs_write_address_io_in), + .io_out(regs_write_address_io_out) + ); + PipelineRegister_7 regs_write_source ( // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 82:33] + .clock(regs_write_source_clock), + .reset(regs_write_source_reset), + .io_write_enable(regs_write_source_io_write_enable), + .io_flush_enable(regs_write_source_io_flush_enable), + .io_in(regs_write_source_io_in), + .io_out(regs_write_source_io_out) + ); + PipelineRegister_2 reg1_data ( // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 88:25] + .clock(reg1_data_clock), + .reset(reg1_data_reset), + .io_write_enable(reg1_data_io_write_enable), + .io_flush_enable(reg1_data_io_flush_enable), + .io_in(reg1_data_io_in), + .io_out(reg1_data_io_out) + ); + PipelineRegister_2 reg2_data ( // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 94:25] + .clock(reg2_data_clock), + .reset(reg2_data_reset), + .io_write_enable(reg2_data_io_write_enable), + .io_flush_enable(reg2_data_io_flush_enable), + .io_in(reg2_data_io_in), + .io_out(reg2_data_io_out) + ); + PipelineRegister_2 immediate ( // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 100:25] + .clock(immediate_clock), + .reset(immediate_reset), + .io_write_enable(immediate_io_write_enable), + .io_flush_enable(immediate_io_flush_enable), + .io_in(immediate_io_in), + .io_out(immediate_io_out) + ); + PipelineRegister_5 aluop1_source ( // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 106:29] + .clock(aluop1_source_clock), + .reset(aluop1_source_reset), + .io_write_enable(aluop1_source_io_write_enable), + .io_flush_enable(aluop1_source_io_flush_enable), + .io_in(aluop1_source_io_in), + .io_out(aluop1_source_io_out) + ); + PipelineRegister_5 aluop2_source ( // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 112:29] + .clock(aluop2_source_clock), + .reset(aluop2_source_reset), + .io_write_enable(aluop2_source_io_write_enable), + .io_flush_enable(aluop2_source_io_flush_enable), + .io_in(aluop2_source_io_in), + .io_out(aluop2_source_io_out) + ); + PipelineRegister_5 csr_write_enable ( // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 118:32] + .clock(csr_write_enable_clock), + .reset(csr_write_enable_reset), + .io_write_enable(csr_write_enable_io_write_enable), + .io_flush_enable(csr_write_enable_io_flush_enable), + .io_in(csr_write_enable_io_in), + .io_out(csr_write_enable_io_out) + ); + PipelineRegister_14 csr_address ( // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 124:27] + .clock(csr_address_clock), + .reset(csr_address_reset), + .io_write_enable(csr_address_io_write_enable), + .io_flush_enable(csr_address_io_flush_enable), + .io_in(csr_address_io_in), + .io_out(csr_address_io_out) + ); + PipelineRegister_5 memory_read_enable ( // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 130:34] + .clock(memory_read_enable_clock), + .reset(memory_read_enable_reset), + .io_write_enable(memory_read_enable_io_write_enable), + .io_flush_enable(memory_read_enable_io_flush_enable), + .io_in(memory_read_enable_io_in), + .io_out(memory_read_enable_io_out) + ); + PipelineRegister_5 memory_write_enable ( // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 136:35] + .clock(memory_write_enable_clock), + .reset(memory_write_enable_reset), + .io_write_enable(memory_write_enable_io_write_enable), + .io_flush_enable(memory_write_enable_io_flush_enable), + .io_in(memory_write_enable_io_in), + .io_out(memory_write_enable_io_out) + ); + PipelineRegister_2 csr_read_data ( // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 142:29] + .clock(csr_read_data_clock), + .reset(csr_read_data_reset), + .io_write_enable(csr_read_data_io_write_enable), + .io_flush_enable(csr_read_data_io_flush_enable), + .io_in(csr_read_data_io_in), + .io_out(csr_read_data_io_out) + ); + assign io_output_instruction = instruction_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 62:25] + assign io_output_instruction_address = instruction_address_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 68:33] + assign io_output_regs_write_enable = regs_write_enable_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 74:31] + assign io_output_regs_write_address = regs_write_address_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 80:32] + assign io_output_regs_write_source = regs_write_source_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 86:31] + assign io_output_reg1_data = reg1_data_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 92:23] + assign io_output_reg2_data = reg2_data_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 98:23] + assign io_output_immediate = immediate_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 104:23] + assign io_output_aluop1_source = aluop1_source_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 110:27] + assign io_output_aluop2_source = aluop2_source_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 116:27] + assign io_output_csr_write_enable = csr_write_enable_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 122:30] + assign io_output_csr_address = csr_address_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 128:25] + assign io_output_memory_read_enable = memory_read_enable_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 134:32] + assign io_output_memory_write_enable = memory_write_enable_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 140:33] + assign io_output_csr_read_data = csr_read_data_io_out; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 146:27] + assign instruction_clock = clock; + assign instruction_reset = reset; + assign instruction_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 56:22] + assign instruction_io_flush_enable = io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 61:31] + assign instruction_io_in = io_instruction; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 59:21] + assign instruction_address_clock = clock; + assign instruction_address_reset = reset; + assign instruction_address_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 56:22] + assign instruction_address_io_flush_enable = io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 67:39] + assign instruction_address_io_in = io_instruction_address; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 65:29] + assign regs_write_enable_clock = clock; + assign regs_write_enable_reset = reset; + assign regs_write_enable_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 56:22] + assign regs_write_enable_io_flush_enable = io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 73:37] + assign regs_write_enable_io_in = io_regs_write_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 71:27] + assign regs_write_address_clock = clock; + assign regs_write_address_reset = reset; + assign regs_write_address_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 56:22] + assign regs_write_address_io_flush_enable = io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 79:38] + assign regs_write_address_io_in = io_regs_write_address; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 77:28] + assign regs_write_source_clock = clock; + assign regs_write_source_reset = reset; + assign regs_write_source_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 56:22] + assign regs_write_source_io_flush_enable = io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 85:37] + assign regs_write_source_io_in = io_regs_write_source; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 83:27] + assign reg1_data_clock = clock; + assign reg1_data_reset = reset; + assign reg1_data_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 56:22] + assign reg1_data_io_flush_enable = io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 91:29] + assign reg1_data_io_in = io_reg1_data; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 89:19] + assign reg2_data_clock = clock; + assign reg2_data_reset = reset; + assign reg2_data_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 56:22] + assign reg2_data_io_flush_enable = io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 97:29] + assign reg2_data_io_in = io_reg2_data; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 95:19] + assign immediate_clock = clock; + assign immediate_reset = reset; + assign immediate_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 56:22] + assign immediate_io_flush_enable = io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 103:29] + assign immediate_io_in = io_immediate; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 101:19] + assign aluop1_source_clock = clock; + assign aluop1_source_reset = reset; + assign aluop1_source_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 56:22] + assign aluop1_source_io_flush_enable = io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 109:33] + assign aluop1_source_io_in = io_aluop1_source; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 107:23] + assign aluop2_source_clock = clock; + assign aluop2_source_reset = reset; + assign aluop2_source_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 56:22] + assign aluop2_source_io_flush_enable = io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 115:33] + assign aluop2_source_io_in = io_aluop2_source; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 113:23] + assign csr_write_enable_clock = clock; + assign csr_write_enable_reset = reset; + assign csr_write_enable_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 56:22] + assign csr_write_enable_io_flush_enable = io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 121:36] + assign csr_write_enable_io_in = io_csr_write_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 119:26] + assign csr_address_clock = clock; + assign csr_address_reset = reset; + assign csr_address_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 56:22] + assign csr_address_io_flush_enable = io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 127:31] + assign csr_address_io_in = io_csr_address; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 125:21] + assign memory_read_enable_clock = clock; + assign memory_read_enable_reset = reset; + assign memory_read_enable_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 56:22] + assign memory_read_enable_io_flush_enable = io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 133:38] + assign memory_read_enable_io_in = io_memory_read_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 131:28] + assign memory_write_enable_clock = clock; + assign memory_write_enable_reset = reset; + assign memory_write_enable_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 56:22] + assign memory_write_enable_io_flush_enable = io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 139:39] + assign memory_write_enable_io_in = io_memory_write_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 137:29] + assign csr_read_data_clock = clock; + assign csr_read_data_reset = reset; + assign csr_read_data_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 56:22] + assign csr_read_data_io_flush_enable = io_flush_enable; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 145:33] + assign csr_read_data_io_in = io_csr_read_data; // @[src/main/scala/riscv/core/fivestage/ID2EX.scala 143:23] +endmodule +module ALU( + input [3:0] io_func, // @[src/main/scala/riscv/core/fivestage/ALU.scala 26:14] + input [31:0] io_op1, // @[src/main/scala/riscv/core/fivestage/ALU.scala 26:14] + input [31:0] io_op2, // @[src/main/scala/riscv/core/fivestage/ALU.scala 26:14] + output [31:0] io_result // @[src/main/scala/riscv/core/fivestage/ALU.scala 26:14] +); + wire [31:0] _io_result_T_1 = io_op1 + io_op2; // @[src/main/scala/riscv/core/fivestage/ALU.scala 38:27] + wire [31:0] _io_result_T_3 = io_op1 - io_op2; // @[src/main/scala/riscv/core/fivestage/ALU.scala 41:27] + wire [62:0] _GEN_10 = {{31'd0}, io_op1}; // @[src/main/scala/riscv/core/fivestage/ALU.scala 44:27] + wire [62:0] _io_result_T_5 = _GEN_10 << io_op2[4:0]; // @[src/main/scala/riscv/core/fivestage/ALU.scala 44:27] + wire [31:0] _io_result_T_6 = io_op1; // @[src/main/scala/riscv/core/fivestage/ALU.scala 47:27] + wire [31:0] _io_result_T_7 = io_op2; // @[src/main/scala/riscv/core/fivestage/ALU.scala 47:43] + wire [31:0] _io_result_T_9 = io_op1 ^ io_op2; // @[src/main/scala/riscv/core/fivestage/ALU.scala 50:27] + wire [31:0] _io_result_T_10 = io_op1 | io_op2; // @[src/main/scala/riscv/core/fivestage/ALU.scala 53:27] + wire [31:0] _io_result_T_11 = io_op1 & io_op2; // @[src/main/scala/riscv/core/fivestage/ALU.scala 56:27] + wire [31:0] _io_result_T_13 = io_op1 >> io_op2[4:0]; // @[src/main/scala/riscv/core/fivestage/ALU.scala 59:27] + wire [31:0] _io_result_T_17 = $signed(io_op1) >>> io_op2[4:0]; // @[src/main/scala/riscv/core/fivestage/ALU.scala 62:52] + wire _GEN_0 = 4'ha == io_func & io_op1 < io_op2; // @[src/main/scala/riscv/core/fivestage/ALU.scala 35:13 36:19 65:17] + wire [31:0] _GEN_1 = 4'h9 == io_func ? _io_result_T_17 : {{31'd0}, _GEN_0}; // @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19 62:17] + wire [31:0] _GEN_2 = 4'h8 == io_func ? _io_result_T_13 : _GEN_1; // @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19 59:17] + wire [31:0] _GEN_3 = 4'h7 == io_func ? _io_result_T_11 : _GEN_2; // @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19 56:17] + wire [31:0] _GEN_4 = 4'h6 == io_func ? _io_result_T_10 : _GEN_3; // @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19 53:17] + wire [31:0] _GEN_5 = 4'h5 == io_func ? _io_result_T_9 : _GEN_4; // @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19 50:17] + wire [31:0] _GEN_6 = 4'h4 == io_func ? {{31'd0}, $signed(_io_result_T_6) < $signed(_io_result_T_7)} : _GEN_5; // @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19 47:17] + wire [62:0] _GEN_7 = 4'h3 == io_func ? _io_result_T_5 : {{31'd0}, _GEN_6}; // @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19 44:17] + wire [62:0] _GEN_8 = 4'h2 == io_func ? {{31'd0}, _io_result_T_3} : _GEN_7; // @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19 41:17] + wire [62:0] _GEN_9 = 4'h1 == io_func ? {{31'd0}, _io_result_T_1} : _GEN_8; // @[src/main/scala/riscv/core/fivestage/ALU.scala 36:19 38:17] + assign io_result = _GEN_9[31:0]; +endmodule +module ALUControl( + input [6:0] io_opcode, // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 21:14] + input [2:0] io_funct3, // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 21:14] + input [6:0] io_funct7, // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 21:14] + output [3:0] io_alu_funct // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 21:14] +); + wire [3:0] _io_alu_funct_T_1 = io_funct7[5] ? 4'h9 : 4'h8; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 42:39] + wire _io_alu_funct_T_2 = 3'h1 == io_funct3; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + wire [1:0] _io_alu_funct_T_3 = 3'h1 == io_funct3 ? 2'h3 : 2'h1; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + wire _io_alu_funct_T_4 = 3'h2 == io_funct3; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + wire [2:0] _io_alu_funct_T_5 = 3'h2 == io_funct3 ? 3'h4 : {{1'd0}, _io_alu_funct_T_3}; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + wire _io_alu_funct_T_6 = 3'h3 == io_funct3; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + wire [3:0] _io_alu_funct_T_7 = 3'h3 == io_funct3 ? 4'ha : {{1'd0}, _io_alu_funct_T_5}; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + wire _io_alu_funct_T_8 = 3'h4 == io_funct3; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + wire [3:0] _io_alu_funct_T_9 = 3'h4 == io_funct3 ? 4'h5 : _io_alu_funct_T_7; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + wire _io_alu_funct_T_10 = 3'h6 == io_funct3; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + wire [3:0] _io_alu_funct_T_11 = 3'h6 == io_funct3 ? 4'h6 : _io_alu_funct_T_9; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + wire _io_alu_funct_T_12 = 3'h7 == io_funct3; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + wire [3:0] _io_alu_funct_T_13 = 3'h7 == io_funct3 ? 4'h7 : _io_alu_funct_T_11; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + wire _io_alu_funct_T_14 = 3'h5 == io_funct3; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + wire [3:0] _io_alu_funct_T_15 = 3'h5 == io_funct3 ? _io_alu_funct_T_1 : _io_alu_funct_T_13; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 33:62] + wire [1:0] _io_alu_funct_T_17 = io_funct7[5] ? 2'h2 : 2'h1; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 49:43] + wire [1:0] _io_alu_funct_T_21 = _io_alu_funct_T_2 ? 2'h3 : _io_alu_funct_T_17; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 47:62] + wire [2:0] _io_alu_funct_T_23 = _io_alu_funct_T_4 ? 3'h4 : {{1'd0}, _io_alu_funct_T_21}; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 47:62] + wire [3:0] _io_alu_funct_T_25 = _io_alu_funct_T_6 ? 4'ha : {{1'd0}, _io_alu_funct_T_23}; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 47:62] + wire [3:0] _io_alu_funct_T_27 = _io_alu_funct_T_8 ? 4'h5 : _io_alu_funct_T_25; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 47:62] + wire [3:0] _io_alu_funct_T_29 = _io_alu_funct_T_10 ? 4'h6 : _io_alu_funct_T_27; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 47:62] + wire [3:0] _io_alu_funct_T_31 = _io_alu_funct_T_12 ? 4'h7 : _io_alu_funct_T_29; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 47:62] + wire [3:0] _io_alu_funct_T_33 = _io_alu_funct_T_14 ? _io_alu_funct_T_1 : _io_alu_funct_T_31; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 47:62] + wire _GEN_1 = 7'h37 == io_opcode | 7'h17 == io_opcode; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 31:21 76:20] + wire _GEN_2 = 7'h67 == io_opcode | _GEN_1; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 31:21 73:20] + wire _GEN_3 = 7'h6f == io_opcode | _GEN_2; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 31:21 70:20] + wire _GEN_4 = 7'h23 == io_opcode | _GEN_3; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 31:21 67:20] + wire _GEN_5 = 7'h3 == io_opcode | _GEN_4; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 31:21 64:20] + wire _GEN_6 = 7'h63 == io_opcode | _GEN_5; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 31:21 61:20] + wire [3:0] _GEN_7 = 7'h33 == io_opcode ? _io_alu_funct_T_33 : {{3'd0}, _GEN_6}; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 31:21 47:20] + assign io_alu_funct = 7'h13 == io_opcode ? _io_alu_funct_T_15 : _GEN_7; // @[src/main/scala/riscv/core/fivestage/ALUControl.scala 31:21 33:20] +endmodule +module Execute( + input [31:0] io_instruction, // @[src/main/scala/riscv/core/fivestage/Execute.scala 26:14] + input [31:0] io_instruction_address, // @[src/main/scala/riscv/core/fivestage/Execute.scala 26:14] + input [31:0] io_reg1_data, // @[src/main/scala/riscv/core/fivestage/Execute.scala 26:14] + input [31:0] io_reg2_data, // @[src/main/scala/riscv/core/fivestage/Execute.scala 26:14] + input [31:0] io_immediate, // @[src/main/scala/riscv/core/fivestage/Execute.scala 26:14] + input io_aluop1_source, // @[src/main/scala/riscv/core/fivestage/Execute.scala 26:14] + input io_aluop2_source, // @[src/main/scala/riscv/core/fivestage/Execute.scala 26:14] + input [31:0] io_csr_read_data, // @[src/main/scala/riscv/core/fivestage/Execute.scala 26:14] + input [31:0] io_forward_from_mem, // @[src/main/scala/riscv/core/fivestage/Execute.scala 26:14] + input [31:0] io_forward_from_wb, // @[src/main/scala/riscv/core/fivestage/Execute.scala 26:14] + input [1:0] io_reg1_forward, // @[src/main/scala/riscv/core/fivestage/Execute.scala 26:14] + input [1:0] io_reg2_forward, // @[src/main/scala/riscv/core/fivestage/Execute.scala 26:14] + output [31:0] io_mem_alu_result, // @[src/main/scala/riscv/core/fivestage/Execute.scala 26:14] + output [31:0] io_csr_write_data // @[src/main/scala/riscv/core/fivestage/Execute.scala 26:14] +); + wire [3:0] alu_io_func; // @[src/main/scala/riscv/core/fivestage/Execute.scala 50:19] + wire [31:0] alu_io_op1; // @[src/main/scala/riscv/core/fivestage/Execute.scala 50:19] + wire [31:0] alu_io_op2; // @[src/main/scala/riscv/core/fivestage/Execute.scala 50:19] + wire [31:0] alu_io_result; // @[src/main/scala/riscv/core/fivestage/Execute.scala 50:19] + wire [6:0] alu_ctrl_io_opcode; // @[src/main/scala/riscv/core/fivestage/Execute.scala 51:24] + wire [2:0] alu_ctrl_io_funct3; // @[src/main/scala/riscv/core/fivestage/Execute.scala 51:24] + wire [6:0] alu_ctrl_io_funct7; // @[src/main/scala/riscv/core/fivestage/Execute.scala 51:24] + wire [3:0] alu_ctrl_io_alu_funct; // @[src/main/scala/riscv/core/fivestage/Execute.scala 51:24] + wire [2:0] funct3 = io_instruction[14:12]; // @[src/main/scala/riscv/core/fivestage/Execute.scala 45:30] + wire [4:0] uimm = io_instruction[19:15]; // @[src/main/scala/riscv/core/fivestage/Execute.scala 48:28] + wire [31:0] _alu_io_op1_T_2 = 2'h1 == io_reg1_forward ? io_forward_from_mem : io_reg1_data; // @[src/main/scala/riscv/core/fivestage/Execute.scala 60:45] + wire [31:0] _alu_io_op1_T_4 = 2'h2 == io_reg1_forward ? io_forward_from_wb : _alu_io_op1_T_2; // @[src/main/scala/riscv/core/fivestage/Execute.scala 60:45] + wire [31:0] _alu_io_op2_T_2 = 2'h1 == io_reg2_forward ? io_forward_from_mem : io_reg2_data; // @[src/main/scala/riscv/core/fivestage/Execute.scala 70:45] + wire [31:0] _alu_io_op2_T_4 = 2'h2 == io_reg2_forward ? io_forward_from_wb : _alu_io_op2_T_2; // @[src/main/scala/riscv/core/fivestage/Execute.scala 70:45] + wire [31:0] _io_csr_write_data_T = ~io_reg1_data; // @[src/main/scala/riscv/core/fivestage/Execute.scala 80:54] + wire [31:0] _io_csr_write_data_T_1 = io_csr_read_data & _io_csr_write_data_T; // @[src/main/scala/riscv/core/fivestage/Execute.scala 80:52] + wire [31:0] _io_csr_write_data_T_2 = io_csr_read_data | io_reg1_data; // @[src/main/scala/riscv/core/fivestage/Execute.scala 81:52] + wire [31:0] _io_csr_write_data_T_3 = {27'h0,uimm}; // @[src/main/scala/riscv/core/fivestage/Execute.scala 82:38] + wire [31:0] _io_csr_write_data_T_5 = ~_io_csr_write_data_T_3; // @[src/main/scala/riscv/core/fivestage/Execute.scala 83:55] + wire [31:0] _io_csr_write_data_T_6 = io_csr_read_data & _io_csr_write_data_T_5; // @[src/main/scala/riscv/core/fivestage/Execute.scala 83:53] + wire [31:0] _io_csr_write_data_T_8 = io_csr_read_data | _io_csr_write_data_T_3; // @[src/main/scala/riscv/core/fivestage/Execute.scala 84:53] + wire [31:0] _io_csr_write_data_T_10 = 3'h1 == funct3 ? io_reg1_data : 32'h0; // @[src/main/scala/riscv/core/fivestage/Execute.scala 78:46] + wire [31:0] _io_csr_write_data_T_12 = 3'h3 == funct3 ? _io_csr_write_data_T_1 : _io_csr_write_data_T_10; // @[src/main/scala/riscv/core/fivestage/Execute.scala 78:46] + wire [31:0] _io_csr_write_data_T_14 = 3'h2 == funct3 ? _io_csr_write_data_T_2 : _io_csr_write_data_T_12; // @[src/main/scala/riscv/core/fivestage/Execute.scala 78:46] + wire [31:0] _io_csr_write_data_T_16 = 3'h5 == funct3 ? _io_csr_write_data_T_3 : _io_csr_write_data_T_14; // @[src/main/scala/riscv/core/fivestage/Execute.scala 78:46] + wire [31:0] _io_csr_write_data_T_18 = 3'h7 == funct3 ? _io_csr_write_data_T_6 : _io_csr_write_data_T_16; // @[src/main/scala/riscv/core/fivestage/Execute.scala 78:46] + ALU alu ( // @[src/main/scala/riscv/core/fivestage/Execute.scala 50:19] + .io_func(alu_io_func), + .io_op1(alu_io_op1), + .io_op2(alu_io_op2), + .io_result(alu_io_result) + ); + ALUControl alu_ctrl ( // @[src/main/scala/riscv/core/fivestage/Execute.scala 51:24] + .io_opcode(alu_ctrl_io_opcode), + .io_funct3(alu_ctrl_io_funct3), + .io_funct7(alu_ctrl_io_funct7), + .io_alu_funct(alu_ctrl_io_alu_funct) + ); + assign io_mem_alu_result = alu_io_result; // @[src/main/scala/riscv/core/fivestage/Execute.scala 77:21] + assign io_csr_write_data = 3'h6 == funct3 ? _io_csr_write_data_T_8 : _io_csr_write_data_T_18; // @[src/main/scala/riscv/core/fivestage/Execute.scala 78:46] + assign alu_io_func = alu_ctrl_io_alu_funct; // @[src/main/scala/riscv/core/fivestage/Execute.scala 56:15] + assign alu_io_op1 = io_aluop1_source ? io_instruction_address : _alu_io_op1_T_4; // @[src/main/scala/riscv/core/fivestage/Execute.scala 57:20] + assign alu_io_op2 = io_aluop2_source ? io_immediate : _alu_io_op2_T_4; // @[src/main/scala/riscv/core/fivestage/Execute.scala 67:20] + assign alu_ctrl_io_opcode = io_instruction[6:0]; // @[src/main/scala/riscv/core/fivestage/Execute.scala 44:30] + assign alu_ctrl_io_funct3 = io_instruction[14:12]; // @[src/main/scala/riscv/core/fivestage/Execute.scala 45:30] + assign alu_ctrl_io_funct7 = io_instruction[31:25]; // @[src/main/scala/riscv/core/fivestage/Execute.scala 46:30] +endmodule +module EX2MEM( + input clock, + input reset, + input io_stall_flag, // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 21:14] + input io_regs_write_enable, // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 21:14] + input [1:0] io_regs_write_source, // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 21:14] + input [31:0] io_regs_write_address, // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 21:14] + input [31:0] io_instruction_address, // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 21:14] + input [31:0] io_instruction, // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 21:14] + input [31:0] io_reg1_data, // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 21:14] + input [31:0] io_reg2_data, // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 21:14] + input io_memory_read_enable, // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 21:14] + input io_memory_write_enable, // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 21:14] + input [31:0] io_alu_result, // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 21:14] + input [31:0] io_csr_read_data, // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 21:14] + output io_output_regs_write_enable, // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 21:14] + output [1:0] io_output_regs_write_source, // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 21:14] + output [31:0] io_output_regs_write_address, // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 21:14] + output [31:0] io_output_instruction_address, // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 21:14] + output [31:0] io_output_instruction, // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 21:14] + output [31:0] io_output_reg2_data, // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 21:14] + output io_output_memory_read_enable, // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 21:14] + output io_output_memory_write_enable, // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 21:14] + output [31:0] io_output_alu_result, // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 21:14] + output [31:0] io_output_csr_read_data // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 21:14] +); + wire regs_write_enable_clock; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 50:33] + wire regs_write_enable_reset; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 50:33] + wire regs_write_enable_io_write_enable; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 50:33] + wire regs_write_enable_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 50:33] + wire regs_write_enable_io_in; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 50:33] + wire regs_write_enable_io_out; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 50:33] + wire regs_write_source_clock; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 56:33] + wire regs_write_source_reset; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 56:33] + wire regs_write_source_io_write_enable; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 56:33] + wire regs_write_source_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 56:33] + wire [1:0] regs_write_source_io_in; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 56:33] + wire [1:0] regs_write_source_io_out; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 56:33] + wire regs_write_address_clock; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 62:34] + wire regs_write_address_reset; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 62:34] + wire regs_write_address_io_write_enable; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 62:34] + wire regs_write_address_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 62:34] + wire [4:0] regs_write_address_io_in; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 62:34] + wire [4:0] regs_write_address_io_out; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 62:34] + wire instruction_address_clock; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 68:35] + wire instruction_address_reset; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 68:35] + wire instruction_address_io_write_enable; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 68:35] + wire instruction_address_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 68:35] + wire [31:0] instruction_address_io_in; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 68:35] + wire [31:0] instruction_address_io_out; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 68:35] + wire instruction_clock; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 74:27] + wire instruction_reset; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 74:27] + wire instruction_io_write_enable; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 74:27] + wire instruction_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 74:27] + wire [31:0] instruction_io_in; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 74:27] + wire [31:0] instruction_io_out; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 74:27] + wire reg1_data_clock; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 80:25] + wire reg1_data_reset; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 80:25] + wire reg1_data_io_write_enable; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 80:25] + wire reg1_data_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 80:25] + wire [31:0] reg1_data_io_in; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 80:25] + wire [31:0] reg1_data_io_out; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 80:25] + wire reg2_data_clock; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 86:25] + wire reg2_data_reset; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 86:25] + wire reg2_data_io_write_enable; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 86:25] + wire reg2_data_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 86:25] + wire [31:0] reg2_data_io_in; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 86:25] + wire [31:0] reg2_data_io_out; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 86:25] + wire alu_result_clock; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 92:26] + wire alu_result_reset; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 92:26] + wire alu_result_io_write_enable; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 92:26] + wire alu_result_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 92:26] + wire [31:0] alu_result_io_in; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 92:26] + wire [31:0] alu_result_io_out; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 92:26] + wire memory_read_enable_clock; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 98:34] + wire memory_read_enable_reset; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 98:34] + wire memory_read_enable_io_write_enable; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 98:34] + wire memory_read_enable_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 98:34] + wire memory_read_enable_io_in; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 98:34] + wire memory_read_enable_io_out; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 98:34] + wire memory_write_enable_clock; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 104:35] + wire memory_write_enable_reset; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 104:35] + wire memory_write_enable_io_write_enable; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 104:35] + wire memory_write_enable_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 104:35] + wire memory_write_enable_io_in; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 104:35] + wire memory_write_enable_io_out; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 104:35] + wire csr_read_data_clock; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 110:29] + wire csr_read_data_reset; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 110:29] + wire csr_read_data_io_write_enable; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 110:29] + wire csr_read_data_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 110:29] + wire [31:0] csr_read_data_io_in; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 110:29] + wire [31:0] csr_read_data_io_out; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 110:29] + PipelineRegister_5 regs_write_enable ( // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 50:33] + .clock(regs_write_enable_clock), + .reset(regs_write_enable_reset), + .io_write_enable(regs_write_enable_io_write_enable), + .io_flush_enable(regs_write_enable_io_flush_enable), + .io_in(regs_write_enable_io_in), + .io_out(regs_write_enable_io_out) + ); + PipelineRegister_7 regs_write_source ( // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 56:33] + .clock(regs_write_source_clock), + .reset(regs_write_source_reset), + .io_write_enable(regs_write_source_io_write_enable), + .io_flush_enable(regs_write_source_io_flush_enable), + .io_in(regs_write_source_io_in), + .io_out(regs_write_source_io_out) + ); + PipelineRegister_6 regs_write_address ( // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 62:34] + .clock(regs_write_address_clock), + .reset(regs_write_address_reset), + .io_write_enable(regs_write_address_io_write_enable), + .io_flush_enable(regs_write_address_io_flush_enable), + .io_in(regs_write_address_io_in), + .io_out(regs_write_address_io_out) + ); + PipelineRegister_2 instruction_address ( // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 68:35] + .clock(instruction_address_clock), + .reset(instruction_address_reset), + .io_write_enable(instruction_address_io_write_enable), + .io_flush_enable(instruction_address_io_flush_enable), + .io_in(instruction_address_io_in), + .io_out(instruction_address_io_out) + ); + PipelineRegister_2 instruction ( // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 74:27] + .clock(instruction_clock), + .reset(instruction_reset), + .io_write_enable(instruction_io_write_enable), + .io_flush_enable(instruction_io_flush_enable), + .io_in(instruction_io_in), + .io_out(instruction_io_out) + ); + PipelineRegister_2 reg1_data ( // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 80:25] + .clock(reg1_data_clock), + .reset(reg1_data_reset), + .io_write_enable(reg1_data_io_write_enable), + .io_flush_enable(reg1_data_io_flush_enable), + .io_in(reg1_data_io_in), + .io_out(reg1_data_io_out) + ); + PipelineRegister_2 reg2_data ( // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 86:25] + .clock(reg2_data_clock), + .reset(reg2_data_reset), + .io_write_enable(reg2_data_io_write_enable), + .io_flush_enable(reg2_data_io_flush_enable), + .io_in(reg2_data_io_in), + .io_out(reg2_data_io_out) + ); + PipelineRegister_2 alu_result ( // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 92:26] + .clock(alu_result_clock), + .reset(alu_result_reset), + .io_write_enable(alu_result_io_write_enable), + .io_flush_enable(alu_result_io_flush_enable), + .io_in(alu_result_io_in), + .io_out(alu_result_io_out) + ); + PipelineRegister_5 memory_read_enable ( // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 98:34] + .clock(memory_read_enable_clock), + .reset(memory_read_enable_reset), + .io_write_enable(memory_read_enable_io_write_enable), + .io_flush_enable(memory_read_enable_io_flush_enable), + .io_in(memory_read_enable_io_in), + .io_out(memory_read_enable_io_out) + ); + PipelineRegister_5 memory_write_enable ( // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 104:35] + .clock(memory_write_enable_clock), + .reset(memory_write_enable_reset), + .io_write_enable(memory_write_enable_io_write_enable), + .io_flush_enable(memory_write_enable_io_flush_enable), + .io_in(memory_write_enable_io_in), + .io_out(memory_write_enable_io_out) + ); + PipelineRegister_2 csr_read_data ( // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 110:29] + .clock(csr_read_data_clock), + .reset(csr_read_data_reset), + .io_write_enable(csr_read_data_io_write_enable), + .io_flush_enable(csr_read_data_io_flush_enable), + .io_in(csr_read_data_io_in), + .io_out(csr_read_data_io_out) + ); + assign io_output_regs_write_enable = regs_write_enable_io_out; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 54:31] + assign io_output_regs_write_source = regs_write_source_io_out; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 60:31] + assign io_output_regs_write_address = {{27'd0}, regs_write_address_io_out}; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 66:32] + assign io_output_instruction_address = instruction_address_io_out; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 72:33] + assign io_output_instruction = instruction_io_out; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 78:25] + assign io_output_reg2_data = reg2_data_io_out; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 90:23] + assign io_output_memory_read_enable = memory_read_enable_io_out; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 102:32] + assign io_output_memory_write_enable = memory_write_enable_io_out; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 108:33] + assign io_output_alu_result = alu_result_io_out; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 96:24] + assign io_output_csr_read_data = csr_read_data_io_out; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 114:27] + assign regs_write_enable_clock = clock; + assign regs_write_enable_reset = reset; + assign regs_write_enable_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 48:22] + assign regs_write_enable_io_flush_enable = 1'h0; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 53:37] + assign regs_write_enable_io_in = io_regs_write_enable; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 51:27] + assign regs_write_source_clock = clock; + assign regs_write_source_reset = reset; + assign regs_write_source_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 48:22] + assign regs_write_source_io_flush_enable = 1'h0; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 59:37] + assign regs_write_source_io_in = io_regs_write_source; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 57:27] + assign regs_write_address_clock = clock; + assign regs_write_address_reset = reset; + assign regs_write_address_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 48:22] + assign regs_write_address_io_flush_enable = 1'h0; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 65:38] + assign regs_write_address_io_in = io_regs_write_address[4:0]; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 63:28] + assign instruction_address_clock = clock; + assign instruction_address_reset = reset; + assign instruction_address_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 48:22] + assign instruction_address_io_flush_enable = 1'h0; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 71:39] + assign instruction_address_io_in = io_instruction_address; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 69:29] + assign instruction_clock = clock; + assign instruction_reset = reset; + assign instruction_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 48:22] + assign instruction_io_flush_enable = 1'h0; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 77:31] + assign instruction_io_in = io_instruction; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 75:21] + assign reg1_data_clock = clock; + assign reg1_data_reset = reset; + assign reg1_data_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 48:22] + assign reg1_data_io_flush_enable = 1'h0; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 83:29] + assign reg1_data_io_in = io_reg1_data; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 81:19] + assign reg2_data_clock = clock; + assign reg2_data_reset = reset; + assign reg2_data_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 48:22] + assign reg2_data_io_flush_enable = 1'h0; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 89:29] + assign reg2_data_io_in = io_reg2_data; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 87:19] + assign alu_result_clock = clock; + assign alu_result_reset = reset; + assign alu_result_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 48:22] + assign alu_result_io_flush_enable = 1'h0; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 95:30] + assign alu_result_io_in = io_alu_result; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 93:20] + assign memory_read_enable_clock = clock; + assign memory_read_enable_reset = reset; + assign memory_read_enable_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 48:22] + assign memory_read_enable_io_flush_enable = 1'h0; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 101:38] + assign memory_read_enable_io_in = io_memory_read_enable; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 99:28] + assign memory_write_enable_clock = clock; + assign memory_write_enable_reset = reset; + assign memory_write_enable_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 48:22] + assign memory_write_enable_io_flush_enable = 1'h0; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 107:39] + assign memory_write_enable_io_in = io_memory_write_enable; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 105:29] + assign csr_read_data_clock = clock; + assign csr_read_data_reset = reset; + assign csr_read_data_io_write_enable = ~io_stall_flag; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 48:22] + assign csr_read_data_io_flush_enable = 1'h0; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 113:33] + assign csr_read_data_io_in = io_csr_read_data; // @[src/main/scala/riscv/core/fivestage/EX2MEM.scala 111:23] +endmodule +module MemoryAccess( + input clock, + input reset, + input [31:0] io_alu_result, // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 23:14] + input [31:0] io_reg2_data, // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 23:14] + input io_memory_read_enable, // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 23:14] + input io_memory_write_enable, // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 23:14] + input [2:0] io_funct3, // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 23:14] + input [1:0] io_regs_write_source, // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 23:14] + input [31:0] io_csr_read_data, // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 23:14] + input io_clint_exception_token, // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 23:14] + output [31:0] io_wb_memory_read_data, // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 23:14] + output io_ctrl_stall_flag, // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 23:14] + output [31:0] io_forward_data, // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 23:14] + input [31:0] io_physical_address, // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 23:14] + output io_bus_read, // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 23:14] + output [31:0] io_bus_address, // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 23:14] + input [31:0] io_bus_read_data, // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 23:14] + input io_bus_read_valid, // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 23:14] + output io_bus_write, // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 23:14] + output [31:0] io_bus_write_data, // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 23:14] + output io_bus_write_strobe_0, // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 23:14] + output io_bus_write_strobe_1, // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 23:14] + output io_bus_write_strobe_2, // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 23:14] + output io_bus_write_strobe_3, // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 23:14] + input io_bus_write_valid, // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 23:14] + output io_bus_request, // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 23:14] + input io_bus_granted // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 23:14] +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; +`endif // RANDOMIZE_REG_INIT + wire [1:0] mem_address_index = io_physical_address[1:0]; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 41:46] + reg [1:0] mem_access_state; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 42:33] + wire _T = mem_access_state == 2'h0; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 62:27] + wire [1:0] _GEN_2 = io_bus_granted ? 2'h1 : mem_access_state; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 67:28 70:26 42:33] + wire _T_1 = mem_access_state == 2'h1; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 72:33] + wire [23:0] _io_wb_memory_read_data_T_2 = io_bus_read_data[31] ? 24'hffffff : 24'h0; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 80:74] + wire [31:0] _io_wb_memory_read_data_T_4 = {_io_wb_memory_read_data_T_2,io_bus_read_data[31:24]}; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 80:69] + wire [23:0] _io_wb_memory_read_data_T_7 = io_bus_read_data[7] ? 24'hffffff : 24'h0; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 82:32] + wire [31:0] _io_wb_memory_read_data_T_9 = {_io_wb_memory_read_data_T_7,io_bus_read_data[7:0]}; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 82:27] + wire [23:0] _io_wb_memory_read_data_T_12 = io_bus_read_data[15] ? 24'hffffff : 24'h0; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 83:32] + wire [31:0] _io_wb_memory_read_data_T_14 = {_io_wb_memory_read_data_T_12,io_bus_read_data[15:8]}; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 83:27] + wire [23:0] _io_wb_memory_read_data_T_17 = io_bus_read_data[23] ? 24'hffffff : 24'h0; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 84:32] + wire [31:0] _io_wb_memory_read_data_T_19 = {_io_wb_memory_read_data_T_17,io_bus_read_data[23:16]}; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 84:27] + wire _io_wb_memory_read_data_T_20 = 2'h0 == mem_address_index; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 80:104] + wire [31:0] _io_wb_memory_read_data_T_21 = 2'h0 == mem_address_index ? _io_wb_memory_read_data_T_9 : + _io_wb_memory_read_data_T_4; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 80:104] + wire _io_wb_memory_read_data_T_22 = 2'h1 == mem_address_index; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 80:104] + wire [31:0] _io_wb_memory_read_data_T_23 = 2'h1 == mem_address_index ? _io_wb_memory_read_data_T_14 : + _io_wb_memory_read_data_T_21; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 80:104] + wire _io_wb_memory_read_data_T_24 = 2'h2 == mem_address_index; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 80:104] + wire [31:0] _io_wb_memory_read_data_T_25 = 2'h2 == mem_address_index ? _io_wb_memory_read_data_T_19 : + _io_wb_memory_read_data_T_23; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 80:104] + wire [31:0] _io_wb_memory_read_data_T_28 = {24'h0,io_bus_read_data[31:24]}; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 87:70] + wire [31:0] _io_wb_memory_read_data_T_31 = {24'h0,io_bus_read_data[7:0]}; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 89:27] + wire [31:0] _io_wb_memory_read_data_T_34 = {24'h0,io_bus_read_data[15:8]}; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 90:27] + wire [31:0] _io_wb_memory_read_data_T_37 = {24'h0,io_bus_read_data[23:16]}; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 91:27] + wire [31:0] _io_wb_memory_read_data_T_39 = _io_wb_memory_read_data_T_20 ? _io_wb_memory_read_data_T_31 : + _io_wb_memory_read_data_T_28; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 87:100] + wire [31:0] _io_wb_memory_read_data_T_41 = _io_wb_memory_read_data_T_22 ? _io_wb_memory_read_data_T_34 : + _io_wb_memory_read_data_T_39; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 87:100] + wire [31:0] _io_wb_memory_read_data_T_43 = _io_wb_memory_read_data_T_24 ? _io_wb_memory_read_data_T_37 : + _io_wb_memory_read_data_T_41; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 87:100] + wire _io_wb_memory_read_data_T_44 = mem_address_index == 2'h0; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 95:33] + wire [15:0] _io_wb_memory_read_data_T_47 = io_bus_read_data[15] ? 16'hffff : 16'h0; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 96:23] + wire [31:0] _io_wb_memory_read_data_T_49 = {_io_wb_memory_read_data_T_47,io_bus_read_data[15:0]}; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 96:18] + wire [15:0] _io_wb_memory_read_data_T_52 = io_bus_read_data[31] ? 16'hffff : 16'h0; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 97:23] + wire [31:0] _io_wb_memory_read_data_T_54 = {_io_wb_memory_read_data_T_52,io_bus_read_data[31:16]}; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 97:18] + wire [31:0] _io_wb_memory_read_data_T_55 = _io_wb_memory_read_data_T_44 ? _io_wb_memory_read_data_T_49 : + _io_wb_memory_read_data_T_54; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 94:40] + wire [31:0] _io_wb_memory_read_data_T_59 = {16'h0,io_bus_read_data[15:0]}; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 101:18] + wire [31:0] _io_wb_memory_read_data_T_62 = {16'h0,io_bus_read_data[31:16]}; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 102:18] + wire [31:0] _io_wb_memory_read_data_T_63 = _io_wb_memory_read_data_T_44 ? _io_wb_memory_read_data_T_59 : + _io_wb_memory_read_data_T_62; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 99:41] + wire [31:0] _io_wb_memory_read_data_T_65 = 3'h0 == io_funct3 ? _io_wb_memory_read_data_T_25 : 32'h0; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 78:60] + wire [31:0] _io_wb_memory_read_data_T_67 = 3'h4 == io_funct3 ? _io_wb_memory_read_data_T_43 : + _io_wb_memory_read_data_T_65; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 78:60] + wire [31:0] _io_wb_memory_read_data_T_69 = 3'h1 == io_funct3 ? _io_wb_memory_read_data_T_55 : + _io_wb_memory_read_data_T_67; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 78:60] + wire [31:0] _io_wb_memory_read_data_T_71 = 3'h5 == io_funct3 ? _io_wb_memory_read_data_T_63 : + _io_wb_memory_read_data_T_69; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 78:60] + wire [31:0] _io_wb_memory_read_data_T_73 = 3'h2 == io_funct3 ? io_bus_read_data : _io_wb_memory_read_data_T_71; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 78:60] + wire [31:0] _GEN_3 = io_bus_read_valid ? _io_wb_memory_read_data_T_73 : 32'h0; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 55:26 76:31 78:32] + wire [1:0] _GEN_4 = io_bus_read_valid ? 2'h0 : mem_access_state; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 45:22 76:31 42:33] + wire _GEN_5 = io_bus_read_valid ? 1'h0 : 1'h1; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 46:24 75:26 76:31] + wire _GEN_8 = mem_access_state == 2'h1 & _GEN_5; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 56:22 72:62] + wire [31:0] _GEN_9 = mem_access_state == 2'h1 ? _GEN_3 : 32'h0; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 55:26 72:62] + wire [1:0] _GEN_10 = mem_access_state == 2'h1 ? _GEN_4 : mem_access_state; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 42:33 72:62] + wire _GEN_11 = mem_access_state == 2'h0 | _GEN_8; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 62:56 64:26] + wire _GEN_13 = mem_access_state == 2'h0 | _T_1; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 62:56 66:22] + wire [31:0] _GEN_16 = mem_access_state == 2'h0 ? 32'h0 : _GEN_9; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 55:26 62:56] + wire _GEN_20 = 2'h3 == mem_address_index; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 115:27 117:{48,48}] + wire [4:0] _io_bus_write_data_T_1 = {mem_address_index, 3'h0}; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 118:89] + wire [39:0] _GEN_0 = {{31'd0}, io_reg2_data[8:0]}; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 118:67] + wire [39:0] _io_bus_write_data_T_2 = _GEN_0 << _io_bus_write_data_T_1; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 118:67] + wire [32:0] _io_bus_write_data_T_5 = {io_reg2_data[16:0], 16'h0}; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 130:95] + wire [32:0] _GEN_23 = _io_wb_memory_read_data_T_44 ? {{16'd0}, io_reg2_data[16:0]} : _io_bus_write_data_T_5; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 121:41 125:29 130:29] + wire _GEN_24 = _io_wb_memory_read_data_T_44 ? 1'h0 : 1'h1; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 115:27 121:41 128:36] + wire _T_6 = io_funct3 == 3'h2; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 133:28] + wire _GEN_30 = io_funct3 == 3'h1 ? _io_wb_memory_read_data_T_44 : _T_6; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 120:54] + wire [32:0] _GEN_32 = io_funct3 == 3'h1 ? _GEN_23 : {{1'd0}, io_reg2_data}; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 114:25 120:54] + wire _GEN_33 = io_funct3 == 3'h1 ? _GEN_24 : _T_6; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 120:54] + wire _GEN_35 = io_funct3 == 3'h0 ? _io_wb_memory_read_data_T_20 : _GEN_30; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 116:48] + wire _GEN_36 = io_funct3 == 3'h0 ? _io_wb_memory_read_data_T_22 : _GEN_30; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 116:48] + wire _GEN_37 = io_funct3 == 3'h0 ? _io_wb_memory_read_data_T_24 : _GEN_33; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 116:48] + wire _GEN_38 = io_funct3 == 3'h0 ? _GEN_20 : _GEN_33; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 116:48] + wire [39:0] _GEN_39 = io_funct3 == 3'h0 ? _io_bus_write_data_T_2 : {{7'd0}, _GEN_32}; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 116:48 118:27] + wire [1:0] _GEN_41 = io_bus_granted ? 2'h2 : mem_access_state; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 139:28 141:26 42:33] + wire _T_7 = mem_access_state == 2'h2; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 143:33] + wire [1:0] _GEN_42 = io_bus_write_valid ? 2'h0 : mem_access_state; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 147:32 45:22 42:33] + wire _GEN_43 = io_bus_write_valid ? 1'h0 : 1'h1; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 147:32 46:24 145:26] + wire _GEN_45 = mem_access_state == 2'h2 & _GEN_43; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 143:63 56:22] + wire [1:0] _GEN_47 = mem_access_state == 2'h2 ? _GEN_42 : mem_access_state; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 143:63 42:33] + wire _GEN_48 = _T | _GEN_45; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 111:56 113:26] + wire [39:0] _GEN_49 = _T ? _GEN_39 : 40'h0; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 111:56 52:21] + wire _GEN_50 = _T & _GEN_35; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 111:56 53:23] + wire _GEN_51 = _T & _GEN_36; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 111:56 53:23] + wire _GEN_52 = _T & _GEN_37; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 111:56 53:23] + wire _GEN_53 = _T & _GEN_38; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 111:56 53:23] + wire _GEN_54 = _T | _T_7; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 111:56 138:22] + wire _GEN_55 = _T & io_bus_granted; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 111:56] + wire [1:0] _GEN_56 = _T ? _GEN_41 : _GEN_47; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 111:56] + wire _GEN_57 = io_memory_write_enable & _GEN_48; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 110:38 56:22] + wire [39:0] _GEN_58 = io_memory_write_enable ? _GEN_49 : 40'h0; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 110:38 52:21] + wire _GEN_59 = io_memory_write_enable & _GEN_50; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 110:38 53:23] + wire _GEN_60 = io_memory_write_enable & _GEN_51; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 110:38 53:23] + wire _GEN_61 = io_memory_write_enable & _GEN_52; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 110:38 53:23] + wire _GEN_62 = io_memory_write_enable & _GEN_53; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 110:38 53:23] + wire _GEN_63 = io_memory_write_enable & _GEN_54; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 110:38 49:18] + wire _GEN_64 = io_memory_write_enable & _GEN_55; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 110:38 54:16] + wire _GEN_66 = io_memory_read_enable ? _GEN_11 : _GEN_57; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 61:37] + wire _GEN_67 = io_memory_read_enable & _T; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 50:15 61:37] + wire _GEN_68 = io_memory_read_enable ? _GEN_13 : _GEN_63; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 61:37] + wire [31:0] _GEN_71 = io_memory_read_enable ? _GEN_16 : 32'h0; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 55:26 61:37] + wire [39:0] _GEN_72 = io_memory_read_enable ? 40'h0 : _GEN_58; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 52:21 61:37] + wire _GEN_73 = io_memory_read_enable ? 1'h0 : _GEN_59; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 53:23 61:37] + wire _GEN_74 = io_memory_read_enable ? 1'h0 : _GEN_60; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 53:23 61:37] + wire _GEN_75 = io_memory_read_enable ? 1'h0 : _GEN_61; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 53:23 61:37] + wire _GEN_76 = io_memory_read_enable ? 1'h0 : _GEN_62; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 53:23 61:37] + wire _GEN_77 = io_memory_read_enable ? 1'h0 : _GEN_64; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 54:16 61:37] + wire [39:0] _GEN_84 = io_clint_exception_token ? 40'h0 : _GEN_72; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 52:21 58:34] + assign io_wb_memory_read_data = io_clint_exception_token ? 32'h0 : _GEN_71; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 55:26 58:34] + assign io_ctrl_stall_flag = io_clint_exception_token ? 1'h0 : _GEN_66; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 58:34 60:24] + assign io_forward_data = io_regs_write_source == 2'h2 ? io_csr_read_data : io_alu_result; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 153:25] + assign io_bus_read = io_clint_exception_token ? 1'h0 : _GEN_67; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 50:15 58:34] + assign io_bus_address = io_physical_address; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 51:18 58:34] + assign io_bus_write = io_clint_exception_token ? 1'h0 : _GEN_77; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 54:16 58:34] + assign io_bus_write_data = _GEN_84[31:0]; + assign io_bus_write_strobe_0 = io_clint_exception_token ? 1'h0 : _GEN_73; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 53:23 58:34] + assign io_bus_write_strobe_1 = io_clint_exception_token ? 1'h0 : _GEN_74; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 53:23 58:34] + assign io_bus_write_strobe_2 = io_clint_exception_token ? 1'h0 : _GEN_75; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 53:23 58:34] + assign io_bus_write_strobe_3 = io_clint_exception_token ? 1'h0 : _GEN_76; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 53:23 58:34] + assign io_bus_request = io_clint_exception_token ? 1'h0 : _GEN_68; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 58:34 59:20] + always @(posedge clock) begin + if (reset) begin // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 42:33] + mem_access_state <= 2'h0; // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 42:33] + end else if (!(io_clint_exception_token)) begin // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 58:34] + if (io_memory_read_enable) begin // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 61:37] + if (mem_access_state == 2'h0) begin // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 62:56] + mem_access_state <= _GEN_2; + end else begin + mem_access_state <= _GEN_10; + end + end else if (io_memory_write_enable) begin // @[src/main/scala/riscv/core/fivestage/MemoryAccess.scala 110:38] + mem_access_state <= _GEN_56; + end + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + mem_access_state = _RAND_0[1:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module MEM2WB( + input clock, + input reset, + input [31:0] io_instruction_address, // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 21:14] + input [31:0] io_alu_result, // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 21:14] + input io_regs_write_enable, // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 21:14] + input [1:0] io_regs_write_source, // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 21:14] + input [31:0] io_regs_write_address, // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 21:14] + input [31:0] io_memory_read_data, // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 21:14] + input [31:0] io_csr_read_data, // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 21:14] + output [31:0] io_output_instruction_address, // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 21:14] + output [31:0] io_output_alu_result, // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 21:14] + output io_output_regs_write_enable, // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 21:14] + output [1:0] io_output_regs_write_source, // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 21:14] + output [31:0] io_output_regs_write_address, // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 21:14] + output [31:0] io_output_memory_read_data, // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 21:14] + output [31:0] io_output_csr_read_data // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 21:14] +); + wire alu_result_clock; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 41:26] + wire alu_result_reset; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 41:26] + wire alu_result_io_write_enable; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 41:26] + wire alu_result_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 41:26] + wire [31:0] alu_result_io_in; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 41:26] + wire [31:0] alu_result_io_out; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 41:26] + wire memory_read_data_clock; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 47:32] + wire memory_read_data_reset; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 47:32] + wire memory_read_data_io_write_enable; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 47:32] + wire memory_read_data_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 47:32] + wire [31:0] memory_read_data_io_in; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 47:32] + wire [31:0] memory_read_data_io_out; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 47:32] + wire regs_write_enable_clock; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 53:33] + wire regs_write_enable_reset; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 53:33] + wire regs_write_enable_io_write_enable; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 53:33] + wire regs_write_enable_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 53:33] + wire regs_write_enable_io_in; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 53:33] + wire regs_write_enable_io_out; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 53:33] + wire regs_write_source_clock; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 59:33] + wire regs_write_source_reset; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 59:33] + wire regs_write_source_io_write_enable; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 59:33] + wire regs_write_source_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 59:33] + wire [1:0] regs_write_source_io_in; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 59:33] + wire [1:0] regs_write_source_io_out; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 59:33] + wire regs_write_address_clock; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 65:34] + wire regs_write_address_reset; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 65:34] + wire regs_write_address_io_write_enable; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 65:34] + wire regs_write_address_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 65:34] + wire [4:0] regs_write_address_io_in; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 65:34] + wire [4:0] regs_write_address_io_out; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 65:34] + wire instruction_address_clock; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 71:35] + wire instruction_address_reset; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 71:35] + wire instruction_address_io_write_enable; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 71:35] + wire instruction_address_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 71:35] + wire [31:0] instruction_address_io_in; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 71:35] + wire [31:0] instruction_address_io_out; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 71:35] + wire csr_read_data_clock; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 77:29] + wire csr_read_data_reset; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 77:29] + wire csr_read_data_io_write_enable; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 77:29] + wire csr_read_data_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 77:29] + wire [31:0] csr_read_data_io_in; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 77:29] + wire [31:0] csr_read_data_io_out; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 77:29] + PipelineRegister_2 alu_result ( // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 41:26] + .clock(alu_result_clock), + .reset(alu_result_reset), + .io_write_enable(alu_result_io_write_enable), + .io_flush_enable(alu_result_io_flush_enable), + .io_in(alu_result_io_in), + .io_out(alu_result_io_out) + ); + PipelineRegister_2 memory_read_data ( // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 47:32] + .clock(memory_read_data_clock), + .reset(memory_read_data_reset), + .io_write_enable(memory_read_data_io_write_enable), + .io_flush_enable(memory_read_data_io_flush_enable), + .io_in(memory_read_data_io_in), + .io_out(memory_read_data_io_out) + ); + PipelineRegister_5 regs_write_enable ( // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 53:33] + .clock(regs_write_enable_clock), + .reset(regs_write_enable_reset), + .io_write_enable(regs_write_enable_io_write_enable), + .io_flush_enable(regs_write_enable_io_flush_enable), + .io_in(regs_write_enable_io_in), + .io_out(regs_write_enable_io_out) + ); + PipelineRegister_7 regs_write_source ( // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 59:33] + .clock(regs_write_source_clock), + .reset(regs_write_source_reset), + .io_write_enable(regs_write_source_io_write_enable), + .io_flush_enable(regs_write_source_io_flush_enable), + .io_in(regs_write_source_io_in), + .io_out(regs_write_source_io_out) + ); + PipelineRegister_6 regs_write_address ( // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 65:34] + .clock(regs_write_address_clock), + .reset(regs_write_address_reset), + .io_write_enable(regs_write_address_io_write_enable), + .io_flush_enable(regs_write_address_io_flush_enable), + .io_in(regs_write_address_io_in), + .io_out(regs_write_address_io_out) + ); + PipelineRegister_2 instruction_address ( // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 71:35] + .clock(instruction_address_clock), + .reset(instruction_address_reset), + .io_write_enable(instruction_address_io_write_enable), + .io_flush_enable(instruction_address_io_flush_enable), + .io_in(instruction_address_io_in), + .io_out(instruction_address_io_out) + ); + PipelineRegister_2 csr_read_data ( // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 77:29] + .clock(csr_read_data_clock), + .reset(csr_read_data_reset), + .io_write_enable(csr_read_data_io_write_enable), + .io_flush_enable(csr_read_data_io_flush_enable), + .io_in(csr_read_data_io_in), + .io_out(csr_read_data_io_out) + ); + assign io_output_instruction_address = instruction_address_io_out; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 75:33] + assign io_output_alu_result = alu_result_io_out; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 45:24] + assign io_output_regs_write_enable = regs_write_enable_io_out; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 57:31] + assign io_output_regs_write_source = regs_write_source_io_out; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 63:31] + assign io_output_regs_write_address = {{27'd0}, regs_write_address_io_out}; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 69:32] + assign io_output_memory_read_data = memory_read_data_io_out; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 51:30] + assign io_output_csr_read_data = csr_read_data_io_out; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 81:27] + assign alu_result_clock = clock; + assign alu_result_reset = reset; + assign alu_result_io_write_enable = 1'h1; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 43:30] + assign alu_result_io_flush_enable = 1'h0; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 44:30] + assign alu_result_io_in = io_alu_result; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 42:20] + assign memory_read_data_clock = clock; + assign memory_read_data_reset = reset; + assign memory_read_data_io_write_enable = 1'h1; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 49:36] + assign memory_read_data_io_flush_enable = 1'h0; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 50:36] + assign memory_read_data_io_in = io_memory_read_data; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 48:26] + assign regs_write_enable_clock = clock; + assign regs_write_enable_reset = reset; + assign regs_write_enable_io_write_enable = 1'h1; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 55:37] + assign regs_write_enable_io_flush_enable = 1'h0; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 56:37] + assign regs_write_enable_io_in = io_regs_write_enable; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 54:27] + assign regs_write_source_clock = clock; + assign regs_write_source_reset = reset; + assign regs_write_source_io_write_enable = 1'h1; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 61:37] + assign regs_write_source_io_flush_enable = 1'h0; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 62:37] + assign regs_write_source_io_in = io_regs_write_source; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 60:27] + assign regs_write_address_clock = clock; + assign regs_write_address_reset = reset; + assign regs_write_address_io_write_enable = 1'h1; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 67:38] + assign regs_write_address_io_flush_enable = 1'h0; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 68:38] + assign regs_write_address_io_in = io_regs_write_address[4:0]; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 66:28] + assign instruction_address_clock = clock; + assign instruction_address_reset = reset; + assign instruction_address_io_write_enable = 1'h1; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 73:39] + assign instruction_address_io_flush_enable = 1'h0; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 74:39] + assign instruction_address_io_in = io_instruction_address; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 72:29] + assign csr_read_data_clock = clock; + assign csr_read_data_reset = reset; + assign csr_read_data_io_write_enable = 1'h1; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 79:33] + assign csr_read_data_io_flush_enable = 1'h0; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 80:33] + assign csr_read_data_io_in = io_csr_read_data; // @[src/main/scala/riscv/core/fivestage/MEM2WB.scala 78:23] +endmodule +module WriteBack( + input [31:0] io_instruction_address, // @[src/main/scala/riscv/core/fivestage/WriteBack.scala 22:14] + input [31:0] io_alu_result, // @[src/main/scala/riscv/core/fivestage/WriteBack.scala 22:14] + input [31:0] io_memory_read_data, // @[src/main/scala/riscv/core/fivestage/WriteBack.scala 22:14] + input [1:0] io_regs_write_source, // @[src/main/scala/riscv/core/fivestage/WriteBack.scala 22:14] + input [31:0] io_csr_read_data, // @[src/main/scala/riscv/core/fivestage/WriteBack.scala 22:14] + output [31:0] io_regs_write_data // @[src/main/scala/riscv/core/fivestage/WriteBack.scala 22:14] +); + wire [31:0] _io_regs_write_data_T_1 = io_instruction_address + 32'h4; // @[src/main/scala/riscv/core/fivestage/WriteBack.scala 35:72] + wire [31:0] _io_regs_write_data_T_3 = 2'h1 == io_regs_write_source ? io_memory_read_data : io_alu_result; // @[src/main/scala/riscv/core/fivestage/WriteBack.scala 31:71] + wire [31:0] _io_regs_write_data_T_5 = 2'h2 == io_regs_write_source ? io_csr_read_data : _io_regs_write_data_T_3; // @[src/main/scala/riscv/core/fivestage/WriteBack.scala 31:71] + assign io_regs_write_data = 2'h3 == io_regs_write_source ? _io_regs_write_data_T_1 : _io_regs_write_data_T_5; // @[src/main/scala/riscv/core/fivestage/WriteBack.scala 31:71] +endmodule +module Forwarding( + input [4:0] io_rs1_id, // @[src/main/scala/riscv/core/fivestage/Forwarding.scala 27:14] + input [4:0] io_rs2_id, // @[src/main/scala/riscv/core/fivestage/Forwarding.scala 27:14] + input [4:0] io_rs1_ex, // @[src/main/scala/riscv/core/fivestage/Forwarding.scala 27:14] + input [4:0] io_rs2_ex, // @[src/main/scala/riscv/core/fivestage/Forwarding.scala 27:14] + input [4:0] io_rd_mem, // @[src/main/scala/riscv/core/fivestage/Forwarding.scala 27:14] + input io_reg_write_enable_mem, // @[src/main/scala/riscv/core/fivestage/Forwarding.scala 27:14] + input [4:0] io_rd_wb, // @[src/main/scala/riscv/core/fivestage/Forwarding.scala 27:14] + input io_reg_write_enable_wb, // @[src/main/scala/riscv/core/fivestage/Forwarding.scala 27:14] + output [1:0] io_reg1_forward_id, // @[src/main/scala/riscv/core/fivestage/Forwarding.scala 27:14] + output [1:0] io_reg2_forward_id, // @[src/main/scala/riscv/core/fivestage/Forwarding.scala 27:14] + output [1:0] io_reg1_forward_ex, // @[src/main/scala/riscv/core/fivestage/Forwarding.scala 27:14] + output [1:0] io_reg2_forward_ex // @[src/main/scala/riscv/core/fivestage/Forwarding.scala 27:14] +); + wire _T_1 = io_reg_write_enable_mem & io_rd_mem != 5'h0; // @[src/main/scala/riscv/core/fivestage/Forwarding.scala 43:32] + wire _T_5 = io_reg_write_enable_wb & io_rd_wb != 5'h0; // @[src/main/scala/riscv/core/fivestage/Forwarding.scala 45:37] + wire [1:0] _GEN_0 = io_reg_write_enable_wb & io_rd_wb != 5'h0 & io_rd_wb == io_rs1_id ? 2'h2 : 2'h0; // @[src/main/scala/riscv/core/fivestage/Forwarding.scala 45:84 46:24 48:24] + wire [1:0] _GEN_2 = _T_5 & io_rd_wb == io_rs2_id ? 2'h2 : 2'h0; // @[src/main/scala/riscv/core/fivestage/Forwarding.scala 53:84 54:24 56:24] + wire [1:0] _GEN_4 = _T_5 & io_rd_wb == io_rs1_ex ? 2'h2 : 2'h0; // @[src/main/scala/riscv/core/fivestage/Forwarding.scala 61:84 62:24 64:24] + wire [1:0] _GEN_6 = _T_5 & io_rd_wb == io_rs2_ex ? 2'h2 : 2'h0; // @[src/main/scala/riscv/core/fivestage/Forwarding.scala 69:84 70:24 72:24] + assign io_reg1_forward_id = io_reg_write_enable_mem & io_rd_mem != 5'h0 & io_rd_mem == io_rs1_id ? 2'h1 : _GEN_0; // @[src/main/scala/riscv/core/fivestage/Forwarding.scala 43:81 44:24] + assign io_reg2_forward_id = _T_1 & io_rd_mem == io_rs2_id ? 2'h1 : _GEN_2; // @[src/main/scala/riscv/core/fivestage/Forwarding.scala 51:81 52:24] + assign io_reg1_forward_ex = _T_1 & io_rd_mem == io_rs1_ex ? 2'h1 : _GEN_4; // @[src/main/scala/riscv/core/fivestage/Forwarding.scala 59:81 60:24] + assign io_reg2_forward_ex = _T_1 & io_rd_mem == io_rs2_ex ? 2'h1 : _GEN_6; // @[src/main/scala/riscv/core/fivestage/Forwarding.scala 67:81 68:24] +endmodule +module CLINT( + input clock, + input reset, + input [31:0] io_interrupt_flag, // @[src/main/scala/riscv/core/fivestage/CLINT.scala 49:14] + input [31:0] io_instruction, // @[src/main/scala/riscv/core/fivestage/CLINT.scala 49:14] + input [31:0] io_instruction_address_if, // @[src/main/scala/riscv/core/fivestage/CLINT.scala 49:14] + input io_exception_signal, // @[src/main/scala/riscv/core/fivestage/CLINT.scala 49:14] + input [31:0] io_instruction_address_cause_exception, // @[src/main/scala/riscv/core/fivestage/CLINT.scala 49:14] + input [31:0] io_exception_cause, // @[src/main/scala/riscv/core/fivestage/CLINT.scala 49:14] + input [31:0] io_exception_val, // @[src/main/scala/riscv/core/fivestage/CLINT.scala 49:14] + output io_exception_token, // @[src/main/scala/riscv/core/fivestage/CLINT.scala 49:14] + input io_jump_flag, // @[src/main/scala/riscv/core/fivestage/CLINT.scala 49:14] + input [31:0] io_jump_address, // @[src/main/scala/riscv/core/fivestage/CLINT.scala 49:14] + input [31:0] io_csr_mtvec, // @[src/main/scala/riscv/core/fivestage/CLINT.scala 49:14] + input [31:0] io_csr_mepc, // @[src/main/scala/riscv/core/fivestage/CLINT.scala 49:14] + input [31:0] io_csr_mstatus, // @[src/main/scala/riscv/core/fivestage/CLINT.scala 49:14] + input io_interrupt_enable, // @[src/main/scala/riscv/core/fivestage/CLINT.scala 49:14] + output io_ctrl_stall_flag, // @[src/main/scala/riscv/core/fivestage/CLINT.scala 49:14] + output io_csr_reg_write_enable, // @[src/main/scala/riscv/core/fivestage/CLINT.scala 49:14] + output [11:0] io_csr_reg_write_address, // @[src/main/scala/riscv/core/fivestage/CLINT.scala 49:14] + output [31:0] io_csr_reg_write_data, // @[src/main/scala/riscv/core/fivestage/CLINT.scala 49:14] + output [31:0] io_id_interrupt_handler_address, // @[src/main/scala/riscv/core/fivestage/CLINT.scala 49:14] + output io_id_interrupt_assert // @[src/main/scala/riscv/core/fivestage/CLINT.scala 49:14] +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; +`endif // RANDOMIZE_REG_INIT + reg [2:0] csr_state; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 87:26] + reg [31:0] instruction_address; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 88:36] + reg [31:0] cause; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 89:22] + reg [31:0] trap_val; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 90:25] + reg interrupt_assert; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 91:33] + reg [31:0] interrupt_handler_address; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 92:42] + reg csr_reg_write_enable; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 93:37] + reg [11:0] csr_reg_write_address; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 94:38] + reg [31:0] csr_reg_write_data; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 95:35] + reg exception_token; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 96:32] + reg exception_signal; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 97:33] + wire [1:0] _GEN_3 = io_instruction == 32'h30200073 ? 2'h3 : 2'h0; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 119:55 120:21 122:21] + wire [1:0] _GEN_4 = io_interrupt_flag != 32'h0 & io_interrupt_enable ? 2'h2 : _GEN_3; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 117:81 118:21] + wire [1:0] interrupt_state = exception_signal | io_instruction == 32'h73 | io_instruction == 32'h100073 ? 2'h1 : + _GEN_4; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 115:115 116:21] + wire _io_ctrl_stall_flag_T_1 = csr_state != 3'h0; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 98:79] + wire _T = csr_state == 3'h4; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 101:38] + wire _T_1 = exception_signal & csr_state == 3'h4; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 101:25] + wire _GEN_1 = ~exception_signal & io_exception_signal | exception_signal; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 109:67 110:22 97:33] + wire [31:0] _instruction_address_T_1 = io_jump_address - 32'h4; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 136:27] + wire [31:0] _instruction_address_T_2 = io_jump_flag ? _instruction_address_T_1 : io_instruction_address_if; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 134:12] + wire [3:0] _cause_T_1 = 32'h73 == io_instruction ? 4'hb : 4'ha; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 144:40] + wire [3:0] _cause_T_3 = 32'h100073 == io_instruction ? 4'h3 : _cause_T_1; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 144:40] + wire [31:0] _GEN_6 = io_interrupt_flag[0] ? 32'h80000007 : 32'h8000000b; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 161:13 162:34 163:15] + wire [31:0] _instruction_address_T_4 = io_jump_flag ? io_jump_address : io_instruction_address_if; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 167:33] + wire [2:0] _GEN_7 = interrupt_state == 2'h3 ? 3'h3 : csr_state; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 172:57 174:17 87:26] + wire _T_20 = csr_state == 3'h3; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 184:24] + wire [2:0] _GEN_18 = csr_state == 3'h5 ? 3'h4 : 3'h0; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 180:44 181:15] + wire _csr_reg_write_address_T_1 = 3'h2 == csr_state; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 191:110] + wire [11:0] _csr_reg_write_address_T_2 = 3'h2 == csr_state ? 12'h341 : 12'h0; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 191:110] + wire _csr_reg_write_address_T_3 = 3'h4 == csr_state; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 191:110] + wire [11:0] _csr_reg_write_address_T_4 = 3'h4 == csr_state ? 12'h342 : _csr_reg_write_address_T_2; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 191:110] + wire _csr_reg_write_address_T_5 = 3'h1 == csr_state; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 191:110] + wire [11:0] _csr_reg_write_address_T_6 = 3'h1 == csr_state ? 12'h300 : _csr_reg_write_address_T_4; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 191:110] + wire _csr_reg_write_address_T_7 = 3'h3 == csr_state; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 191:110] + wire [11:0] _csr_reg_write_address_T_8 = 3'h3 == csr_state ? 12'h300 : _csr_reg_write_address_T_6; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 191:110] + wire _csr_reg_write_address_T_9 = 3'h5 == csr_state; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 191:110] + wire [11:0] _csr_reg_write_address_T_10 = 3'h5 == csr_state ? 12'h343 : _csr_reg_write_address_T_8; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 191:110] + wire [31:0] _csr_reg_write_address_T_11 = {20'h0,_csr_reg_write_address_T_10}; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 191:31] + wire [31:0] _csr_reg_write_data_T_2 = {io_csr_mstatus[31:4],1'h0,io_csr_mstatus[2:0]}; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 205:30] + wire [31:0] _csr_reg_write_data_T_6 = {io_csr_mstatus[31:4],io_csr_mstatus[7],io_csr_mstatus[2:0]}; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 206:27] + wire [31:0] _csr_reg_write_data_T_8 = _csr_reg_write_address_T_1 ? instruction_address : 32'h0; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 201:72] + wire [31:0] _csr_reg_write_data_T_10 = _csr_reg_write_address_T_3 ? cause : _csr_reg_write_data_T_8; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 201:72] + wire [31:0] _GEN_25 = reset ? 32'h0 : _csr_reg_write_address_T_11; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 191:25 94:{38,38}] + assign io_exception_token = exception_token; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 99:22] + assign io_ctrl_stall_flag = (interrupt_state != 2'h0 | csr_state != 3'h0) & ~exception_token; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 98:98] + assign io_csr_reg_write_enable = csr_reg_write_enable; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 211:27] + assign io_csr_reg_write_address = csr_reg_write_address; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 212:28] + assign io_csr_reg_write_data = csr_reg_write_data; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 213:25] + assign io_id_interrupt_handler_address = interrupt_handler_address; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 224:35] + assign io_id_interrupt_assert = interrupt_assert; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 223:26] + always @(posedge clock) begin + if (reset) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 87:26] + csr_state <= 3'h0; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 87:26] + end else if (csr_state == 3'h0) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 126:37] + if (interrupt_state == 2'h1) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 127:57] + csr_state <= 3'h2; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 129:17] + end else if (interrupt_state == 2'h2) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 159:64] + csr_state <= 3'h2; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 166:17] + end else begin + csr_state <= _GEN_7; + end + end else if (csr_state == 3'h2) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 176:43] + csr_state <= 3'h1; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 177:15] + end else if (csr_state == 3'h1) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 178:46] + csr_state <= 3'h5; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 179:15] + end else begin + csr_state <= _GEN_18; + end + if (reset) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 88:36] + instruction_address <= 32'h0; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 88:36] + end else if (csr_state == 3'h0) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 126:37] + if (interrupt_state == 2'h1) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 127:57] + if (exception_signal) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 131:33] + instruction_address <= io_instruction_address_cause_exception; + end else begin + instruction_address <= _instruction_address_T_2; + end + end else if (interrupt_state == 2'h2) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 159:64] + instruction_address <= _instruction_address_T_4; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 167:27] + end + end + if (reset) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 89:22] + cause <= 32'h0; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 89:22] + end else if (csr_state == 3'h0) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 126:37] + if (interrupt_state == 2'h1) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 127:57] + if (exception_signal) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 141:19] + cause <= io_exception_cause; + end else begin + cause <= {{28'd0}, _cause_T_3}; + end + end else if (interrupt_state == 2'h2) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 159:64] + cause <= _GEN_6; + end + end + if (reset) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 90:25] + trap_val <= 32'h0; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 90:25] + end else if (csr_state == 3'h0) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 126:37] + if (interrupt_state == 2'h1) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 127:57] + if (exception_signal) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 154:22] + trap_val <= io_exception_val; + end else begin + trap_val <= 32'h0; + end + end else if (interrupt_state == 2'h2) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 159:64] + trap_val <= 32'h0; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 165:16] + end + end + if (reset) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 91:33] + interrupt_assert <= 1'h0; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 91:33] + end else begin + interrupt_assert <= _T | _T_20; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 215:20] + end + if (reset) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 92:42] + interrupt_handler_address <= 32'h0; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 92:42] + end else if (_csr_reg_write_address_T_7) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 216:79] + interrupt_handler_address <= io_csr_mepc; + end else if (_csr_reg_write_address_T_3) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 216:79] + interrupt_handler_address <= io_csr_mtvec; + end else begin + interrupt_handler_address <= 32'h0; + end + if (reset) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 93:37] + csr_reg_write_enable <= 1'h0; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 93:37] + end else begin + csr_reg_write_enable <= _io_ctrl_stall_flag_T_1; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 190:24] + end + csr_reg_write_address <= _GEN_25[11:0]; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 191:25 94:{38,38}] + if (reset) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 95:35] + csr_reg_write_data <= 32'h0; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 95:35] + end else if (_csr_reg_write_address_T_9) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 201:72] + csr_reg_write_data <= trap_val; + end else if (_csr_reg_write_address_T_7) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 201:72] + csr_reg_write_data <= _csr_reg_write_data_T_6; + end else if (_csr_reg_write_address_T_5) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 201:72] + csr_reg_write_data <= _csr_reg_write_data_T_2; + end else begin + csr_reg_write_data <= _csr_reg_write_data_T_10; + end + if (reset) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 96:32] + exception_token <= 1'h0; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 96:32] + end else begin + exception_token <= _T_1; + end + if (reset) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 97:33] + exception_signal <= 1'h0; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 97:33] + end else if (exception_token) begin // @[src/main/scala/riscv/core/fivestage/CLINT.scala 107:25] + exception_signal <= 1'h0; // @[src/main/scala/riscv/core/fivestage/CLINT.scala 108:22] + end else begin + exception_signal <= _GEN_1; + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + csr_state = _RAND_0[2:0]; + _RAND_1 = {1{`RANDOM}}; + instruction_address = _RAND_1[31:0]; + _RAND_2 = {1{`RANDOM}}; + cause = _RAND_2[31:0]; + _RAND_3 = {1{`RANDOM}}; + trap_val = _RAND_3[31:0]; + _RAND_4 = {1{`RANDOM}}; + interrupt_assert = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + interrupt_handler_address = _RAND_5[31:0]; + _RAND_6 = {1{`RANDOM}}; + csr_reg_write_enable = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + csr_reg_write_address = _RAND_7[11:0]; + _RAND_8 = {1{`RANDOM}}; + csr_reg_write_data = _RAND_8[31:0]; + _RAND_9 = {1{`RANDOM}}; + exception_token = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + exception_signal = _RAND_10[0:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module CSR( + input clock, + input reset, + input io_reg_write_enable_ex, // @[src/main/scala/riscv/core/fivestage/CSR.scala 37:14] + input [11:0] io_reg_read_address_id, // @[src/main/scala/riscv/core/fivestage/CSR.scala 37:14] + input [11:0] io_reg_write_address_ex, // @[src/main/scala/riscv/core/fivestage/CSR.scala 37:14] + input [31:0] io_reg_write_data_ex, // @[src/main/scala/riscv/core/fivestage/CSR.scala 37:14] + input io_reg_write_enable_clint, // @[src/main/scala/riscv/core/fivestage/CSR.scala 37:14] + input [11:0] io_reg_write_address_clint, // @[src/main/scala/riscv/core/fivestage/CSR.scala 37:14] + input [31:0] io_reg_write_data_clint, // @[src/main/scala/riscv/core/fivestage/CSR.scala 37:14] + output io_interrupt_enable, // @[src/main/scala/riscv/core/fivestage/CSR.scala 37:14] + output io_mmu_enable, // @[src/main/scala/riscv/core/fivestage/CSR.scala 37:14] + output [31:0] io_id_reg_data, // @[src/main/scala/riscv/core/fivestage/CSR.scala 37:14] + output io_start_paging, // @[src/main/scala/riscv/core/fivestage/CSR.scala 37:14] + output [31:0] io_clint_csr_mtvec, // @[src/main/scala/riscv/core/fivestage/CSR.scala 37:14] + output [31:0] io_clint_csr_mepc, // @[src/main/scala/riscv/core/fivestage/CSR.scala 37:14] + output [31:0] io_clint_csr_mstatus, // @[src/main/scala/riscv/core/fivestage/CSR.scala 37:14] + output [31:0] io_mmu_csr_satp // @[src/main/scala/riscv/core/fivestage/CSR.scala 37:14] +); +`ifdef RANDOMIZE_REG_INIT + reg [63:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; +`endif // RANDOMIZE_REG_INIT + reg [63:0] cycles; // @[src/main/scala/riscv/core/fivestage/CSR.scala 62:23] + reg [31:0] mtvec; // @[src/main/scala/riscv/core/fivestage/CSR.scala 63:22] + reg [31:0] mcause; // @[src/main/scala/riscv/core/fivestage/CSR.scala 64:23] + reg [31:0] mepc; // @[src/main/scala/riscv/core/fivestage/CSR.scala 65:21] + reg [31:0] mie; // @[src/main/scala/riscv/core/fivestage/CSR.scala 66:20] + reg [31:0] mstatus; // @[src/main/scala/riscv/core/fivestage/CSR.scala 67:24] + reg [31:0] mscratch; // @[src/main/scala/riscv/core/fivestage/CSR.scala 68:25] + reg [31:0] mtval; // @[src/main/scala/riscv/core/fivestage/CSR.scala 69:22] + reg [31:0] satp; // @[src/main/scala/riscv/core/fivestage/CSR.scala 70:21] + wire [63:0] _cycles_T_1 = cycles + 64'h1; // @[src/main/scala/riscv/core/fivestage/CSR.scala 72:20] + wire [11:0] _GEN_0 = io_reg_write_enable_clint ? io_reg_write_address_clint : 12'h0; // @[src/main/scala/riscv/core/fivestage/CSR.scala 83:21 94:41 95:23] + wire [31:0] _GEN_1 = io_reg_write_enable_clint ? io_reg_write_data_clint : 32'h0; // @[src/main/scala/riscv/core/fivestage/CSR.scala 84:18 94:41 96:20] + wire [11:0] reg_write_address = io_reg_write_enable_ex ? io_reg_write_address_ex : _GEN_0; // @[src/main/scala/riscv/core/fivestage/CSR.scala 91:32 92:23] + wire [31:0] reg_write_data = io_reg_write_enable_ex ? io_reg_write_data_ex : _GEN_1; // @[src/main/scala/riscv/core/fivestage/CSR.scala 91:32 93:20] + wire _T_12 = reg_write_data[31] & ~satp[31]; // @[src/main/scala/riscv/core/fivestage/CSR.scala 115:37] + wire [31:0] _GEN_5 = reg_write_address == 12'h180 ? reg_write_data : satp; // @[src/main/scala/riscv/core/fivestage/CSR.scala 113:54 114:10 70:21] + wire _GEN_6 = reg_write_address == 12'h180 & _T_12; // @[src/main/scala/riscv/core/fivestage/CSR.scala 113:54 79:19] + wire [31:0] _GEN_7 = reg_write_address == 12'h343 ? reg_write_data : mtval; // @[src/main/scala/riscv/core/fivestage/CSR.scala 111:55 112:11 69:22] + wire [31:0] _GEN_8 = reg_write_address == 12'h343 ? satp : _GEN_5; // @[src/main/scala/riscv/core/fivestage/CSR.scala 111:55 70:21] + wire _GEN_9 = reg_write_address == 12'h343 ? 1'h0 : _GEN_6; // @[src/main/scala/riscv/core/fivestage/CSR.scala 111:55 79:19] + wire [31:0] _GEN_10 = reg_write_address == 12'h340 ? reg_write_data : mscratch; // @[src/main/scala/riscv/core/fivestage/CSR.scala 109:58 110:14 68:25] + wire [31:0] _GEN_11 = reg_write_address == 12'h340 ? mtval : _GEN_7; // @[src/main/scala/riscv/core/fivestage/CSR.scala 109:58 69:22] + wire [31:0] _GEN_12 = reg_write_address == 12'h340 ? satp : _GEN_8; // @[src/main/scala/riscv/core/fivestage/CSR.scala 109:58 70:21] + wire _GEN_13 = reg_write_address == 12'h340 ? 1'h0 : _GEN_9; // @[src/main/scala/riscv/core/fivestage/CSR.scala 109:58 79:19] + wire [31:0] _GEN_14 = reg_write_address == 12'h300 ? reg_write_data : mstatus; // @[src/main/scala/riscv/core/fivestage/CSR.scala 107:57 108:13 67:24] + wire [31:0] _GEN_15 = reg_write_address == 12'h300 ? mscratch : _GEN_10; // @[src/main/scala/riscv/core/fivestage/CSR.scala 107:57 68:25] + wire [31:0] _GEN_16 = reg_write_address == 12'h300 ? mtval : _GEN_11; // @[src/main/scala/riscv/core/fivestage/CSR.scala 107:57 69:22] + wire [31:0] _GEN_17 = reg_write_address == 12'h300 ? satp : _GEN_12; // @[src/main/scala/riscv/core/fivestage/CSR.scala 107:57 70:21] + wire _GEN_18 = reg_write_address == 12'h300 ? 1'h0 : _GEN_13; // @[src/main/scala/riscv/core/fivestage/CSR.scala 107:57 79:19] + wire [31:0] _GEN_19 = reg_write_address == 12'h304 ? reg_write_data : mie; // @[src/main/scala/riscv/core/fivestage/CSR.scala 105:53 106:9 66:20] + wire [31:0] _GEN_20 = reg_write_address == 12'h304 ? mstatus : _GEN_14; // @[src/main/scala/riscv/core/fivestage/CSR.scala 105:53 67:24] + wire [31:0] _GEN_21 = reg_write_address == 12'h304 ? mscratch : _GEN_15; // @[src/main/scala/riscv/core/fivestage/CSR.scala 105:53 68:25] + wire [31:0] _GEN_22 = reg_write_address == 12'h304 ? mtval : _GEN_16; // @[src/main/scala/riscv/core/fivestage/CSR.scala 105:53 69:22] + wire [31:0] _GEN_23 = reg_write_address == 12'h304 ? satp : _GEN_17; // @[src/main/scala/riscv/core/fivestage/CSR.scala 105:53 70:21] + wire _GEN_24 = reg_write_address == 12'h304 ? 1'h0 : _GEN_18; // @[src/main/scala/riscv/core/fivestage/CSR.scala 105:53 79:19] + wire _GEN_31 = reg_write_address == 12'h341 ? 1'h0 : _GEN_24; // @[src/main/scala/riscv/core/fivestage/CSR.scala 103:54 79:19] + wire _GEN_39 = reg_write_address == 12'h342 ? 1'h0 : _GEN_31; // @[src/main/scala/riscv/core/fivestage/CSR.scala 101:56 79:19] + wire [31:0] _io_id_reg_data_T_1 = 12'hc00 == io_reg_read_address_id ? cycles[31:0] : 32'h0; // @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + wire [31:0] _io_id_reg_data_T_3 = 12'hc80 == io_reg_read_address_id ? cycles[63:32] : _io_id_reg_data_T_1; // @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + wire [31:0] _io_id_reg_data_T_5 = 12'h305 == io_reg_read_address_id ? mtvec : _io_id_reg_data_T_3; // @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + wire [31:0] _io_id_reg_data_T_7 = 12'h342 == io_reg_read_address_id ? mcause : _io_id_reg_data_T_5; // @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + wire [31:0] _io_id_reg_data_T_9 = 12'h341 == io_reg_read_address_id ? mepc : _io_id_reg_data_T_7; // @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + wire [31:0] _io_id_reg_data_T_11 = 12'h304 == io_reg_read_address_id ? mie : _io_id_reg_data_T_9; // @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + wire [31:0] _io_id_reg_data_T_13 = 12'h300 == io_reg_read_address_id ? mstatus : _io_id_reg_data_T_11; // @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + wire [31:0] _io_id_reg_data_T_15 = 12'h340 == io_reg_read_address_id ? mscratch : _io_id_reg_data_T_13; // @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + wire [31:0] _io_id_reg_data_T_17 = 12'h343 == io_reg_read_address_id ? mtval : _io_id_reg_data_T_15; // @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + assign io_interrupt_enable = mstatus[3]; // @[src/main/scala/riscv/core/fivestage/CSR.scala 76:33] + assign io_mmu_enable = satp[31]; // @[src/main/scala/riscv/core/fivestage/CSR.scala 78:24] + assign io_id_reg_data = 12'h180 == io_reg_read_address_id ? satp : _io_id_reg_data_T_17; // @[src/main/scala/riscv/core/fivestage/CSR.scala 134:59] + assign io_start_paging = reg_write_address == 12'h305 ? 1'h0 : _GEN_39; // @[src/main/scala/riscv/core/fivestage/CSR.scala 79:19 99:49] + assign io_clint_csr_mtvec = mtvec; // @[src/main/scala/riscv/core/fivestage/CSR.scala 73:22] + assign io_clint_csr_mepc = mepc; // @[src/main/scala/riscv/core/fivestage/CSR.scala 74:21] + assign io_clint_csr_mstatus = mstatus; // @[src/main/scala/riscv/core/fivestage/CSR.scala 75:24] + assign io_mmu_csr_satp = satp; // @[src/main/scala/riscv/core/fivestage/CSR.scala 77:19] + always @(posedge clock) begin + if (reset) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 62:23] + cycles <= 64'h0; // @[src/main/scala/riscv/core/fivestage/CSR.scala 62:23] + end else begin + cycles <= _cycles_T_1; // @[src/main/scala/riscv/core/fivestage/CSR.scala 72:10] + end + if (reset) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 63:22] + mtvec <= 32'h0; // @[src/main/scala/riscv/core/fivestage/CSR.scala 63:22] + end else if (reg_write_address == 12'h305) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 99:49] + if (io_reg_write_enable_ex) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 91:32] + mtvec <= io_reg_write_data_ex; // @[src/main/scala/riscv/core/fivestage/CSR.scala 93:20] + end else if (io_reg_write_enable_clint) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 94:41] + mtvec <= io_reg_write_data_clint; // @[src/main/scala/riscv/core/fivestage/CSR.scala 96:20] + end else begin + mtvec <= 32'h0; // @[src/main/scala/riscv/core/fivestage/CSR.scala 84:18] + end + end + if (reset) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 64:23] + mcause <= 32'h0; // @[src/main/scala/riscv/core/fivestage/CSR.scala 64:23] + end else if (!(reg_write_address == 12'h305)) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 99:49] + if (reg_write_address == 12'h342) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 101:56] + if (io_reg_write_enable_ex) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 91:32] + mcause <= io_reg_write_data_ex; // @[src/main/scala/riscv/core/fivestage/CSR.scala 93:20] + end else begin + mcause <= _GEN_1; + end + end + end + if (reset) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 65:21] + mepc <= 32'h0; // @[src/main/scala/riscv/core/fivestage/CSR.scala 65:21] + end else if (!(reg_write_address == 12'h305)) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 99:49] + if (!(reg_write_address == 12'h342)) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 101:56] + if (reg_write_address == 12'h341) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 103:54] + mepc <= reg_write_data; // @[src/main/scala/riscv/core/fivestage/CSR.scala 104:10] + end + end + end + if (reset) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 66:20] + mie <= 32'h0; // @[src/main/scala/riscv/core/fivestage/CSR.scala 66:20] + end else if (!(reg_write_address == 12'h305)) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 99:49] + if (!(reg_write_address == 12'h342)) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 101:56] + if (!(reg_write_address == 12'h341)) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 103:54] + mie <= _GEN_19; + end + end + end + if (reset) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 67:24] + mstatus <= 32'h0; // @[src/main/scala/riscv/core/fivestage/CSR.scala 67:24] + end else if (!(reg_write_address == 12'h305)) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 99:49] + if (!(reg_write_address == 12'h342)) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 101:56] + if (!(reg_write_address == 12'h341)) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 103:54] + mstatus <= _GEN_20; + end + end + end + if (reset) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 68:25] + mscratch <= 32'h0; // @[src/main/scala/riscv/core/fivestage/CSR.scala 68:25] + end else if (!(reg_write_address == 12'h305)) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 99:49] + if (!(reg_write_address == 12'h342)) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 101:56] + if (!(reg_write_address == 12'h341)) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 103:54] + mscratch <= _GEN_21; + end + end + end + if (reset) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 69:22] + mtval <= 32'h0; // @[src/main/scala/riscv/core/fivestage/CSR.scala 69:22] + end else if (!(reg_write_address == 12'h305)) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 99:49] + if (!(reg_write_address == 12'h342)) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 101:56] + if (!(reg_write_address == 12'h341)) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 103:54] + mtval <= _GEN_22; + end + end + end + if (reset) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 70:21] + satp <= 32'h0; // @[src/main/scala/riscv/core/fivestage/CSR.scala 70:21] + end else if (!(reg_write_address == 12'h305)) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 99:49] + if (!(reg_write_address == 12'h342)) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 101:56] + if (!(reg_write_address == 12'h341)) begin // @[src/main/scala/riscv/core/fivestage/CSR.scala 103:54] + satp <= _GEN_23; + end + end + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {2{`RANDOM}}; + cycles = _RAND_0[63:0]; + _RAND_1 = {1{`RANDOM}}; + mtvec = _RAND_1[31:0]; + _RAND_2 = {1{`RANDOM}}; + mcause = _RAND_2[31:0]; + _RAND_3 = {1{`RANDOM}}; + mepc = _RAND_3[31:0]; + _RAND_4 = {1{`RANDOM}}; + mie = _RAND_4[31:0]; + _RAND_5 = {1{`RANDOM}}; + mstatus = _RAND_5[31:0]; + _RAND_6 = {1{`RANDOM}}; + mscratch = _RAND_6[31:0]; + _RAND_7 = {1{`RANDOM}}; + mtval = _RAND_7[31:0]; + _RAND_8 = {1{`RANDOM}}; + satp = _RAND_8[31:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module AXI4LiteMaster( + input clock, + input reset, + output io_channels_write_address_channel_AWVALID, // @[src/main/scala/bus/AXI4Lite.scala 215:14] + input io_channels_write_address_channel_AWREADY, // @[src/main/scala/bus/AXI4Lite.scala 215:14] + output [31:0] io_channels_write_address_channel_AWADDR, // @[src/main/scala/bus/AXI4Lite.scala 215:14] + output io_channels_write_data_channel_WVALID, // @[src/main/scala/bus/AXI4Lite.scala 215:14] + input io_channels_write_data_channel_WREADY, // @[src/main/scala/bus/AXI4Lite.scala 215:14] + output [31:0] io_channels_write_data_channel_WDATA, // @[src/main/scala/bus/AXI4Lite.scala 215:14] + output [3:0] io_channels_write_data_channel_WSTRB, // @[src/main/scala/bus/AXI4Lite.scala 215:14] + input io_channels_write_response_channel_BVALID, // @[src/main/scala/bus/AXI4Lite.scala 215:14] + output io_channels_write_response_channel_BREADY, // @[src/main/scala/bus/AXI4Lite.scala 215:14] + output io_channels_read_address_channel_ARVALID, // @[src/main/scala/bus/AXI4Lite.scala 215:14] + input io_channels_read_address_channel_ARREADY, // @[src/main/scala/bus/AXI4Lite.scala 215:14] + output [31:0] io_channels_read_address_channel_ARADDR, // @[src/main/scala/bus/AXI4Lite.scala 215:14] + input io_channels_read_data_channel_RVALID, // @[src/main/scala/bus/AXI4Lite.scala 215:14] + output io_channels_read_data_channel_RREADY, // @[src/main/scala/bus/AXI4Lite.scala 215:14] + input [31:0] io_channels_read_data_channel_RDATA, // @[src/main/scala/bus/AXI4Lite.scala 215:14] + input [1:0] io_channels_read_data_channel_RRESP, // @[src/main/scala/bus/AXI4Lite.scala 215:14] + input io_bundle_read, // @[src/main/scala/bus/AXI4Lite.scala 215:14] + input io_bundle_write, // @[src/main/scala/bus/AXI4Lite.scala 215:14] + output [31:0] io_bundle_read_data, // @[src/main/scala/bus/AXI4Lite.scala 215:14] + input [31:0] io_bundle_write_data, // @[src/main/scala/bus/AXI4Lite.scala 215:14] + input io_bundle_write_strobe_0, // @[src/main/scala/bus/AXI4Lite.scala 215:14] + input io_bundle_write_strobe_1, // @[src/main/scala/bus/AXI4Lite.scala 215:14] + input io_bundle_write_strobe_2, // @[src/main/scala/bus/AXI4Lite.scala 215:14] + input io_bundle_write_strobe_3, // @[src/main/scala/bus/AXI4Lite.scala 215:14] + input [31:0] io_bundle_address, // @[src/main/scala/bus/AXI4Lite.scala 215:14] + output io_bundle_busy, // @[src/main/scala/bus/AXI4Lite.scala 215:14] + output io_bundle_read_valid, // @[src/main/scala/bus/AXI4Lite.scala 215:14] + output io_bundle_write_valid // @[src/main/scala/bus/AXI4Lite.scala 215:14] +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; +`endif // RANDOMIZE_REG_INIT + reg [2:0] state; // @[src/main/scala/bus/AXI4Lite.scala 219:22] + reg [31:0] addr; // @[src/main/scala/bus/AXI4Lite.scala 222:21] + reg read_valid; // @[src/main/scala/bus/AXI4Lite.scala 223:27] + reg write_valid; // @[src/main/scala/bus/AXI4Lite.scala 225:28] + reg [31:0] write_data; // @[src/main/scala/bus/AXI4Lite.scala 227:27] + reg write_strobe_0; // @[src/main/scala/bus/AXI4Lite.scala 228:29] + reg write_strobe_1; // @[src/main/scala/bus/AXI4Lite.scala 228:29] + reg write_strobe_2; // @[src/main/scala/bus/AXI4Lite.scala 228:29] + reg write_strobe_3; // @[src/main/scala/bus/AXI4Lite.scala 228:29] + reg ARVALID; // @[src/main/scala/bus/AXI4Lite.scala 232:24] + reg RREADY; // @[src/main/scala/bus/AXI4Lite.scala 235:23] + reg AWVALID; // @[src/main/scala/bus/AXI4Lite.scala 239:24] + reg WVALID; // @[src/main/scala/bus/AXI4Lite.scala 242:23] + wire [1:0] io_channels_write_data_channel_WSTRB_lo = {write_strobe_1,write_strobe_0}; // @[src/main/scala/bus/AXI4Lite.scala 246:56] + wire [1:0] io_channels_write_data_channel_WSTRB_hi = {write_strobe_3,write_strobe_2}; // @[src/main/scala/bus/AXI4Lite.scala 246:56] + reg BREADY; // @[src/main/scala/bus/AXI4Lite.scala 247:23] + wire [2:0] _GEN_12 = io_channels_read_data_channel_RVALID & io_channels_read_data_channel_RRESP == 2'h0 ? 3'h0 : state + ; // @[src/main/scala/bus/AXI4Lite.scala 278:97 279:15 219:22] + wire _GEN_13 = io_channels_read_data_channel_RVALID & io_channels_read_data_channel_RRESP == 2'h0 | read_valid; // @[src/main/scala/bus/AXI4Lite.scala 278:97 280:20 223:27] + wire _GEN_14 = io_channels_read_data_channel_RVALID & io_channels_read_data_channel_RRESP == 2'h0 | RREADY; // @[src/main/scala/bus/AXI4Lite.scala 278:97 281:16 235:23] + wire [2:0] _GEN_16 = io_channels_write_address_channel_AWREADY & AWVALID ? 3'h4 : state; // @[src/main/scala/bus/AXI4Lite.scala 288:66 289:15 219:22] + wire _GEN_18 = io_channels_write_address_channel_AWREADY & AWVALID ? 1'h0 : 1'h1; // @[src/main/scala/bus/AXI4Lite.scala 286:15 288:66 291:17] + wire [2:0] _GEN_20 = io_channels_write_data_channel_WREADY & WVALID ? 3'h5 : state; // @[src/main/scala/bus/AXI4Lite.scala 297:61 299:15 219:22] + wire _GEN_21 = io_channels_write_data_channel_WREADY & WVALID ? 1'h0 : 1'h1; // @[src/main/scala/bus/AXI4Lite.scala 295:14 297:61 300:16] + wire [2:0] _GEN_22 = io_channels_write_response_channel_BVALID & BREADY ? 3'h0 : state; // @[src/main/scala/bus/AXI4Lite.scala 305:65 306:15 219:22] + wire _GEN_23 = io_channels_write_response_channel_BVALID & BREADY | write_valid; // @[src/main/scala/bus/AXI4Lite.scala 305:65 307:21 225:28] + wire _GEN_24 = io_channels_write_response_channel_BVALID & BREADY ? 1'h0 : 1'h1; // @[src/main/scala/bus/AXI4Lite.scala 304:14 305:65 308:16] + wire _GEN_25 = 3'h5 == state ? _GEN_24 : BREADY; // @[src/main/scala/bus/AXI4Lite.scala 250:17 247:23] + wire [2:0] _GEN_26 = 3'h5 == state ? _GEN_22 : state; // @[src/main/scala/bus/AXI4Lite.scala 250:17 219:22] + wire _GEN_27 = 3'h5 == state ? _GEN_23 : write_valid; // @[src/main/scala/bus/AXI4Lite.scala 250:17 225:28] + wire _GEN_28 = 3'h4 == state ? _GEN_21 : WVALID; // @[src/main/scala/bus/AXI4Lite.scala 250:17 242:23] + wire [31:0] _GEN_29 = 3'h4 == state ? addr : 32'h0; // @[src/main/scala/bus/AXI4Lite.scala 250:17 240:44] + wire [2:0] _GEN_30 = 3'h4 == state ? _GEN_20 : _GEN_26; // @[src/main/scala/bus/AXI4Lite.scala 250:17] + wire _GEN_31 = 3'h4 == state ? BREADY : _GEN_25; // @[src/main/scala/bus/AXI4Lite.scala 250:17 247:23] + wire _GEN_32 = 3'h4 == state ? write_valid : _GEN_27; // @[src/main/scala/bus/AXI4Lite.scala 250:17 225:28] + wire _GEN_33 = 3'h3 == state ? _GEN_18 : AWVALID; // @[src/main/scala/bus/AXI4Lite.scala 250:17 239:24] + wire [31:0] _GEN_34 = 3'h3 == state ? addr : _GEN_29; // @[src/main/scala/bus/AXI4Lite.scala 250:17] + wire [2:0] _GEN_35 = 3'h3 == state ? _GEN_16 : _GEN_30; // @[src/main/scala/bus/AXI4Lite.scala 250:17] + wire _GEN_36 = 3'h3 == state ? WVALID : _GEN_28; // @[src/main/scala/bus/AXI4Lite.scala 250:17 242:23] + wire _GEN_37 = 3'h3 == state ? BREADY : _GEN_31; // @[src/main/scala/bus/AXI4Lite.scala 250:17 247:23] + wire _GEN_38 = 3'h3 == state ? write_valid : _GEN_32; // @[src/main/scala/bus/AXI4Lite.scala 250:17 225:28] + wire [31:0] _GEN_44 = 3'h2 == state ? 32'h0 : _GEN_34; // @[src/main/scala/bus/AXI4Lite.scala 250:17 240:44] + wire [31:0] _GEN_49 = 3'h1 == state ? addr : 32'h0; // @[src/main/scala/bus/AXI4Lite.scala 250:17 231:43] + wire [31:0] _GEN_55 = 3'h1 == state ? 32'h0 : _GEN_44; // @[src/main/scala/bus/AXI4Lite.scala 250:17 240:44] + assign io_channels_write_address_channel_AWVALID = AWVALID; // @[src/main/scala/bus/AXI4Lite.scala 241:45] + assign io_channels_write_address_channel_AWADDR = 3'h0 == state ? 32'h0 : _GEN_55; // @[src/main/scala/bus/AXI4Lite.scala 250:17 240:44] + assign io_channels_write_data_channel_WVALID = WVALID; // @[src/main/scala/bus/AXI4Lite.scala 243:41] + assign io_channels_write_data_channel_WDATA = write_data; // @[src/main/scala/bus/AXI4Lite.scala 244:40] + assign io_channels_write_data_channel_WSTRB = {io_channels_write_data_channel_WSTRB_hi, + io_channels_write_data_channel_WSTRB_lo}; // @[src/main/scala/bus/AXI4Lite.scala 246:56] + assign io_channels_write_response_channel_BREADY = BREADY; // @[src/main/scala/bus/AXI4Lite.scala 248:45] + assign io_channels_read_address_channel_ARVALID = ARVALID; // @[src/main/scala/bus/AXI4Lite.scala 233:44] + assign io_channels_read_address_channel_ARADDR = 3'h0 == state ? 32'h0 : _GEN_49; // @[src/main/scala/bus/AXI4Lite.scala 250:17 231:43] + assign io_channels_read_data_channel_RREADY = RREADY; // @[src/main/scala/bus/AXI4Lite.scala 236:40] + assign io_bundle_read_data = io_channels_read_data_channel_RDATA; // @[src/main/scala/bus/AXI4Lite.scala 238:23] + assign io_bundle_busy = state != 3'h0; // @[src/main/scala/bus/AXI4Lite.scala 220:27] + assign io_bundle_read_valid = read_valid; // @[src/main/scala/bus/AXI4Lite.scala 224:24] + assign io_bundle_write_valid = write_valid; // @[src/main/scala/bus/AXI4Lite.scala 226:25] + always @(posedge clock) begin + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 219:22] + state <= 3'h0; // @[src/main/scala/bus/AXI4Lite.scala 219:22] + end else if (3'h0 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + if (io_bundle_write) begin // @[src/main/scala/bus/AXI4Lite.scala 258:29] + state <= 3'h3; // @[src/main/scala/bus/AXI4Lite.scala 259:15] + end else if (io_bundle_read) begin // @[src/main/scala/bus/AXI4Lite.scala 263:34] + state <= 3'h1; // @[src/main/scala/bus/AXI4Lite.scala 264:15] + end + end else if (3'h1 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + if (io_channels_read_address_channel_ARREADY & ARVALID) begin // @[src/main/scala/bus/AXI4Lite.scala 271:65] + state <= 3'h2; // @[src/main/scala/bus/AXI4Lite.scala 272:15] + end + end else if (3'h2 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + state <= _GEN_12; + end else begin + state <= _GEN_35; + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 222:21] + addr <= 32'h0; // @[src/main/scala/bus/AXI4Lite.scala 222:21] + end else if (3'h0 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + if (io_bundle_write) begin // @[src/main/scala/bus/AXI4Lite.scala 258:29] + addr <= io_bundle_address; // @[src/main/scala/bus/AXI4Lite.scala 260:14] + end else if (io_bundle_read) begin // @[src/main/scala/bus/AXI4Lite.scala 263:34] + addr <= io_bundle_address; // @[src/main/scala/bus/AXI4Lite.scala 265:14] + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 223:27] + read_valid <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 223:27] + end else if (3'h0 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + read_valid <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 256:18] + end else if (!(3'h1 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + if (3'h2 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + read_valid <= _GEN_13; + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 225:28] + write_valid <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 225:28] + end else if (3'h0 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + write_valid <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 257:19] + end else if (!(3'h1 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + if (!(3'h2 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + write_valid <= _GEN_38; + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 227:27] + write_data <= 32'h0; // @[src/main/scala/bus/AXI4Lite.scala 227:27] + end else if (3'h0 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + if (io_bundle_write) begin // @[src/main/scala/bus/AXI4Lite.scala 258:29] + write_data <= io_bundle_write_data; // @[src/main/scala/bus/AXI4Lite.scala 261:20] + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 228:29] + write_strobe_0 <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 228:29] + end else if (3'h0 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + if (io_bundle_write) begin // @[src/main/scala/bus/AXI4Lite.scala 258:29] + write_strobe_0 <= io_bundle_write_strobe_0; // @[src/main/scala/bus/AXI4Lite.scala 262:22] + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 228:29] + write_strobe_1 <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 228:29] + end else if (3'h0 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + if (io_bundle_write) begin // @[src/main/scala/bus/AXI4Lite.scala 258:29] + write_strobe_1 <= io_bundle_write_strobe_1; // @[src/main/scala/bus/AXI4Lite.scala 262:22] + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 228:29] + write_strobe_2 <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 228:29] + end else if (3'h0 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + if (io_bundle_write) begin // @[src/main/scala/bus/AXI4Lite.scala 258:29] + write_strobe_2 <= io_bundle_write_strobe_2; // @[src/main/scala/bus/AXI4Lite.scala 262:22] + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 228:29] + write_strobe_3 <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 228:29] + end else if (3'h0 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + if (io_bundle_write) begin // @[src/main/scala/bus/AXI4Lite.scala 258:29] + write_strobe_3 <= io_bundle_write_strobe_3; // @[src/main/scala/bus/AXI4Lite.scala 262:22] + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 232:24] + ARVALID <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 232:24] + end else if (3'h0 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + ARVALID <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 254:15] + end else if (3'h1 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + if (io_channels_read_address_channel_ARREADY & ARVALID) begin // @[src/main/scala/bus/AXI4Lite.scala 271:65] + ARVALID <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 274:17] + end else begin + ARVALID <= 1'h1; // @[src/main/scala/bus/AXI4Lite.scala 269:15] + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 235:23] + RREADY <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 235:23] + end else if (3'h0 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + RREADY <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 255:14] + end else if (!(3'h1 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + if (3'h2 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + RREADY <= _GEN_14; + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 239:24] + AWVALID <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 239:24] + end else if (3'h0 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + AWVALID <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 253:15] + end else if (!(3'h1 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + if (!(3'h2 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + AWVALID <= _GEN_33; + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 242:23] + WVALID <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 242:23] + end else if (3'h0 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + WVALID <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 252:14] + end else if (!(3'h1 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + if (!(3'h2 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + WVALID <= _GEN_36; + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 247:23] + BREADY <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 247:23] + end else if (!(3'h0 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + if (!(3'h1 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + if (!(3'h2 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 250:17] + BREADY <= _GEN_37; + end + end + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + state = _RAND_0[2:0]; + _RAND_1 = {1{`RANDOM}}; + addr = _RAND_1[31:0]; + _RAND_2 = {1{`RANDOM}}; + read_valid = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + write_valid = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + write_data = _RAND_4[31:0]; + _RAND_5 = {1{`RANDOM}}; + write_strobe_0 = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + write_strobe_1 = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + write_strobe_2 = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + write_strobe_3 = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + ARVALID = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + RREADY = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + AWVALID = _RAND_11[0:0]; + _RAND_12 = {1{`RANDOM}}; + WVALID = _RAND_12[0:0]; + _RAND_13 = {1{`RANDOM}}; + BREADY = _RAND_13[0:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module MMU( + input clock, + input reset, + input [31:0] io_instructions, // @[src/main/scala/riscv/core/fivestage/MMU.scala 14:14] + input [31:0] io_instructions_address, // @[src/main/scala/riscv/core/fivestage/MMU.scala 14:14] + input [19:0] io_ppn_from_satp, // @[src/main/scala/riscv/core/fivestage/MMU.scala 14:14] + input [31:0] io_virtual_address, // @[src/main/scala/riscv/core/fivestage/MMU.scala 14:14] + input io_mmu_occupied_by_mem, // @[src/main/scala/riscv/core/fivestage/MMU.scala 14:14] + input io_restart, // @[src/main/scala/riscv/core/fivestage/MMU.scala 14:14] + output io_restart_done, // @[src/main/scala/riscv/core/fivestage/MMU.scala 14:14] + output io_pa_valid, // @[src/main/scala/riscv/core/fivestage/MMU.scala 14:14] + output [31:0] io_pa, // @[src/main/scala/riscv/core/fivestage/MMU.scala 14:14] + output io_page_fault_signals, // @[src/main/scala/riscv/core/fivestage/MMU.scala 14:14] + output [31:0] io_va_cause_page_fault, // @[src/main/scala/riscv/core/fivestage/MMU.scala 14:14] + output [31:0] io_ecause, // @[src/main/scala/riscv/core/fivestage/MMU.scala 14:14] + output [31:0] io_epc, // @[src/main/scala/riscv/core/fivestage/MMU.scala 14:14] + input io_page_fault_responed, // @[src/main/scala/riscv/core/fivestage/MMU.scala 14:14] + output io_bus_read, // @[src/main/scala/riscv/core/fivestage/MMU.scala 14:14] + output [31:0] io_bus_address, // @[src/main/scala/riscv/core/fivestage/MMU.scala 14:14] + input [31:0] io_bus_read_data, // @[src/main/scala/riscv/core/fivestage/MMU.scala 14:14] + input io_bus_read_valid, // @[src/main/scala/riscv/core/fivestage/MMU.scala 14:14] + output io_bus_write, // @[src/main/scala/riscv/core/fivestage/MMU.scala 14:14] + output [31:0] io_bus_write_data, // @[src/main/scala/riscv/core/fivestage/MMU.scala 14:14] + output io_bus_write_strobe_0, // @[src/main/scala/riscv/core/fivestage/MMU.scala 14:14] + output io_bus_write_strobe_1, // @[src/main/scala/riscv/core/fivestage/MMU.scala 14:14] + output io_bus_write_strobe_2, // @[src/main/scala/riscv/core/fivestage/MMU.scala 14:14] + output io_bus_write_strobe_3, // @[src/main/scala/riscv/core/fivestage/MMU.scala 14:14] + input io_bus_write_valid, // @[src/main/scala/riscv/core/fivestage/MMU.scala 14:14] + input io_bus_granted // @[src/main/scala/riscv/core/fivestage/MMU.scala 14:14] +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; +`endif // RANDOMIZE_REG_INIT + wire [6:0] opcode = io_instructions[6:0]; // @[src/main/scala/riscv/core/fivestage/MMU.scala 37:31] + reg [2:0] state; // @[src/main/scala/riscv/core/fivestage/MMU.scala 39:22] + wire [9:0] vpn1 = io_virtual_address[31:22]; // @[src/main/scala/riscv/core/fivestage/MMU.scala 43:16] + wire [9:0] vpn0 = io_virtual_address[21:12]; // @[src/main/scala/riscv/core/fivestage/MMU.scala 45:16] + wire [11:0] pageoffset = io_virtual_address[11:0]; // @[src/main/scala/riscv/core/fivestage/MMU.scala 46:22] + reg [31:0] pte1; // @[src/main/scala/riscv/core/fivestage/MMU.scala 48:17] + reg [31:0] pte0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 49:17] + reg page_fault_signals; // @[src/main/scala/riscv/core/fivestage/MMU.scala 51:35] + wire [31:0] _GEN_199 = {io_ppn_from_satp, 12'h0}; // @[src/main/scala/riscv/core/fivestage/MMU.scala 101:44] + wire [34:0] _io_bus_address_T = {{3'd0}, _GEN_199}; // @[src/main/scala/riscv/core/fivestage/MMU.scala 101:44] + wire [11:0] _io_bus_address_T_1 = {vpn1, 2'h0}; // @[src/main/scala/riscv/core/fivestage/MMU.scala 101:91] + wire [34:0] _GEN_200 = {{23'd0}, _io_bus_address_T_1}; // @[src/main/scala/riscv/core/fivestage/MMU.scala 101:83] + wire [34:0] _io_bus_address_T_2 = _io_bus_address_T & _GEN_200; // @[src/main/scala/riscv/core/fivestage/MMU.scala 101:83] + wire [1:0] _GEN_1 = io_restart ? 2'h0 : 2'h2; // @[src/main/scala/riscv/core/fivestage/MMU.scala 109:26 111:17 113:17] + wire _GEN_3 = io_bus_read_valid & io_restart; // @[src/main/scala/riscv/core/fivestage/MMU.scala 107:31 88:19] + wire [2:0] _GEN_4 = io_bus_read_valid ? {{1'd0}, _GEN_1} : state; // @[src/main/scala/riscv/core/fivestage/MMU.scala 107:31 39:22] + wire [3:0] _io_ecause_T_1 = 32'h23 == io_instructions ? 4'hf : 4'ha; // @[src/main/scala/riscv/core/fivestage/MMU.scala 56:39] + wire [3:0] _io_ecause_T_3 = 32'h3 == io_instructions ? 4'hd : _io_ecause_T_1; // @[src/main/scala/riscv/core/fivestage/MMU.scala 56:39] + wire [3:0] _io_ecause_T_4 = io_mmu_occupied_by_mem ? _io_ecause_T_3 : 4'hc; // @[src/main/scala/riscv/core/fivestage/MMU.scala 54:21] + wire [31:0] _io_epc_T = io_mmu_occupied_by_mem ? io_instructions_address : io_virtual_address; // @[src/main/scala/riscv/core/fivestage/MMU.scala 66:18] + wire _GEN_5 = io_page_fault_responed ? 1'h0 : 1'h1; // @[src/main/scala/riscv/core/fivestage/MMU.scala 65:24 71:34 72:26] + wire [2:0] _GEN_6 = io_page_fault_responed ? 3'h0 : state; // @[src/main/scala/riscv/core/fivestage/MMU.scala 71:34 73:13 39:22] + wire [31:0] _GEN_201 = {pte1[29:10], 12'h0}; // @[src/main/scala/riscv/core/fivestage/MMU.scala 126:42] + wire [34:0] _io_bus_address_T_4 = {{3'd0}, _GEN_201}; // @[src/main/scala/riscv/core/fivestage/MMU.scala 126:42] + wire [11:0] _io_bus_address_T_5 = {vpn0, 2'h0}; // @[src/main/scala/riscv/core/fivestage/MMU.scala 126:89] + wire [34:0] _GEN_202 = {{23'd0}, _io_bus_address_T_5}; // @[src/main/scala/riscv/core/fivestage/MMU.scala 126:81] + wire [34:0] _io_bus_address_T_6 = _io_bus_address_T_4 & _GEN_202; // @[src/main/scala/riscv/core/fivestage/MMU.scala 126:81] + wire [2:0] _GEN_7 = io_bus_granted ? 3'h3 : state; // @[src/main/scala/riscv/core/fivestage/MMU.scala 128:30 129:17 39:22] + wire [3:0] _GEN_8 = ~pte1[0] | pte1[2:1] == 2'h2 | pte1[9:8] != 2'h0 ? _io_ecause_T_4 : 4'h0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 121:91 54:15 86:13] + wire [31:0] _GEN_9 = ~pte1[0] | pte1[2:1] == 2'h2 | pte1[9:8] != 2'h0 ? io_virtual_address : 32'h0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 121:91 64:28 89:26] + wire _GEN_10 = ~pte1[0] | pte1[2:1] == 2'h2 | pte1[9:8] != 2'h0 ? _GEN_5 : page_fault_signals; // @[src/main/scala/riscv/core/fivestage/MMU.scala 121:91 51:35] + wire [31:0] _GEN_11 = ~pte1[0] | pte1[2:1] == 2'h2 | pte1[9:8] != 2'h0 ? _io_epc_T : 32'h0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 121:91 66:12 90:10] + wire [2:0] _GEN_12 = ~pte1[0] | pte1[2:1] == 2'h2 | pte1[9:8] != 2'h0 ? _GEN_6 : _GEN_7; // @[src/main/scala/riscv/core/fivestage/MMU.scala 121:91] + wire _GEN_13 = ~pte1[0] | pte1[2:1] == 2'h2 | pte1[9:8] != 2'h0 ? 1'h0 : 1'h1; // @[src/main/scala/riscv/core/fivestage/MMU.scala 121:91 79:15 125:21] + wire [34:0] _GEN_14 = ~pte1[0] | pte1[2:1] == 2'h2 | pte1[9:8] != 2'h0 ? 35'h0 : _io_bus_address_T_6; // @[src/main/scala/riscv/core/fivestage/MMU.scala 121:91 80:18 126:24] + wire [2:0] _GEN_15 = io_restart ? 3'h0 : _GEN_12; // @[src/main/scala/riscv/core/fivestage/MMU.scala 118:24 120:15] + wire [3:0] _GEN_16 = io_restart ? 4'h0 : _GEN_8; // @[src/main/scala/riscv/core/fivestage/MMU.scala 118:24 86:13] + wire [31:0] _GEN_17 = io_restart ? 32'h0 : _GEN_9; // @[src/main/scala/riscv/core/fivestage/MMU.scala 118:24 89:26] + wire _GEN_18 = io_restart ? page_fault_signals : _GEN_10; // @[src/main/scala/riscv/core/fivestage/MMU.scala 118:24 51:35] + wire [31:0] _GEN_19 = io_restart ? 32'h0 : _GEN_11; // @[src/main/scala/riscv/core/fivestage/MMU.scala 118:24 90:10] + wire _GEN_20 = io_restart ? 1'h0 : _GEN_13; // @[src/main/scala/riscv/core/fivestage/MMU.scala 118:24 79:15] + wire [34:0] _GEN_21 = io_restart ? 35'h0 : _GEN_14; // @[src/main/scala/riscv/core/fivestage/MMU.scala 118:24 80:18] + wire [2:0] _GEN_22 = io_restart ? 3'h0 : 3'h4; // @[src/main/scala/riscv/core/fivestage/MMU.scala 136:26 138:17 140:17] + wire [31:0] _GEN_23 = io_bus_read_valid ? io_bus_read_data : pte0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 134:31 135:14 49:17] + wire [2:0] _GEN_24 = io_bus_read_valid ? _GEN_22 : state; // @[src/main/scala/riscv/core/fivestage/MMU.scala 134:31 39:22] + wire instructionInvalid = ~io_mmu_occupied_by_mem & ~pte0[3]; // @[src/main/scala/riscv/core/fivestage/MMU.scala 152:69] + wire _storeInvalid_T_1 = opcode == 7'h23; // @[src/main/scala/riscv/core/fivestage/MMU.scala 153:50] + wire storeInvalid = opcode == 7'h23 & ~pte0[2]; // @[src/main/scala/riscv/core/fivestage/MMU.scala 153:73] + wire loadInvalid = opcode == 7'h3 & ~pte0[1]; // @[src/main/scala/riscv/core/fivestage/MMU.scala 154:72] + wire _T_38 = ~pte0[6] | ~pte0[7] & _storeInvalid_T_1; // @[src/main/scala/riscv/core/fivestage/MMU.scala 158:36] + wire [31:0] _io_bus_write_data_T_2 = {pte0[31:8],_storeInvalid_T_1,1'h1,pte0[5:0]}; // @[src/main/scala/riscv/core/fivestage/MMU.scala 164:35] + wire [34:0] _io_bus_address_T_11 = _io_bus_address_T_4 + _GEN_202; // @[src/main/scala/riscv/core/fivestage/MMU.scala 166:83] + wire [31:0] _GEN_25 = ~pte0[6] | ~pte0[7] & _storeInvalid_T_1 ? _io_bus_write_data_T_2 : 32'h0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 158:106 164:29 81:21] + wire [34:0] _GEN_27 = ~pte0[6] | ~pte0[7] & _storeInvalid_T_1 ? _io_bus_address_T_11 : 35'h0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 158:106 166:26 80:18] + wire [2:0] _GEN_32 = ~pte0[6] | ~pte0[7] & _storeInvalid_T_1 ? 3'h5 : 3'h6; // @[src/main/scala/riscv/core/fivestage/MMU.scala 158:106 170:17 172:17] + wire [3:0] _GEN_33 = instructionInvalid | storeInvalid | loadInvalid ? _io_ecause_T_4 : 4'h0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 155:65 54:15 86:13] + wire [31:0] _GEN_34 = instructionInvalid | storeInvalid | loadInvalid ? io_virtual_address : 32'h0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 155:65 64:28 89:26] + wire _GEN_35 = instructionInvalid | storeInvalid | loadInvalid ? _GEN_5 : page_fault_signals; // @[src/main/scala/riscv/core/fivestage/MMU.scala 155:65 51:35] + wire [31:0] _GEN_36 = instructionInvalid | storeInvalid | loadInvalid ? _io_epc_T : 32'h0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 155:65 66:12 90:10] + wire [2:0] _GEN_37 = instructionInvalid | storeInvalid | loadInvalid ? _GEN_6 : _GEN_32; // @[src/main/scala/riscv/core/fivestage/MMU.scala 155:65] + wire [31:0] _GEN_38 = instructionInvalid | storeInvalid | loadInvalid ? 32'h0 : _GEN_25; // @[src/main/scala/riscv/core/fivestage/MMU.scala 155:65 81:21] + wire _GEN_39 = instructionInvalid | storeInvalid | loadInvalid ? 1'h0 : _T_38; // @[src/main/scala/riscv/core/fivestage/MMU.scala 155:65 83:16] + wire [34:0] _GEN_40 = instructionInvalid | storeInvalid | loadInvalid ? 35'h0 : _GEN_27; // @[src/main/scala/riscv/core/fivestage/MMU.scala 155:65 80:18] + wire [3:0] _GEN_45 = pte0[1] | pte0[3] ? _GEN_33 : 4'h0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 150:54 86:13] + wire [31:0] _GEN_46 = pte0[1] | pte0[3] ? _GEN_34 : 32'h0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 150:54 89:26] + wire _GEN_47 = pte0[1] | pte0[3] ? _GEN_35 : page_fault_signals; // @[src/main/scala/riscv/core/fivestage/MMU.scala 150:54 51:35] + wire [31:0] _GEN_48 = pte0[1] | pte0[3] ? _GEN_36 : 32'h0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 150:54 90:10] + wire [2:0] _GEN_49 = pte0[1] | pte0[3] ? _GEN_37 : state; // @[src/main/scala/riscv/core/fivestage/MMU.scala 150:54 39:22] + wire [31:0] _GEN_50 = pte0[1] | pte0[3] ? _GEN_38 : 32'h0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 150:54 81:21] + wire _GEN_51 = (pte0[1] | pte0[3]) & _GEN_39; // @[src/main/scala/riscv/core/fivestage/MMU.scala 150:54 83:16] + wire [34:0] _GEN_52 = pte0[1] | pte0[3] ? _GEN_40 : 35'h0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 150:54 80:18] + wire [3:0] _GEN_57 = ~pte0[0] | pte0[2:1] == 2'h2 | pte0[9:8] != 2'h0 | pte0[3:1] == 3'h0 ? _io_ecause_T_4 : _GEN_45; // @[src/main/scala/riscv/core/fivestage/MMU.scala 147:120 54:15] + wire [31:0] _GEN_58 = ~pte0[0] | pte0[2:1] == 2'h2 | pte0[9:8] != 2'h0 | pte0[3:1] == 3'h0 ? io_virtual_address : + _GEN_46; // @[src/main/scala/riscv/core/fivestage/MMU.scala 147:120 64:28] + wire _GEN_59 = ~pte0[0] | pte0[2:1] == 2'h2 | pte0[9:8] != 2'h0 | pte0[3:1] == 3'h0 ? _GEN_5 : _GEN_47; // @[src/main/scala/riscv/core/fivestage/MMU.scala 147:120] + wire [31:0] _GEN_60 = ~pte0[0] | pte0[2:1] == 2'h2 | pte0[9:8] != 2'h0 | pte0[3:1] == 3'h0 ? _io_epc_T : _GEN_48; // @[src/main/scala/riscv/core/fivestage/MMU.scala 147:120 66:12] + wire [2:0] _GEN_61 = ~pte0[0] | pte0[2:1] == 2'h2 | pte0[9:8] != 2'h0 | pte0[3:1] == 3'h0 ? _GEN_6 : _GEN_49; // @[src/main/scala/riscv/core/fivestage/MMU.scala 147:120] + wire [31:0] _GEN_62 = ~pte0[0] | pte0[2:1] == 2'h2 | pte0[9:8] != 2'h0 | pte0[3:1] == 3'h0 ? 32'h0 : _GEN_50; // @[src/main/scala/riscv/core/fivestage/MMU.scala 147:120 81:21] + wire _GEN_63 = ~pte0[0] | pte0[2:1] == 2'h2 | pte0[9:8] != 2'h0 | pte0[3:1] == 3'h0 ? 1'h0 : _GEN_51; // @[src/main/scala/riscv/core/fivestage/MMU.scala 147:120 83:16] + wire [34:0] _GEN_64 = ~pte0[0] | pte0[2:1] == 2'h2 | pte0[9:8] != 2'h0 | pte0[3:1] == 3'h0 ? 35'h0 : _GEN_52; // @[src/main/scala/riscv/core/fivestage/MMU.scala 147:120 80:18] + wire [2:0] _GEN_69 = io_restart ? 3'h0 : _GEN_61; // @[src/main/scala/riscv/core/fivestage/MMU.scala 144:24 146:15] + wire [3:0] _GEN_70 = io_restart ? 4'h0 : _GEN_57; // @[src/main/scala/riscv/core/fivestage/MMU.scala 144:24 86:13] + wire [31:0] _GEN_71 = io_restart ? 32'h0 : _GEN_58; // @[src/main/scala/riscv/core/fivestage/MMU.scala 144:24 89:26] + wire _GEN_72 = io_restart ? page_fault_signals : _GEN_59; // @[src/main/scala/riscv/core/fivestage/MMU.scala 144:24 51:35] + wire [31:0] _GEN_73 = io_restart ? 32'h0 : _GEN_60; // @[src/main/scala/riscv/core/fivestage/MMU.scala 144:24 90:10] + wire [31:0] _GEN_74 = io_restart ? 32'h0 : _GEN_62; // @[src/main/scala/riscv/core/fivestage/MMU.scala 144:24 81:21] + wire _GEN_75 = io_restart ? 1'h0 : _GEN_63; // @[src/main/scala/riscv/core/fivestage/MMU.scala 144:24 83:16] + wire [34:0] _GEN_76 = io_restart ? 35'h0 : _GEN_64; // @[src/main/scala/riscv/core/fivestage/MMU.scala 144:24 80:18] + wire [2:0] _GEN_81 = io_restart ? 3'h0 : 3'h6; // @[src/main/scala/riscv/core/fivestage/MMU.scala 178:26 180:17 182:17] + wire _GEN_82 = io_bus_write_valid & io_restart; // @[src/main/scala/riscv/core/fivestage/MMU.scala 177:32 88:19] + wire [2:0] _GEN_83 = io_bus_write_valid ? _GEN_81 : state; // @[src/main/scala/riscv/core/fivestage/MMU.scala 177:32 39:22] + wire [31:0] _io_pa_T_1 = {pte0[29:10],pageoffset}; // @[src/main/scala/riscv/core/fivestage/MMU.scala 190:21] + wire [31:0] _GEN_85 = io_restart ? 32'h0 : _io_pa_T_1; // @[src/main/scala/riscv/core/fivestage/MMU.scala 186:24 190:15 87:9] + wire _GEN_86 = io_restart ? 1'h0 : 1'h1; // @[src/main/scala/riscv/core/fivestage/MMU.scala 186:24 77:15 191:21] + wire _GEN_87 = state == 3'h6 & io_restart; // @[src/main/scala/riscv/core/fivestage/MMU.scala 185:55 88:19] + wire [2:0] _GEN_88 = state == 3'h6 ? 3'h0 : state; // @[src/main/scala/riscv/core/fivestage/MMU.scala 185:55 39:22] + wire [31:0] _GEN_89 = state == 3'h6 ? _GEN_85 : 32'h0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 185:55 87:9] + wire _GEN_90 = state == 3'h6 & _GEN_86; // @[src/main/scala/riscv/core/fivestage/MMU.scala 185:55 77:15] + wire _GEN_92 = state == 3'h5 ? _GEN_82 : _GEN_87; // @[src/main/scala/riscv/core/fivestage/MMU.scala 175:46] + wire [2:0] _GEN_93 = state == 3'h5 ? _GEN_83 : _GEN_88; // @[src/main/scala/riscv/core/fivestage/MMU.scala 175:46] + wire [31:0] _GEN_94 = state == 3'h5 ? 32'h0 : _GEN_89; // @[src/main/scala/riscv/core/fivestage/MMU.scala 175:46 87:9] + wire _GEN_95 = state == 3'h5 ? 1'h0 : _GEN_90; // @[src/main/scala/riscv/core/fivestage/MMU.scala 175:46 77:15] + wire _GEN_96 = state == 3'h4 ? io_restart : _GEN_92; // @[src/main/scala/riscv/core/fivestage/MMU.scala 143:47] + wire [2:0] _GEN_97 = state == 3'h4 ? _GEN_69 : _GEN_93; // @[src/main/scala/riscv/core/fivestage/MMU.scala 143:47] + wire [3:0] _GEN_98 = state == 3'h4 ? _GEN_70 : 4'h0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 143:47 86:13] + wire [31:0] _GEN_99 = state == 3'h4 ? _GEN_71 : 32'h0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 143:47 89:26] + wire _GEN_100 = state == 3'h4 ? _GEN_72 : page_fault_signals; // @[src/main/scala/riscv/core/fivestage/MMU.scala 143:47 51:35] + wire [31:0] _GEN_101 = state == 3'h4 ? _GEN_73 : 32'h0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 143:47 90:10] + wire [31:0] _GEN_102 = state == 3'h4 ? _GEN_74 : 32'h0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 143:47 81:21] + wire _GEN_103 = state == 3'h4 & _GEN_75; // @[src/main/scala/riscv/core/fivestage/MMU.scala 143:47] + wire [34:0] _GEN_104 = state == 3'h4 ? _GEN_76 : 35'h0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 143:47 80:18] + wire [31:0] _GEN_109 = state == 3'h4 ? 32'h0 : _GEN_94; // @[src/main/scala/riscv/core/fivestage/MMU.scala 143:47 87:9] + wire _GEN_110 = state == 3'h4 ? 1'h0 : _GEN_95; // @[src/main/scala/riscv/core/fivestage/MMU.scala 143:47 77:15] + wire [31:0] _GEN_112 = state == 3'h3 ? _GEN_23 : pte0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 132:44 49:17] + wire _GEN_113 = state == 3'h3 ? _GEN_3 : _GEN_96; // @[src/main/scala/riscv/core/fivestage/MMU.scala 132:44] + wire [2:0] _GEN_114 = state == 3'h3 ? _GEN_24 : _GEN_97; // @[src/main/scala/riscv/core/fivestage/MMU.scala 132:44] + wire [3:0] _GEN_115 = state == 3'h3 ? 4'h0 : _GEN_98; // @[src/main/scala/riscv/core/fivestage/MMU.scala 132:44 86:13] + wire [31:0] _GEN_116 = state == 3'h3 ? 32'h0 : _GEN_99; // @[src/main/scala/riscv/core/fivestage/MMU.scala 132:44 89:26] + wire _GEN_117 = state == 3'h3 ? page_fault_signals : _GEN_100; // @[src/main/scala/riscv/core/fivestage/MMU.scala 132:44 51:35] + wire [31:0] _GEN_118 = state == 3'h3 ? 32'h0 : _GEN_101; // @[src/main/scala/riscv/core/fivestage/MMU.scala 132:44 90:10] + wire [31:0] _GEN_119 = state == 3'h3 ? 32'h0 : _GEN_102; // @[src/main/scala/riscv/core/fivestage/MMU.scala 132:44 81:21] + wire _GEN_120 = state == 3'h3 ? 1'h0 : _GEN_103; // @[src/main/scala/riscv/core/fivestage/MMU.scala 132:44 83:16] + wire [34:0] _GEN_121 = state == 3'h3 ? 35'h0 : _GEN_104; // @[src/main/scala/riscv/core/fivestage/MMU.scala 132:44 80:18] + wire [31:0] _GEN_126 = state == 3'h3 ? 32'h0 : _GEN_109; // @[src/main/scala/riscv/core/fivestage/MMU.scala 132:44 87:9] + wire _GEN_127 = state == 3'h3 ? 1'h0 : _GEN_110; // @[src/main/scala/riscv/core/fivestage/MMU.scala 132:44 77:15] + wire _GEN_128 = state == 3'h2 ? io_restart : _GEN_113; // @[src/main/scala/riscv/core/fivestage/MMU.scala 116:47] + wire [2:0] _GEN_129 = state == 3'h2 ? _GEN_15 : _GEN_114; // @[src/main/scala/riscv/core/fivestage/MMU.scala 116:47] + wire [3:0] _GEN_130 = state == 3'h2 ? _GEN_16 : _GEN_115; // @[src/main/scala/riscv/core/fivestage/MMU.scala 116:47] + wire [31:0] _GEN_131 = state == 3'h2 ? _GEN_17 : _GEN_116; // @[src/main/scala/riscv/core/fivestage/MMU.scala 116:47] + wire _GEN_132 = state == 3'h2 ? _GEN_18 : _GEN_117; // @[src/main/scala/riscv/core/fivestage/MMU.scala 116:47] + wire [31:0] _GEN_133 = state == 3'h2 ? _GEN_19 : _GEN_118; // @[src/main/scala/riscv/core/fivestage/MMU.scala 116:47] + wire _GEN_134 = state == 3'h2 & _GEN_20; // @[src/main/scala/riscv/core/fivestage/MMU.scala 116:47] + wire [34:0] _GEN_135 = state == 3'h2 ? _GEN_21 : _GEN_121; // @[src/main/scala/riscv/core/fivestage/MMU.scala 116:47] + wire [31:0] _GEN_137 = state == 3'h2 ? 32'h0 : _GEN_119; // @[src/main/scala/riscv/core/fivestage/MMU.scala 116:47 81:21] + wire _GEN_138 = state == 3'h2 ? 1'h0 : _GEN_120; // @[src/main/scala/riscv/core/fivestage/MMU.scala 116:47 83:16] + wire [31:0] _GEN_143 = state == 3'h2 ? 32'h0 : _GEN_126; // @[src/main/scala/riscv/core/fivestage/MMU.scala 116:47 87:9] + wire _GEN_144 = state == 3'h2 ? 1'h0 : _GEN_127; // @[src/main/scala/riscv/core/fivestage/MMU.scala 116:47 77:15] + wire _GEN_145 = state == 3'h1 ? 1'h0 : _GEN_134; // @[src/main/scala/riscv/core/fivestage/MMU.scala 104:44 106:19] + wire _GEN_147 = state == 3'h1 ? _GEN_3 : _GEN_128; // @[src/main/scala/riscv/core/fivestage/MMU.scala 104:44] + wire [3:0] _GEN_149 = state == 3'h1 ? 4'h0 : _GEN_130; // @[src/main/scala/riscv/core/fivestage/MMU.scala 104:44 86:13] + wire [31:0] _GEN_150 = state == 3'h1 ? 32'h0 : _GEN_131; // @[src/main/scala/riscv/core/fivestage/MMU.scala 104:44 89:26] + wire [31:0] _GEN_152 = state == 3'h1 ? 32'h0 : _GEN_133; // @[src/main/scala/riscv/core/fivestage/MMU.scala 104:44 90:10] + wire [34:0] _GEN_153 = state == 3'h1 ? 35'h0 : _GEN_135; // @[src/main/scala/riscv/core/fivestage/MMU.scala 104:44 80:18] + wire [31:0] _GEN_155 = state == 3'h1 ? 32'h0 : _GEN_137; // @[src/main/scala/riscv/core/fivestage/MMU.scala 104:44 81:21] + wire _GEN_156 = state == 3'h1 ? 1'h0 : _GEN_138; // @[src/main/scala/riscv/core/fivestage/MMU.scala 104:44 83:16] + wire [31:0] _GEN_161 = state == 3'h1 ? 32'h0 : _GEN_143; // @[src/main/scala/riscv/core/fivestage/MMU.scala 104:44 87:9] + wire _GEN_162 = state == 3'h1 ? 1'h0 : _GEN_144; // @[src/main/scala/riscv/core/fivestage/MMU.scala 104:44 77:15] + wire _GEN_163 = state == 3'h0 ? 1'h0 : _GEN_162; // @[src/main/scala/riscv/core/fivestage/MMU.scala 95:36 98:19] + wire _GEN_164 = state == 3'h0 | _GEN_145; // @[src/main/scala/riscv/core/fivestage/MMU.scala 95:36 99:19] + wire _GEN_165 = state == 3'h0 ? 1'h0 : _GEN_147; // @[src/main/scala/riscv/core/fivestage/MMU.scala 100:23 95:36] + wire [34:0] _GEN_166 = state == 3'h0 ? _io_bus_address_T_2 : _GEN_153; // @[src/main/scala/riscv/core/fivestage/MMU.scala 101:22 95:36] + wire [3:0] _GEN_169 = state == 3'h0 ? 4'h0 : _GEN_149; // @[src/main/scala/riscv/core/fivestage/MMU.scala 86:13 95:36] + wire [31:0] _GEN_170 = state == 3'h0 ? 32'h0 : _GEN_150; // @[src/main/scala/riscv/core/fivestage/MMU.scala 89:26 95:36] + wire [31:0] _GEN_172 = state == 3'h0 ? 32'h0 : _GEN_152; // @[src/main/scala/riscv/core/fivestage/MMU.scala 90:10 95:36] + wire [31:0] _GEN_174 = state == 3'h0 ? 32'h0 : _GEN_155; // @[src/main/scala/riscv/core/fivestage/MMU.scala 81:21 95:36] + wire _GEN_175 = state == 3'h0 ? 1'h0 : _GEN_156; // @[src/main/scala/riscv/core/fivestage/MMU.scala 83:16 95:36] + wire [31:0] _GEN_180 = state == 3'h0 ? 32'h0 : _GEN_161; // @[src/main/scala/riscv/core/fivestage/MMU.scala 95:36 87:9] + wire [34:0] _GEN_184 = io_bus_granted ? _GEN_166 : 35'h0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 80:18 94:24] + wire [3:0] _GEN_187 = io_bus_granted ? _GEN_169 : 4'h0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 86:13 94:24] + assign io_restart_done = io_bus_granted & _GEN_165; // @[src/main/scala/riscv/core/fivestage/MMU.scala 88:19 94:24] + assign io_pa_valid = io_bus_granted & _GEN_163; // @[src/main/scala/riscv/core/fivestage/MMU.scala 77:15 94:24] + assign io_pa = io_bus_granted ? _GEN_180 : 32'h0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 94:24 87:9] + assign io_page_fault_signals = page_fault_signals; // @[src/main/scala/riscv/core/fivestage/MMU.scala 84:25] + assign io_va_cause_page_fault = io_bus_granted ? _GEN_170 : 32'h0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 94:24 89:26] + assign io_ecause = {{28'd0}, _GEN_187}; + assign io_epc = io_bus_granted ? _GEN_172 : 32'h0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 90:10 94:24] + assign io_bus_read = io_bus_granted & _GEN_164; // @[src/main/scala/riscv/core/fivestage/MMU.scala 79:15 94:24] + assign io_bus_address = _GEN_184[31:0]; + assign io_bus_write = io_bus_granted & _GEN_175; // @[src/main/scala/riscv/core/fivestage/MMU.scala 83:16 94:24] + assign io_bus_write_data = io_bus_granted ? _GEN_174 : 32'h0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 81:21 94:24] + assign io_bus_write_strobe_0 = io_bus_granted & _GEN_175; // @[src/main/scala/riscv/core/fivestage/MMU.scala 82:23 94:24] + assign io_bus_write_strobe_1 = io_bus_granted & _GEN_175; // @[src/main/scala/riscv/core/fivestage/MMU.scala 82:23 94:24] + assign io_bus_write_strobe_2 = io_bus_granted & _GEN_175; // @[src/main/scala/riscv/core/fivestage/MMU.scala 82:23 94:24] + assign io_bus_write_strobe_3 = io_bus_granted & _GEN_175; // @[src/main/scala/riscv/core/fivestage/MMU.scala 82:23 94:24] + always @(posedge clock) begin + if (reset) begin // @[src/main/scala/riscv/core/fivestage/MMU.scala 39:22] + state <= 3'h0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 39:22] + end else if (io_bus_granted) begin // @[src/main/scala/riscv/core/fivestage/MMU.scala 94:24] + if (state == 3'h0) begin // @[src/main/scala/riscv/core/fivestage/MMU.scala 95:36] + state <= 3'h1; // @[src/main/scala/riscv/core/fivestage/MMU.scala 103:13] + end else if (state == 3'h1) begin // @[src/main/scala/riscv/core/fivestage/MMU.scala 104:44] + state <= _GEN_4; + end else begin + state <= _GEN_129; + end + end + if (io_bus_granted) begin // @[src/main/scala/riscv/core/fivestage/MMU.scala 94:24] + if (!(state == 3'h0)) begin // @[src/main/scala/riscv/core/fivestage/MMU.scala 95:36] + if (state == 3'h1) begin // @[src/main/scala/riscv/core/fivestage/MMU.scala 104:44] + if (io_bus_read_valid) begin // @[src/main/scala/riscv/core/fivestage/MMU.scala 107:31] + pte1 <= io_bus_read_data; // @[src/main/scala/riscv/core/fivestage/MMU.scala 108:14] + end + end + end + end + if (io_bus_granted) begin // @[src/main/scala/riscv/core/fivestage/MMU.scala 94:24] + if (!(state == 3'h0)) begin // @[src/main/scala/riscv/core/fivestage/MMU.scala 95:36] + if (!(state == 3'h1)) begin // @[src/main/scala/riscv/core/fivestage/MMU.scala 104:44] + if (!(state == 3'h2)) begin // @[src/main/scala/riscv/core/fivestage/MMU.scala 116:47] + pte0 <= _GEN_112; + end + end + end + end + if (reset) begin // @[src/main/scala/riscv/core/fivestage/MMU.scala 51:35] + page_fault_signals <= 1'h0; // @[src/main/scala/riscv/core/fivestage/MMU.scala 51:35] + end else if (io_bus_granted) begin // @[src/main/scala/riscv/core/fivestage/MMU.scala 94:24] + if (!(state == 3'h0)) begin // @[src/main/scala/riscv/core/fivestage/MMU.scala 95:36] + if (!(state == 3'h1)) begin // @[src/main/scala/riscv/core/fivestage/MMU.scala 104:44] + page_fault_signals <= _GEN_132; + end + end + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + state = _RAND_0[2:0]; + _RAND_1 = {1{`RANDOM}}; + pte1 = _RAND_1[31:0]; + _RAND_2 = {1{`RANDOM}}; + pte0 = _RAND_2[31:0]; + _RAND_3 = {1{`RANDOM}}; + page_fault_signals = _RAND_3[0:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module CPU( + input clock, + input reset, + output io_axi4_channels_write_address_channel_AWVALID, // @[src/main/scala/riscv/core/fivestage/CPU.scala 31:14] + input io_axi4_channels_write_address_channel_AWREADY, // @[src/main/scala/riscv/core/fivestage/CPU.scala 31:14] + output [31:0] io_axi4_channels_write_address_channel_AWADDR, // @[src/main/scala/riscv/core/fivestage/CPU.scala 31:14] + output io_axi4_channels_write_data_channel_WVALID, // @[src/main/scala/riscv/core/fivestage/CPU.scala 31:14] + input io_axi4_channels_write_data_channel_WREADY, // @[src/main/scala/riscv/core/fivestage/CPU.scala 31:14] + output [31:0] io_axi4_channels_write_data_channel_WDATA, // @[src/main/scala/riscv/core/fivestage/CPU.scala 31:14] + output [3:0] io_axi4_channels_write_data_channel_WSTRB, // @[src/main/scala/riscv/core/fivestage/CPU.scala 31:14] + input io_axi4_channels_write_response_channel_BVALID, // @[src/main/scala/riscv/core/fivestage/CPU.scala 31:14] + output io_axi4_channels_write_response_channel_BREADY, // @[src/main/scala/riscv/core/fivestage/CPU.scala 31:14] + output io_axi4_channels_read_address_channel_ARVALID, // @[src/main/scala/riscv/core/fivestage/CPU.scala 31:14] + input io_axi4_channels_read_address_channel_ARREADY, // @[src/main/scala/riscv/core/fivestage/CPU.scala 31:14] + output [31:0] io_axi4_channels_read_address_channel_ARADDR, // @[src/main/scala/riscv/core/fivestage/CPU.scala 31:14] + input io_axi4_channels_read_data_channel_RVALID, // @[src/main/scala/riscv/core/fivestage/CPU.scala 31:14] + output io_axi4_channels_read_data_channel_RREADY, // @[src/main/scala/riscv/core/fivestage/CPU.scala 31:14] + input [31:0] io_axi4_channels_read_data_channel_RDATA, // @[src/main/scala/riscv/core/fivestage/CPU.scala 31:14] + output [31:0] io_bus_address, // @[src/main/scala/riscv/core/fivestage/CPU.scala 31:14] + input [31:0] io_interrupt_flag, // @[src/main/scala/riscv/core/fivestage/CPU.scala 31:14] + input io_stall_flag_bus, // @[src/main/scala/riscv/core/fivestage/CPU.scala 31:14] + input io_instruction_valid // @[src/main/scala/riscv/core/fivestage/CPU.scala 31:14] +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; +`endif // RANDOMIZE_REG_INIT + wire ctrl_io_jump_flag; // @[src/main/scala/riscv/core/fivestage/CPU.scala 33:20] + wire ctrl_io_jump_instruction_id; // @[src/main/scala/riscv/core/fivestage/CPU.scala 33:20] + wire ctrl_io_stall_flag_if; // @[src/main/scala/riscv/core/fivestage/CPU.scala 33:20] + wire ctrl_io_stall_flag_mem; // @[src/main/scala/riscv/core/fivestage/CPU.scala 33:20] + wire ctrl_io_stall_flag_clint; // @[src/main/scala/riscv/core/fivestage/CPU.scala 33:20] + wire ctrl_io_stall_flag_bus; // @[src/main/scala/riscv/core/fivestage/CPU.scala 33:20] + wire [4:0] ctrl_io_rs1_id; // @[src/main/scala/riscv/core/fivestage/CPU.scala 33:20] + wire [4:0] ctrl_io_rs2_id; // @[src/main/scala/riscv/core/fivestage/CPU.scala 33:20] + wire ctrl_io_memory_read_enable_ex; // @[src/main/scala/riscv/core/fivestage/CPU.scala 33:20] + wire [4:0] ctrl_io_rd_ex; // @[src/main/scala/riscv/core/fivestage/CPU.scala 33:20] + wire ctrl_io_memory_read_enable_mem; // @[src/main/scala/riscv/core/fivestage/CPU.scala 33:20] + wire [4:0] ctrl_io_rd_mem; // @[src/main/scala/riscv/core/fivestage/CPU.scala 33:20] + wire ctrl_io_csr_start_paging; // @[src/main/scala/riscv/core/fivestage/CPU.scala 33:20] + wire ctrl_io_if_flush; // @[src/main/scala/riscv/core/fivestage/CPU.scala 33:20] + wire ctrl_io_id_flush; // @[src/main/scala/riscv/core/fivestage/CPU.scala 33:20] + wire ctrl_io_pc_stall; // @[src/main/scala/riscv/core/fivestage/CPU.scala 33:20] + wire ctrl_io_if_stall; // @[src/main/scala/riscv/core/fivestage/CPU.scala 33:20] + wire ctrl_io_id_stall; // @[src/main/scala/riscv/core/fivestage/CPU.scala 33:20] + wire ctrl_io_ex_stall; // @[src/main/scala/riscv/core/fivestage/CPU.scala 33:20] + wire regs_clock; // @[src/main/scala/riscv/core/fivestage/CPU.scala 34:20] + wire regs_reset; // @[src/main/scala/riscv/core/fivestage/CPU.scala 34:20] + wire regs_io_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 34:20] + wire [4:0] regs_io_write_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 34:20] + wire [31:0] regs_io_write_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 34:20] + wire [4:0] regs_io_read_address1; // @[src/main/scala/riscv/core/fivestage/CPU.scala 34:20] + wire [4:0] regs_io_read_address2; // @[src/main/scala/riscv/core/fivestage/CPU.scala 34:20] + wire [31:0] regs_io_read_data1; // @[src/main/scala/riscv/core/fivestage/CPU.scala 34:20] + wire [31:0] regs_io_read_data2; // @[src/main/scala/riscv/core/fivestage/CPU.scala 34:20] + wire inst_fetch_clock; // @[src/main/scala/riscv/core/fivestage/CPU.scala 35:26] + wire inst_fetch_reset; // @[src/main/scala/riscv/core/fivestage/CPU.scala 35:26] + wire inst_fetch_io_stall_flag_ctrl; // @[src/main/scala/riscv/core/fivestage/CPU.scala 35:26] + wire inst_fetch_io_jump_flag_id; // @[src/main/scala/riscv/core/fivestage/CPU.scala 35:26] + wire [31:0] inst_fetch_io_jump_address_id; // @[src/main/scala/riscv/core/fivestage/CPU.scala 35:26] + wire [31:0] inst_fetch_io_physical_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 35:26] + wire inst_fetch_io_ctrl_stall_flag; // @[src/main/scala/riscv/core/fivestage/CPU.scala 35:26] + wire [31:0] inst_fetch_io_id_instruction_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 35:26] + wire [31:0] inst_fetch_io_id_instruction; // @[src/main/scala/riscv/core/fivestage/CPU.scala 35:26] + wire inst_fetch_io_pc_valid; // @[src/main/scala/riscv/core/fivestage/CPU.scala 35:26] + wire inst_fetch_io_bus_read; // @[src/main/scala/riscv/core/fivestage/CPU.scala 35:26] + wire [31:0] inst_fetch_io_bus_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 35:26] + wire [31:0] inst_fetch_io_bus_read_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 35:26] + wire inst_fetch_io_bus_read_valid; // @[src/main/scala/riscv/core/fivestage/CPU.scala 35:26] + wire inst_fetch_io_bus_granted; // @[src/main/scala/riscv/core/fivestage/CPU.scala 35:26] + wire if2id_clock; // @[src/main/scala/riscv/core/fivestage/CPU.scala 36:21] + wire if2id_reset; // @[src/main/scala/riscv/core/fivestage/CPU.scala 36:21] + wire if2id_io_stall_flag; // @[src/main/scala/riscv/core/fivestage/CPU.scala 36:21] + wire if2id_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 36:21] + wire [31:0] if2id_io_instruction; // @[src/main/scala/riscv/core/fivestage/CPU.scala 36:21] + wire [31:0] if2id_io_instruction_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 36:21] + wire [31:0] if2id_io_interrupt_flag; // @[src/main/scala/riscv/core/fivestage/CPU.scala 36:21] + wire [31:0] if2id_io_output_instruction; // @[src/main/scala/riscv/core/fivestage/CPU.scala 36:21] + wire [31:0] if2id_io_output_instruction_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 36:21] + wire [31:0] if2id_io_output_interrupt_flag; // @[src/main/scala/riscv/core/fivestage/CPU.scala 36:21] + wire [31:0] id_io_instruction; // @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + wire [31:0] id_io_instruction_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + wire [31:0] id_io_reg1_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + wire [31:0] id_io_reg2_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + wire [31:0] id_io_forward_from_mem; // @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + wire [31:0] id_io_forward_from_wb; // @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + wire [1:0] id_io_reg1_forward; // @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + wire [1:0] id_io_reg2_forward; // @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + wire id_io_interrupt_assert; // @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + wire [31:0] id_io_interrupt_handler_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + wire [4:0] id_io_regs_reg1_read_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + wire [4:0] id_io_regs_reg2_read_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + wire [31:0] id_io_ex_immediate; // @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + wire id_io_ex_aluop1_source; // @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + wire id_io_ex_aluop2_source; // @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + wire id_io_ex_memory_read_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + wire id_io_ex_memory_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + wire [1:0] id_io_ex_reg_write_source; // @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + wire id_io_ex_reg_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + wire [4:0] id_io_ex_reg_write_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + wire [11:0] id_io_ex_csr_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + wire id_io_ex_csr_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + wire id_io_ctrl_jump_instruction; // @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + wire [31:0] id_io_clint_jump_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + wire id_io_if_jump_flag; // @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + wire [31:0] id_io_if_jump_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + wire id2ex_clock; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire id2ex_reset; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire id2ex_io_stall_flag; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire id2ex_io_flush_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire [31:0] id2ex_io_instruction; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire [31:0] id2ex_io_instruction_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire id2ex_io_regs_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire [4:0] id2ex_io_regs_write_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire [1:0] id2ex_io_regs_write_source; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire [31:0] id2ex_io_reg1_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire [31:0] id2ex_io_reg2_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire [31:0] id2ex_io_immediate; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire id2ex_io_aluop1_source; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire id2ex_io_aluop2_source; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire id2ex_io_csr_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire [11:0] id2ex_io_csr_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire id2ex_io_memory_read_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire id2ex_io_memory_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire [31:0] id2ex_io_csr_read_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire [31:0] id2ex_io_output_instruction; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire [31:0] id2ex_io_output_instruction_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire id2ex_io_output_regs_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire [4:0] id2ex_io_output_regs_write_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire [1:0] id2ex_io_output_regs_write_source; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire [31:0] id2ex_io_output_reg1_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire [31:0] id2ex_io_output_reg2_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire [31:0] id2ex_io_output_immediate; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire id2ex_io_output_aluop1_source; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire id2ex_io_output_aluop2_source; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire id2ex_io_output_csr_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire [11:0] id2ex_io_output_csr_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire id2ex_io_output_memory_read_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire id2ex_io_output_memory_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire [31:0] id2ex_io_output_csr_read_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + wire [31:0] ex_io_instruction; // @[src/main/scala/riscv/core/fivestage/CPU.scala 39:18] + wire [31:0] ex_io_instruction_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 39:18] + wire [31:0] ex_io_reg1_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 39:18] + wire [31:0] ex_io_reg2_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 39:18] + wire [31:0] ex_io_immediate; // @[src/main/scala/riscv/core/fivestage/CPU.scala 39:18] + wire ex_io_aluop1_source; // @[src/main/scala/riscv/core/fivestage/CPU.scala 39:18] + wire ex_io_aluop2_source; // @[src/main/scala/riscv/core/fivestage/CPU.scala 39:18] + wire [31:0] ex_io_csr_read_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 39:18] + wire [31:0] ex_io_forward_from_mem; // @[src/main/scala/riscv/core/fivestage/CPU.scala 39:18] + wire [31:0] ex_io_forward_from_wb; // @[src/main/scala/riscv/core/fivestage/CPU.scala 39:18] + wire [1:0] ex_io_reg1_forward; // @[src/main/scala/riscv/core/fivestage/CPU.scala 39:18] + wire [1:0] ex_io_reg2_forward; // @[src/main/scala/riscv/core/fivestage/CPU.scala 39:18] + wire [31:0] ex_io_mem_alu_result; // @[src/main/scala/riscv/core/fivestage/CPU.scala 39:18] + wire [31:0] ex_io_csr_write_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 39:18] + wire ex2mem_clock; // @[src/main/scala/riscv/core/fivestage/CPU.scala 40:22] + wire ex2mem_reset; // @[src/main/scala/riscv/core/fivestage/CPU.scala 40:22] + wire ex2mem_io_stall_flag; // @[src/main/scala/riscv/core/fivestage/CPU.scala 40:22] + wire ex2mem_io_regs_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 40:22] + wire [1:0] ex2mem_io_regs_write_source; // @[src/main/scala/riscv/core/fivestage/CPU.scala 40:22] + wire [31:0] ex2mem_io_regs_write_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 40:22] + wire [31:0] ex2mem_io_instruction_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 40:22] + wire [31:0] ex2mem_io_instruction; // @[src/main/scala/riscv/core/fivestage/CPU.scala 40:22] + wire [31:0] ex2mem_io_reg1_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 40:22] + wire [31:0] ex2mem_io_reg2_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 40:22] + wire ex2mem_io_memory_read_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 40:22] + wire ex2mem_io_memory_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 40:22] + wire [31:0] ex2mem_io_alu_result; // @[src/main/scala/riscv/core/fivestage/CPU.scala 40:22] + wire [31:0] ex2mem_io_csr_read_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 40:22] + wire ex2mem_io_output_regs_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 40:22] + wire [1:0] ex2mem_io_output_regs_write_source; // @[src/main/scala/riscv/core/fivestage/CPU.scala 40:22] + wire [31:0] ex2mem_io_output_regs_write_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 40:22] + wire [31:0] ex2mem_io_output_instruction_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 40:22] + wire [31:0] ex2mem_io_output_instruction; // @[src/main/scala/riscv/core/fivestage/CPU.scala 40:22] + wire [31:0] ex2mem_io_output_reg2_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 40:22] + wire ex2mem_io_output_memory_read_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 40:22] + wire ex2mem_io_output_memory_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 40:22] + wire [31:0] ex2mem_io_output_alu_result; // @[src/main/scala/riscv/core/fivestage/CPU.scala 40:22] + wire [31:0] ex2mem_io_output_csr_read_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 40:22] + wire mem_clock; // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + wire mem_reset; // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + wire [31:0] mem_io_alu_result; // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + wire [31:0] mem_io_reg2_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + wire mem_io_memory_read_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + wire mem_io_memory_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + wire [2:0] mem_io_funct3; // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + wire [1:0] mem_io_regs_write_source; // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + wire [31:0] mem_io_csr_read_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + wire mem_io_clint_exception_token; // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + wire [31:0] mem_io_wb_memory_read_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + wire mem_io_ctrl_stall_flag; // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + wire [31:0] mem_io_forward_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + wire [31:0] mem_io_physical_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + wire mem_io_bus_read; // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + wire [31:0] mem_io_bus_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + wire [31:0] mem_io_bus_read_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + wire mem_io_bus_read_valid; // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + wire mem_io_bus_write; // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + wire [31:0] mem_io_bus_write_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + wire mem_io_bus_write_strobe_0; // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + wire mem_io_bus_write_strobe_1; // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + wire mem_io_bus_write_strobe_2; // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + wire mem_io_bus_write_strobe_3; // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + wire mem_io_bus_write_valid; // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + wire mem_io_bus_request; // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + wire mem_io_bus_granted; // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + wire mem2wb_clock; // @[src/main/scala/riscv/core/fivestage/CPU.scala 42:22] + wire mem2wb_reset; // @[src/main/scala/riscv/core/fivestage/CPU.scala 42:22] + wire [31:0] mem2wb_io_instruction_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 42:22] + wire [31:0] mem2wb_io_alu_result; // @[src/main/scala/riscv/core/fivestage/CPU.scala 42:22] + wire mem2wb_io_regs_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 42:22] + wire [1:0] mem2wb_io_regs_write_source; // @[src/main/scala/riscv/core/fivestage/CPU.scala 42:22] + wire [31:0] mem2wb_io_regs_write_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 42:22] + wire [31:0] mem2wb_io_memory_read_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 42:22] + wire [31:0] mem2wb_io_csr_read_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 42:22] + wire [31:0] mem2wb_io_output_instruction_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 42:22] + wire [31:0] mem2wb_io_output_alu_result; // @[src/main/scala/riscv/core/fivestage/CPU.scala 42:22] + wire mem2wb_io_output_regs_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 42:22] + wire [1:0] mem2wb_io_output_regs_write_source; // @[src/main/scala/riscv/core/fivestage/CPU.scala 42:22] + wire [31:0] mem2wb_io_output_regs_write_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 42:22] + wire [31:0] mem2wb_io_output_memory_read_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 42:22] + wire [31:0] mem2wb_io_output_csr_read_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 42:22] + wire [31:0] wb_io_instruction_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 43:18] + wire [31:0] wb_io_alu_result; // @[src/main/scala/riscv/core/fivestage/CPU.scala 43:18] + wire [31:0] wb_io_memory_read_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 43:18] + wire [1:0] wb_io_regs_write_source; // @[src/main/scala/riscv/core/fivestage/CPU.scala 43:18] + wire [31:0] wb_io_csr_read_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 43:18] + wire [31:0] wb_io_regs_write_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 43:18] + wire [4:0] forwarding_io_rs1_id; // @[src/main/scala/riscv/core/fivestage/CPU.scala 44:26] + wire [4:0] forwarding_io_rs2_id; // @[src/main/scala/riscv/core/fivestage/CPU.scala 44:26] + wire [4:0] forwarding_io_rs1_ex; // @[src/main/scala/riscv/core/fivestage/CPU.scala 44:26] + wire [4:0] forwarding_io_rs2_ex; // @[src/main/scala/riscv/core/fivestage/CPU.scala 44:26] + wire [4:0] forwarding_io_rd_mem; // @[src/main/scala/riscv/core/fivestage/CPU.scala 44:26] + wire forwarding_io_reg_write_enable_mem; // @[src/main/scala/riscv/core/fivestage/CPU.scala 44:26] + wire [4:0] forwarding_io_rd_wb; // @[src/main/scala/riscv/core/fivestage/CPU.scala 44:26] + wire forwarding_io_reg_write_enable_wb; // @[src/main/scala/riscv/core/fivestage/CPU.scala 44:26] + wire [1:0] forwarding_io_reg1_forward_id; // @[src/main/scala/riscv/core/fivestage/CPU.scala 44:26] + wire [1:0] forwarding_io_reg2_forward_id; // @[src/main/scala/riscv/core/fivestage/CPU.scala 44:26] + wire [1:0] forwarding_io_reg1_forward_ex; // @[src/main/scala/riscv/core/fivestage/CPU.scala 44:26] + wire [1:0] forwarding_io_reg2_forward_ex; // @[src/main/scala/riscv/core/fivestage/CPU.scala 44:26] + wire clint_clock; // @[src/main/scala/riscv/core/fivestage/CPU.scala 45:21] + wire clint_reset; // @[src/main/scala/riscv/core/fivestage/CPU.scala 45:21] + wire [31:0] clint_io_interrupt_flag; // @[src/main/scala/riscv/core/fivestage/CPU.scala 45:21] + wire [31:0] clint_io_instruction; // @[src/main/scala/riscv/core/fivestage/CPU.scala 45:21] + wire [31:0] clint_io_instruction_address_if; // @[src/main/scala/riscv/core/fivestage/CPU.scala 45:21] + wire clint_io_exception_signal; // @[src/main/scala/riscv/core/fivestage/CPU.scala 45:21] + wire [31:0] clint_io_instruction_address_cause_exception; // @[src/main/scala/riscv/core/fivestage/CPU.scala 45:21] + wire [31:0] clint_io_exception_cause; // @[src/main/scala/riscv/core/fivestage/CPU.scala 45:21] + wire [31:0] clint_io_exception_val; // @[src/main/scala/riscv/core/fivestage/CPU.scala 45:21] + wire clint_io_exception_token; // @[src/main/scala/riscv/core/fivestage/CPU.scala 45:21] + wire clint_io_jump_flag; // @[src/main/scala/riscv/core/fivestage/CPU.scala 45:21] + wire [31:0] clint_io_jump_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 45:21] + wire [31:0] clint_io_csr_mtvec; // @[src/main/scala/riscv/core/fivestage/CPU.scala 45:21] + wire [31:0] clint_io_csr_mepc; // @[src/main/scala/riscv/core/fivestage/CPU.scala 45:21] + wire [31:0] clint_io_csr_mstatus; // @[src/main/scala/riscv/core/fivestage/CPU.scala 45:21] + wire clint_io_interrupt_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 45:21] + wire clint_io_ctrl_stall_flag; // @[src/main/scala/riscv/core/fivestage/CPU.scala 45:21] + wire clint_io_csr_reg_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 45:21] + wire [11:0] clint_io_csr_reg_write_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 45:21] + wire [31:0] clint_io_csr_reg_write_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 45:21] + wire [31:0] clint_io_id_interrupt_handler_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 45:21] + wire clint_io_id_interrupt_assert; // @[src/main/scala/riscv/core/fivestage/CPU.scala 45:21] + wire csr_regs_clock; // @[src/main/scala/riscv/core/fivestage/CPU.scala 46:24] + wire csr_regs_reset; // @[src/main/scala/riscv/core/fivestage/CPU.scala 46:24] + wire csr_regs_io_reg_write_enable_ex; // @[src/main/scala/riscv/core/fivestage/CPU.scala 46:24] + wire [11:0] csr_regs_io_reg_read_address_id; // @[src/main/scala/riscv/core/fivestage/CPU.scala 46:24] + wire [11:0] csr_regs_io_reg_write_address_ex; // @[src/main/scala/riscv/core/fivestage/CPU.scala 46:24] + wire [31:0] csr_regs_io_reg_write_data_ex; // @[src/main/scala/riscv/core/fivestage/CPU.scala 46:24] + wire csr_regs_io_reg_write_enable_clint; // @[src/main/scala/riscv/core/fivestage/CPU.scala 46:24] + wire [11:0] csr_regs_io_reg_write_address_clint; // @[src/main/scala/riscv/core/fivestage/CPU.scala 46:24] + wire [31:0] csr_regs_io_reg_write_data_clint; // @[src/main/scala/riscv/core/fivestage/CPU.scala 46:24] + wire csr_regs_io_interrupt_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 46:24] + wire csr_regs_io_mmu_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 46:24] + wire [31:0] csr_regs_io_id_reg_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 46:24] + wire csr_regs_io_start_paging; // @[src/main/scala/riscv/core/fivestage/CPU.scala 46:24] + wire [31:0] csr_regs_io_clint_csr_mtvec; // @[src/main/scala/riscv/core/fivestage/CPU.scala 46:24] + wire [31:0] csr_regs_io_clint_csr_mepc; // @[src/main/scala/riscv/core/fivestage/CPU.scala 46:24] + wire [31:0] csr_regs_io_clint_csr_mstatus; // @[src/main/scala/riscv/core/fivestage/CPU.scala 46:24] + wire [31:0] csr_regs_io_mmu_csr_satp; // @[src/main/scala/riscv/core/fivestage/CPU.scala 46:24] + wire axi4_master_clock; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire axi4_master_reset; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire axi4_master_io_channels_write_address_channel_AWVALID; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire axi4_master_io_channels_write_address_channel_AWREADY; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire [31:0] axi4_master_io_channels_write_address_channel_AWADDR; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire axi4_master_io_channels_write_data_channel_WVALID; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire axi4_master_io_channels_write_data_channel_WREADY; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire [31:0] axi4_master_io_channels_write_data_channel_WDATA; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire [3:0] axi4_master_io_channels_write_data_channel_WSTRB; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire axi4_master_io_channels_write_response_channel_BVALID; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire axi4_master_io_channels_write_response_channel_BREADY; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire axi4_master_io_channels_read_address_channel_ARVALID; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire axi4_master_io_channels_read_address_channel_ARREADY; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire [31:0] axi4_master_io_channels_read_address_channel_ARADDR; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire axi4_master_io_channels_read_data_channel_RVALID; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire axi4_master_io_channels_read_data_channel_RREADY; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire [31:0] axi4_master_io_channels_read_data_channel_RDATA; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire [1:0] axi4_master_io_channels_read_data_channel_RRESP; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire axi4_master_io_bundle_read; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire axi4_master_io_bundle_write; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire [31:0] axi4_master_io_bundle_read_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire [31:0] axi4_master_io_bundle_write_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire axi4_master_io_bundle_write_strobe_0; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire axi4_master_io_bundle_write_strobe_1; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire axi4_master_io_bundle_write_strobe_2; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire axi4_master_io_bundle_write_strobe_3; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire [31:0] axi4_master_io_bundle_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire axi4_master_io_bundle_busy; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire axi4_master_io_bundle_read_valid; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire axi4_master_io_bundle_write_valid; // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + wire mmu_clock; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + wire mmu_reset; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + wire [31:0] mmu_io_instructions; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + wire [31:0] mmu_io_instructions_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + wire [19:0] mmu_io_ppn_from_satp; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + wire [31:0] mmu_io_virtual_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + wire mmu_io_mmu_occupied_by_mem; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + wire mmu_io_restart; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + wire mmu_io_restart_done; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + wire mmu_io_pa_valid; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + wire [31:0] mmu_io_pa; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + wire mmu_io_page_fault_signals; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + wire [31:0] mmu_io_va_cause_page_fault; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + wire [31:0] mmu_io_ecause; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + wire [31:0] mmu_io_epc; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + wire mmu_io_page_fault_responed; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + wire mmu_io_bus_read; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + wire [31:0] mmu_io_bus_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + wire [31:0] mmu_io_bus_read_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + wire mmu_io_bus_read_valid; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + wire mmu_io_bus_write; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + wire [31:0] mmu_io_bus_write_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + wire mmu_io_bus_write_strobe_0; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + wire mmu_io_bus_write_strobe_1; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + wire mmu_io_bus_write_strobe_2; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + wire mmu_io_bus_write_strobe_3; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + wire mmu_io_bus_write_valid; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + wire mmu_io_bus_granted; // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + reg [2:0] bus_granted; // @[src/main/scala/riscv/core/fivestage/CPU.scala 58:28] + reg [2:0] mem_access_state; // @[src/main/scala/riscv/core/fivestage/CPU.scala 59:33] + reg [31:0] virtual_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 60:32] + reg [31:0] physical_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 61:33] + reg mmu_restart; // @[src/main/scala/riscv/core/fivestage/CPU.scala 62:28] + reg pending; // @[src/main/scala/riscv/core/fivestage/CPU.scala 63:24] + wire _T_5 = io_instruction_valid & inst_fetch_io_pc_valid; // @[src/main/scala/riscv/core/fivestage/CPU.scala 74:70] + wire [2:0] _GEN_0 = io_instruction_valid & inst_fetch_io_pc_valid ? 3'h1 : mem_access_state; // @[src/main/scala/riscv/core/fivestage/CPU.scala 74:97 75:28 59:33] + wire [2:0] _GEN_1 = io_instruction_valid & inst_fetch_io_pc_valid ? 3'h4 : 3'h0; // @[src/main/scala/riscv/core/fivestage/CPU.scala 67:17 74:97 76:23] + wire [31:0] _GEN_2 = io_instruction_valid & inst_fetch_io_pc_valid ? inst_fetch_io_id_instruction_address : + virtual_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 74:97 77:27 60:32] + wire [2:0] _GEN_3 = mem_io_bus_request ? 3'h2 : _GEN_0; // @[src/main/scala/riscv/core/fivestage/CPU.scala 70:34 71:28] + wire [2:0] _GEN_4 = mem_io_bus_request ? 3'h3 : _GEN_1; // @[src/main/scala/riscv/core/fivestage/CPU.scala 70:34 72:23] + wire [31:0] _GEN_5 = mem_io_bus_request ? ex2mem_io_output_alu_result : _GEN_2; // @[src/main/scala/riscv/core/fivestage/CPU.scala 70:34 73:27] + wire [2:0] _GEN_6 = _T_5 ? 3'h4 : mem_access_state; // @[src/main/scala/riscv/core/fivestage/CPU.scala 84:97 85:28 59:33] + wire [31:0] _GEN_8 = _T_5 ? inst_fetch_io_id_instruction_address : physical_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 84:97 87:28 61:33] + wire [2:0] _GEN_9 = mem_io_bus_request ? 3'h3 : _GEN_6; // @[src/main/scala/riscv/core/fivestage/CPU.scala 80:34 81:28] + wire [31:0] _GEN_10 = mem_io_bus_request ? ex2mem_io_output_alu_result : _GEN_8; // @[src/main/scala/riscv/core/fivestage/CPU.scala 80:34 82:28] + wire [1:0] _GEN_11 = mem_io_bus_request ? 2'h2 : {{1'd0}, _T_5}; // @[src/main/scala/riscv/core/fivestage/CPU.scala 80:34 83:23] + wire [2:0] _GEN_20 = mmu_io_pa_valid ? 3'h3 : mem_access_state; // @[src/main/scala/riscv/core/fivestage/CPU.scala 96:33 97:24 59:33] + wire [2:0] _GEN_21 = mmu_io_pa_valid ? 3'h2 : bus_granted; // @[src/main/scala/riscv/core/fivestage/CPU.scala 96:33 98:19 58:28] + wire [31:0] _GEN_22 = mmu_io_pa_valid ? mmu_io_pa : physical_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 96:33 99:24 61:33] + wire _GEN_27 = mmu_io_restart_done ? 1'h0 : 1'h1; // @[src/main/scala/riscv/core/fivestage/CPU.scala 104:19 105:33 106:21] + wire [2:0] _GEN_28 = mmu_io_restart_done ? 3'h2 : mem_access_state; // @[src/main/scala/riscv/core/fivestage/CPU.scala 105:33 107:26 59:33] + wire [2:0] _GEN_29 = mmu_io_restart_done ? 3'h3 : bus_granted; // @[src/main/scala/riscv/core/fivestage/CPU.scala 105:33 108:21 58:28] + wire [31:0] _GEN_30 = mmu_io_restart_done ? ex2mem_io_output_alu_result : virtual_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 105:33 109:25 60:32] + wire _GEN_31 = mmu_io_restart_done ? 1'h0 : mmu_restart; // @[src/main/scala/riscv/core/fivestage/CPU.scala 113:35 114:23 62:28] + wire _GEN_32 = mmu_io_restart_done ? 1'h0 : pending; // @[src/main/scala/riscv/core/fivestage/CPU.scala 113:35 115:19 63:24] + wire [2:0] _GEN_33 = mmu_io_restart_done ? 3'h1 : mem_access_state; // @[src/main/scala/riscv/core/fivestage/CPU.scala 113:35 116:28 59:33] + wire [2:0] _GEN_34 = mmu_io_restart_done ? 3'h4 : bus_granted; // @[src/main/scala/riscv/core/fivestage/CPU.scala 113:35 117:23 58:28] + wire [31:0] _GEN_35 = mmu_io_restart_done ? inst_fetch_io_id_instruction_address : virtual_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 113:35 118:27 60:32] + wire [2:0] _GEN_36 = ~id_io_if_jump_flag & mmu_io_pa_valid ? 3'h4 : mem_access_state; // @[src/main/scala/riscv/core/fivestage/CPU.scala 121:54 122:28 59:33] + wire [2:0] _GEN_37 = ~id_io_if_jump_flag & mmu_io_pa_valid ? 3'h1 : bus_granted; // @[src/main/scala/riscv/core/fivestage/CPU.scala 121:54 123:23 58:28] + wire [31:0] _GEN_38 = ~id_io_if_jump_flag & mmu_io_pa_valid ? mmu_io_pa : physical_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 121:54 124:28 61:33] + wire _GEN_39 = pending ? _GEN_31 : mmu_restart; // @[src/main/scala/riscv/core/fivestage/CPU.scala 112:21 62:28] + wire _GEN_40 = pending ? _GEN_32 : pending; // @[src/main/scala/riscv/core/fivestage/CPU.scala 112:21 63:24] + wire [2:0] _GEN_41 = pending ? _GEN_33 : _GEN_36; // @[src/main/scala/riscv/core/fivestage/CPU.scala 112:21] + wire [2:0] _GEN_42 = pending ? _GEN_34 : _GEN_37; // @[src/main/scala/riscv/core/fivestage/CPU.scala 112:21] + wire [31:0] _GEN_43 = pending ? _GEN_35 : virtual_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 112:21 60:32] + wire [31:0] _GEN_44 = pending ? physical_address : _GEN_38; // @[src/main/scala/riscv/core/fivestage/CPU.scala 112:21 61:33] + wire _GEN_45 = id_io_if_jump_flag | _GEN_39; // @[src/main/scala/riscv/core/fivestage/CPU.scala 128:32 129:21] + wire _GEN_46 = id_io_if_jump_flag | _GEN_40; // @[src/main/scala/riscv/core/fivestage/CPU.scala 128:32 130:17] + wire _GEN_47 = mem_io_bus_request ? _GEN_27 : _GEN_45; // @[src/main/scala/riscv/core/fivestage/CPU.scala 103:30] + wire [2:0] _GEN_48 = mem_io_bus_request ? _GEN_28 : _GEN_41; // @[src/main/scala/riscv/core/fivestage/CPU.scala 103:30] + wire [2:0] _GEN_49 = mem_io_bus_request ? _GEN_29 : _GEN_42; // @[src/main/scala/riscv/core/fivestage/CPU.scala 103:30] + wire [31:0] _GEN_50 = mem_io_bus_request ? _GEN_30 : _GEN_43; // @[src/main/scala/riscv/core/fivestage/CPU.scala 103:30] + wire _GEN_51 = mem_io_bus_request ? pending : _GEN_46; // @[src/main/scala/riscv/core/fivestage/CPU.scala 103:30 63:24] + wire [31:0] _GEN_52 = mem_io_bus_request ? physical_address : _GEN_44; // @[src/main/scala/riscv/core/fivestage/CPU.scala 103:30 61:33] + wire [2:0] _GEN_53 = mem_io_bus_read_valid | mem_io_bus_write_valid ? 3'h0 : mem_access_state; // @[src/main/scala/riscv/core/fivestage/CPU.scala 134:59 135:24 59:33] + wire [2:0] _GEN_54 = mem_io_bus_read_valid | mem_io_bus_write_valid ? 3'h0 : bus_granted; // @[src/main/scala/riscv/core/fivestage/CPU.scala 134:59 136:19 58:28] + wire [2:0] _GEN_55 = inst_fetch_io_bus_read_valid ? 3'h0 : bus_granted; // @[src/main/scala/riscv/core/fivestage/CPU.scala 139:40 140:19 58:28] + wire [2:0] _GEN_56 = inst_fetch_io_bus_read_valid ? 3'h0 : mem_access_state; // @[src/main/scala/riscv/core/fivestage/CPU.scala 139:40 141:24 59:33] + wire [2:0] _GEN_57 = mem_access_state == 3'h4 ? _GEN_55 : bus_granted; // @[src/main/scala/riscv/core/fivestage/CPU.scala 138:61 58:28] + wire [2:0] _GEN_58 = mem_access_state == 3'h4 ? _GEN_56 : mem_access_state; // @[src/main/scala/riscv/core/fivestage/CPU.scala 138:61 59:33] + wire [2:0] _GEN_59 = mem_access_state == 3'h3 ? _GEN_53 : _GEN_58; // @[src/main/scala/riscv/core/fivestage/CPU.scala 133:62] + wire [2:0] _GEN_60 = mem_access_state == 3'h3 ? _GEN_54 : _GEN_57; // @[src/main/scala/riscv/core/fivestage/CPU.scala 133:62] + wire _T_15 = bus_granted == 3'h4; // @[src/main/scala/riscv/core/fivestage/CPU.scala 145:20] + wire _T_16 = bus_granted == 3'h3; // @[src/main/scala/riscv/core/fivestage/CPU.scala 145:65] + wire _T_17 = bus_granted == 3'h4 | bus_granted == 3'h3; // @[src/main/scala/riscv/core/fivestage/CPU.scala 145:50] + wire _T_18 = bus_granted == 3'h2; // @[src/main/scala/riscv/core/fivestage/CPU.scala 152:26] + wire [31:0] _GEN_79 = bus_granted == 3'h2 ? mem_io_bus_address : inst_fetch_io_bus_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 152:54 153:20 160:20] + wire _GEN_80 = bus_granted == 3'h2 ? mem_io_bus_read : inst_fetch_io_bus_read; // @[src/main/scala/riscv/core/fivestage/CPU.scala 152:54 154:32 161:32] + wire _GEN_81 = bus_granted == 3'h2 & mem_io_bus_write; // @[src/main/scala/riscv/core/fivestage/CPU.scala 152:54 156:33 163:33] + wire [31:0] _GEN_82 = bus_granted == 3'h2 ? mem_io_bus_write_data : 32'h0; // @[src/main/scala/riscv/core/fivestage/CPU.scala 152:54 157:38 164:38] + wire _GEN_83 = bus_granted == 3'h2 & mem_io_bus_write_strobe_0; // @[src/main/scala/riscv/core/fivestage/CPU.scala 152:54 158:40 165:40] + wire _GEN_84 = bus_granted == 3'h2 & mem_io_bus_write_strobe_1; // @[src/main/scala/riscv/core/fivestage/CPU.scala 152:54 158:40 165:40] + wire _GEN_85 = bus_granted == 3'h2 & mem_io_bus_write_strobe_2; // @[src/main/scala/riscv/core/fivestage/CPU.scala 152:54 158:40 165:40] + wire _GEN_86 = bus_granted == 3'h2 & mem_io_bus_write_strobe_3; // @[src/main/scala/riscv/core/fivestage/CPU.scala 152:54 158:40 165:40] + wire _inst_fetch_io_bus_read_valid_T_1 = bus_granted == 3'h1 & io_instruction_valid; // @[src/main/scala/riscv/core/fivestage/CPU.scala 169:43] + Control ctrl ( // @[src/main/scala/riscv/core/fivestage/CPU.scala 33:20] + .io_jump_flag(ctrl_io_jump_flag), + .io_jump_instruction_id(ctrl_io_jump_instruction_id), + .io_stall_flag_if(ctrl_io_stall_flag_if), + .io_stall_flag_mem(ctrl_io_stall_flag_mem), + .io_stall_flag_clint(ctrl_io_stall_flag_clint), + .io_stall_flag_bus(ctrl_io_stall_flag_bus), + .io_rs1_id(ctrl_io_rs1_id), + .io_rs2_id(ctrl_io_rs2_id), + .io_memory_read_enable_ex(ctrl_io_memory_read_enable_ex), + .io_rd_ex(ctrl_io_rd_ex), + .io_memory_read_enable_mem(ctrl_io_memory_read_enable_mem), + .io_rd_mem(ctrl_io_rd_mem), + .io_csr_start_paging(ctrl_io_csr_start_paging), + .io_if_flush(ctrl_io_if_flush), + .io_id_flush(ctrl_io_id_flush), + .io_pc_stall(ctrl_io_pc_stall), + .io_if_stall(ctrl_io_if_stall), + .io_id_stall(ctrl_io_id_stall), + .io_ex_stall(ctrl_io_ex_stall) + ); + RegisterFile regs ( // @[src/main/scala/riscv/core/fivestage/CPU.scala 34:20] + .clock(regs_clock), + .reset(regs_reset), + .io_write_enable(regs_io_write_enable), + .io_write_address(regs_io_write_address), + .io_write_data(regs_io_write_data), + .io_read_address1(regs_io_read_address1), + .io_read_address2(regs_io_read_address2), + .io_read_data1(regs_io_read_data1), + .io_read_data2(regs_io_read_data2) + ); + InstructionFetch inst_fetch ( // @[src/main/scala/riscv/core/fivestage/CPU.scala 35:26] + .clock(inst_fetch_clock), + .reset(inst_fetch_reset), + .io_stall_flag_ctrl(inst_fetch_io_stall_flag_ctrl), + .io_jump_flag_id(inst_fetch_io_jump_flag_id), + .io_jump_address_id(inst_fetch_io_jump_address_id), + .io_physical_address(inst_fetch_io_physical_address), + .io_ctrl_stall_flag(inst_fetch_io_ctrl_stall_flag), + .io_id_instruction_address(inst_fetch_io_id_instruction_address), + .io_id_instruction(inst_fetch_io_id_instruction), + .io_pc_valid(inst_fetch_io_pc_valid), + .io_bus_read(inst_fetch_io_bus_read), + .io_bus_address(inst_fetch_io_bus_address), + .io_bus_read_data(inst_fetch_io_bus_read_data), + .io_bus_read_valid(inst_fetch_io_bus_read_valid), + .io_bus_granted(inst_fetch_io_bus_granted) + ); + IF2ID if2id ( // @[src/main/scala/riscv/core/fivestage/CPU.scala 36:21] + .clock(if2id_clock), + .reset(if2id_reset), + .io_stall_flag(if2id_io_stall_flag), + .io_flush_enable(if2id_io_flush_enable), + .io_instruction(if2id_io_instruction), + .io_instruction_address(if2id_io_instruction_address), + .io_interrupt_flag(if2id_io_interrupt_flag), + .io_output_instruction(if2id_io_output_instruction), + .io_output_instruction_address(if2id_io_output_instruction_address), + .io_output_interrupt_flag(if2id_io_output_interrupt_flag) + ); + InstructionDecode id ( // @[src/main/scala/riscv/core/fivestage/CPU.scala 37:18] + .io_instruction(id_io_instruction), + .io_instruction_address(id_io_instruction_address), + .io_reg1_data(id_io_reg1_data), + .io_reg2_data(id_io_reg2_data), + .io_forward_from_mem(id_io_forward_from_mem), + .io_forward_from_wb(id_io_forward_from_wb), + .io_reg1_forward(id_io_reg1_forward), + .io_reg2_forward(id_io_reg2_forward), + .io_interrupt_assert(id_io_interrupt_assert), + .io_interrupt_handler_address(id_io_interrupt_handler_address), + .io_regs_reg1_read_address(id_io_regs_reg1_read_address), + .io_regs_reg2_read_address(id_io_regs_reg2_read_address), + .io_ex_immediate(id_io_ex_immediate), + .io_ex_aluop1_source(id_io_ex_aluop1_source), + .io_ex_aluop2_source(id_io_ex_aluop2_source), + .io_ex_memory_read_enable(id_io_ex_memory_read_enable), + .io_ex_memory_write_enable(id_io_ex_memory_write_enable), + .io_ex_reg_write_source(id_io_ex_reg_write_source), + .io_ex_reg_write_enable(id_io_ex_reg_write_enable), + .io_ex_reg_write_address(id_io_ex_reg_write_address), + .io_ex_csr_address(id_io_ex_csr_address), + .io_ex_csr_write_enable(id_io_ex_csr_write_enable), + .io_ctrl_jump_instruction(id_io_ctrl_jump_instruction), + .io_clint_jump_address(id_io_clint_jump_address), + .io_if_jump_flag(id_io_if_jump_flag), + .io_if_jump_address(id_io_if_jump_address) + ); + ID2EX id2ex ( // @[src/main/scala/riscv/core/fivestage/CPU.scala 38:21] + .clock(id2ex_clock), + .reset(id2ex_reset), + .io_stall_flag(id2ex_io_stall_flag), + .io_flush_enable(id2ex_io_flush_enable), + .io_instruction(id2ex_io_instruction), + .io_instruction_address(id2ex_io_instruction_address), + .io_regs_write_enable(id2ex_io_regs_write_enable), + .io_regs_write_address(id2ex_io_regs_write_address), + .io_regs_write_source(id2ex_io_regs_write_source), + .io_reg1_data(id2ex_io_reg1_data), + .io_reg2_data(id2ex_io_reg2_data), + .io_immediate(id2ex_io_immediate), + .io_aluop1_source(id2ex_io_aluop1_source), + .io_aluop2_source(id2ex_io_aluop2_source), + .io_csr_write_enable(id2ex_io_csr_write_enable), + .io_csr_address(id2ex_io_csr_address), + .io_memory_read_enable(id2ex_io_memory_read_enable), + .io_memory_write_enable(id2ex_io_memory_write_enable), + .io_csr_read_data(id2ex_io_csr_read_data), + .io_output_instruction(id2ex_io_output_instruction), + .io_output_instruction_address(id2ex_io_output_instruction_address), + .io_output_regs_write_enable(id2ex_io_output_regs_write_enable), + .io_output_regs_write_address(id2ex_io_output_regs_write_address), + .io_output_regs_write_source(id2ex_io_output_regs_write_source), + .io_output_reg1_data(id2ex_io_output_reg1_data), + .io_output_reg2_data(id2ex_io_output_reg2_data), + .io_output_immediate(id2ex_io_output_immediate), + .io_output_aluop1_source(id2ex_io_output_aluop1_source), + .io_output_aluop2_source(id2ex_io_output_aluop2_source), + .io_output_csr_write_enable(id2ex_io_output_csr_write_enable), + .io_output_csr_address(id2ex_io_output_csr_address), + .io_output_memory_read_enable(id2ex_io_output_memory_read_enable), + .io_output_memory_write_enable(id2ex_io_output_memory_write_enable), + .io_output_csr_read_data(id2ex_io_output_csr_read_data) + ); + Execute ex ( // @[src/main/scala/riscv/core/fivestage/CPU.scala 39:18] + .io_instruction(ex_io_instruction), + .io_instruction_address(ex_io_instruction_address), + .io_reg1_data(ex_io_reg1_data), + .io_reg2_data(ex_io_reg2_data), + .io_immediate(ex_io_immediate), + .io_aluop1_source(ex_io_aluop1_source), + .io_aluop2_source(ex_io_aluop2_source), + .io_csr_read_data(ex_io_csr_read_data), + .io_forward_from_mem(ex_io_forward_from_mem), + .io_forward_from_wb(ex_io_forward_from_wb), + .io_reg1_forward(ex_io_reg1_forward), + .io_reg2_forward(ex_io_reg2_forward), + .io_mem_alu_result(ex_io_mem_alu_result), + .io_csr_write_data(ex_io_csr_write_data) + ); + EX2MEM ex2mem ( // @[src/main/scala/riscv/core/fivestage/CPU.scala 40:22] + .clock(ex2mem_clock), + .reset(ex2mem_reset), + .io_stall_flag(ex2mem_io_stall_flag), + .io_regs_write_enable(ex2mem_io_regs_write_enable), + .io_regs_write_source(ex2mem_io_regs_write_source), + .io_regs_write_address(ex2mem_io_regs_write_address), + .io_instruction_address(ex2mem_io_instruction_address), + .io_instruction(ex2mem_io_instruction), + .io_reg1_data(ex2mem_io_reg1_data), + .io_reg2_data(ex2mem_io_reg2_data), + .io_memory_read_enable(ex2mem_io_memory_read_enable), + .io_memory_write_enable(ex2mem_io_memory_write_enable), + .io_alu_result(ex2mem_io_alu_result), + .io_csr_read_data(ex2mem_io_csr_read_data), + .io_output_regs_write_enable(ex2mem_io_output_regs_write_enable), + .io_output_regs_write_source(ex2mem_io_output_regs_write_source), + .io_output_regs_write_address(ex2mem_io_output_regs_write_address), + .io_output_instruction_address(ex2mem_io_output_instruction_address), + .io_output_instruction(ex2mem_io_output_instruction), + .io_output_reg2_data(ex2mem_io_output_reg2_data), + .io_output_memory_read_enable(ex2mem_io_output_memory_read_enable), + .io_output_memory_write_enable(ex2mem_io_output_memory_write_enable), + .io_output_alu_result(ex2mem_io_output_alu_result), + .io_output_csr_read_data(ex2mem_io_output_csr_read_data) + ); + MemoryAccess mem ( // @[src/main/scala/riscv/core/fivestage/CPU.scala 41:19] + .clock(mem_clock), + .reset(mem_reset), + .io_alu_result(mem_io_alu_result), + .io_reg2_data(mem_io_reg2_data), + .io_memory_read_enable(mem_io_memory_read_enable), + .io_memory_write_enable(mem_io_memory_write_enable), + .io_funct3(mem_io_funct3), + .io_regs_write_source(mem_io_regs_write_source), + .io_csr_read_data(mem_io_csr_read_data), + .io_clint_exception_token(mem_io_clint_exception_token), + .io_wb_memory_read_data(mem_io_wb_memory_read_data), + .io_ctrl_stall_flag(mem_io_ctrl_stall_flag), + .io_forward_data(mem_io_forward_data), + .io_physical_address(mem_io_physical_address), + .io_bus_read(mem_io_bus_read), + .io_bus_address(mem_io_bus_address), + .io_bus_read_data(mem_io_bus_read_data), + .io_bus_read_valid(mem_io_bus_read_valid), + .io_bus_write(mem_io_bus_write), + .io_bus_write_data(mem_io_bus_write_data), + .io_bus_write_strobe_0(mem_io_bus_write_strobe_0), + .io_bus_write_strobe_1(mem_io_bus_write_strobe_1), + .io_bus_write_strobe_2(mem_io_bus_write_strobe_2), + .io_bus_write_strobe_3(mem_io_bus_write_strobe_3), + .io_bus_write_valid(mem_io_bus_write_valid), + .io_bus_request(mem_io_bus_request), + .io_bus_granted(mem_io_bus_granted) + ); + MEM2WB mem2wb ( // @[src/main/scala/riscv/core/fivestage/CPU.scala 42:22] + .clock(mem2wb_clock), + .reset(mem2wb_reset), + .io_instruction_address(mem2wb_io_instruction_address), + .io_alu_result(mem2wb_io_alu_result), + .io_regs_write_enable(mem2wb_io_regs_write_enable), + .io_regs_write_source(mem2wb_io_regs_write_source), + .io_regs_write_address(mem2wb_io_regs_write_address), + .io_memory_read_data(mem2wb_io_memory_read_data), + .io_csr_read_data(mem2wb_io_csr_read_data), + .io_output_instruction_address(mem2wb_io_output_instruction_address), + .io_output_alu_result(mem2wb_io_output_alu_result), + .io_output_regs_write_enable(mem2wb_io_output_regs_write_enable), + .io_output_regs_write_source(mem2wb_io_output_regs_write_source), + .io_output_regs_write_address(mem2wb_io_output_regs_write_address), + .io_output_memory_read_data(mem2wb_io_output_memory_read_data), + .io_output_csr_read_data(mem2wb_io_output_csr_read_data) + ); + WriteBack wb ( // @[src/main/scala/riscv/core/fivestage/CPU.scala 43:18] + .io_instruction_address(wb_io_instruction_address), + .io_alu_result(wb_io_alu_result), + .io_memory_read_data(wb_io_memory_read_data), + .io_regs_write_source(wb_io_regs_write_source), + .io_csr_read_data(wb_io_csr_read_data), + .io_regs_write_data(wb_io_regs_write_data) + ); + Forwarding forwarding ( // @[src/main/scala/riscv/core/fivestage/CPU.scala 44:26] + .io_rs1_id(forwarding_io_rs1_id), + .io_rs2_id(forwarding_io_rs2_id), + .io_rs1_ex(forwarding_io_rs1_ex), + .io_rs2_ex(forwarding_io_rs2_ex), + .io_rd_mem(forwarding_io_rd_mem), + .io_reg_write_enable_mem(forwarding_io_reg_write_enable_mem), + .io_rd_wb(forwarding_io_rd_wb), + .io_reg_write_enable_wb(forwarding_io_reg_write_enable_wb), + .io_reg1_forward_id(forwarding_io_reg1_forward_id), + .io_reg2_forward_id(forwarding_io_reg2_forward_id), + .io_reg1_forward_ex(forwarding_io_reg1_forward_ex), + .io_reg2_forward_ex(forwarding_io_reg2_forward_ex) + ); + CLINT clint ( // @[src/main/scala/riscv/core/fivestage/CPU.scala 45:21] + .clock(clint_clock), + .reset(clint_reset), + .io_interrupt_flag(clint_io_interrupt_flag), + .io_instruction(clint_io_instruction), + .io_instruction_address_if(clint_io_instruction_address_if), + .io_exception_signal(clint_io_exception_signal), + .io_instruction_address_cause_exception(clint_io_instruction_address_cause_exception), + .io_exception_cause(clint_io_exception_cause), + .io_exception_val(clint_io_exception_val), + .io_exception_token(clint_io_exception_token), + .io_jump_flag(clint_io_jump_flag), + .io_jump_address(clint_io_jump_address), + .io_csr_mtvec(clint_io_csr_mtvec), + .io_csr_mepc(clint_io_csr_mepc), + .io_csr_mstatus(clint_io_csr_mstatus), + .io_interrupt_enable(clint_io_interrupt_enable), + .io_ctrl_stall_flag(clint_io_ctrl_stall_flag), + .io_csr_reg_write_enable(clint_io_csr_reg_write_enable), + .io_csr_reg_write_address(clint_io_csr_reg_write_address), + .io_csr_reg_write_data(clint_io_csr_reg_write_data), + .io_id_interrupt_handler_address(clint_io_id_interrupt_handler_address), + .io_id_interrupt_assert(clint_io_id_interrupt_assert) + ); + CSR csr_regs ( // @[src/main/scala/riscv/core/fivestage/CPU.scala 46:24] + .clock(csr_regs_clock), + .reset(csr_regs_reset), + .io_reg_write_enable_ex(csr_regs_io_reg_write_enable_ex), + .io_reg_read_address_id(csr_regs_io_reg_read_address_id), + .io_reg_write_address_ex(csr_regs_io_reg_write_address_ex), + .io_reg_write_data_ex(csr_regs_io_reg_write_data_ex), + .io_reg_write_enable_clint(csr_regs_io_reg_write_enable_clint), + .io_reg_write_address_clint(csr_regs_io_reg_write_address_clint), + .io_reg_write_data_clint(csr_regs_io_reg_write_data_clint), + .io_interrupt_enable(csr_regs_io_interrupt_enable), + .io_mmu_enable(csr_regs_io_mmu_enable), + .io_id_reg_data(csr_regs_io_id_reg_data), + .io_start_paging(csr_regs_io_start_paging), + .io_clint_csr_mtvec(csr_regs_io_clint_csr_mtvec), + .io_clint_csr_mepc(csr_regs_io_clint_csr_mepc), + .io_clint_csr_mstatus(csr_regs_io_clint_csr_mstatus), + .io_mmu_csr_satp(csr_regs_io_mmu_csr_satp) + ); + AXI4LiteMaster axi4_master ( // @[src/main/scala/riscv/core/fivestage/CPU.scala 47:27] + .clock(axi4_master_clock), + .reset(axi4_master_reset), + .io_channels_write_address_channel_AWVALID(axi4_master_io_channels_write_address_channel_AWVALID), + .io_channels_write_address_channel_AWREADY(axi4_master_io_channels_write_address_channel_AWREADY), + .io_channels_write_address_channel_AWADDR(axi4_master_io_channels_write_address_channel_AWADDR), + .io_channels_write_data_channel_WVALID(axi4_master_io_channels_write_data_channel_WVALID), + .io_channels_write_data_channel_WREADY(axi4_master_io_channels_write_data_channel_WREADY), + .io_channels_write_data_channel_WDATA(axi4_master_io_channels_write_data_channel_WDATA), + .io_channels_write_data_channel_WSTRB(axi4_master_io_channels_write_data_channel_WSTRB), + .io_channels_write_response_channel_BVALID(axi4_master_io_channels_write_response_channel_BVALID), + .io_channels_write_response_channel_BREADY(axi4_master_io_channels_write_response_channel_BREADY), + .io_channels_read_address_channel_ARVALID(axi4_master_io_channels_read_address_channel_ARVALID), + .io_channels_read_address_channel_ARREADY(axi4_master_io_channels_read_address_channel_ARREADY), + .io_channels_read_address_channel_ARADDR(axi4_master_io_channels_read_address_channel_ARADDR), + .io_channels_read_data_channel_RVALID(axi4_master_io_channels_read_data_channel_RVALID), + .io_channels_read_data_channel_RREADY(axi4_master_io_channels_read_data_channel_RREADY), + .io_channels_read_data_channel_RDATA(axi4_master_io_channels_read_data_channel_RDATA), + .io_channels_read_data_channel_RRESP(axi4_master_io_channels_read_data_channel_RRESP), + .io_bundle_read(axi4_master_io_bundle_read), + .io_bundle_write(axi4_master_io_bundle_write), + .io_bundle_read_data(axi4_master_io_bundle_read_data), + .io_bundle_write_data(axi4_master_io_bundle_write_data), + .io_bundle_write_strobe_0(axi4_master_io_bundle_write_strobe_0), + .io_bundle_write_strobe_1(axi4_master_io_bundle_write_strobe_1), + .io_bundle_write_strobe_2(axi4_master_io_bundle_write_strobe_2), + .io_bundle_write_strobe_3(axi4_master_io_bundle_write_strobe_3), + .io_bundle_address(axi4_master_io_bundle_address), + .io_bundle_busy(axi4_master_io_bundle_busy), + .io_bundle_read_valid(axi4_master_io_bundle_read_valid), + .io_bundle_write_valid(axi4_master_io_bundle_write_valid) + ); + MMU mmu ( // @[src/main/scala/riscv/core/fivestage/CPU.scala 48:19] + .clock(mmu_clock), + .reset(mmu_reset), + .io_instructions(mmu_io_instructions), + .io_instructions_address(mmu_io_instructions_address), + .io_ppn_from_satp(mmu_io_ppn_from_satp), + .io_virtual_address(mmu_io_virtual_address), + .io_mmu_occupied_by_mem(mmu_io_mmu_occupied_by_mem), + .io_restart(mmu_io_restart), + .io_restart_done(mmu_io_restart_done), + .io_pa_valid(mmu_io_pa_valid), + .io_pa(mmu_io_pa), + .io_page_fault_signals(mmu_io_page_fault_signals), + .io_va_cause_page_fault(mmu_io_va_cause_page_fault), + .io_ecause(mmu_io_ecause), + .io_epc(mmu_io_epc), + .io_page_fault_responed(mmu_io_page_fault_responed), + .io_bus_read(mmu_io_bus_read), + .io_bus_address(mmu_io_bus_address), + .io_bus_read_data(mmu_io_bus_read_data), + .io_bus_read_valid(mmu_io_bus_read_valid), + .io_bus_write(mmu_io_bus_write), + .io_bus_write_data(mmu_io_bus_write_data), + .io_bus_write_strobe_0(mmu_io_bus_write_strobe_0), + .io_bus_write_strobe_1(mmu_io_bus_write_strobe_1), + .io_bus_write_strobe_2(mmu_io_bus_write_strobe_2), + .io_bus_write_strobe_3(mmu_io_bus_write_strobe_3), + .io_bus_write_valid(mmu_io_bus_write_valid), + .io_bus_granted(mmu_io_bus_granted) + ); + assign io_axi4_channels_write_address_channel_AWVALID = axi4_master_io_channels_write_address_channel_AWVALID; // @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + assign io_axi4_channels_write_address_channel_AWADDR = axi4_master_io_channels_write_address_channel_AWADDR; // @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + assign io_axi4_channels_write_data_channel_WVALID = axi4_master_io_channels_write_data_channel_WVALID; // @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + assign io_axi4_channels_write_data_channel_WDATA = axi4_master_io_channels_write_data_channel_WDATA; // @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + assign io_axi4_channels_write_data_channel_WSTRB = axi4_master_io_channels_write_data_channel_WSTRB; // @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + assign io_axi4_channels_write_response_channel_BREADY = axi4_master_io_channels_write_response_channel_BREADY; // @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + assign io_axi4_channels_read_address_channel_ARVALID = axi4_master_io_channels_read_address_channel_ARVALID; // @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + assign io_axi4_channels_read_address_channel_ARADDR = axi4_master_io_channels_read_address_channel_ARADDR; // @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + assign io_axi4_channels_read_data_channel_RREADY = axi4_master_io_channels_read_data_channel_RREADY; // @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + assign io_bus_address = bus_granted == 3'h4 | bus_granted == 3'h3 ? mmu_io_bus_address : _GEN_79; // @[src/main/scala/riscv/core/fivestage/CPU.scala 145:97 146:20] + assign ctrl_io_jump_flag = id_io_if_jump_flag; // @[src/main/scala/riscv/core/fivestage/CPU.scala 241:21] + assign ctrl_io_jump_instruction_id = id_io_ctrl_jump_instruction; // @[src/main/scala/riscv/core/fivestage/CPU.scala 242:31] + assign ctrl_io_stall_flag_if = inst_fetch_io_ctrl_stall_flag; // @[src/main/scala/riscv/core/fivestage/CPU.scala 243:25] + assign ctrl_io_stall_flag_mem = mem_io_ctrl_stall_flag; // @[src/main/scala/riscv/core/fivestage/CPU.scala 244:26] + assign ctrl_io_stall_flag_clint = clint_io_ctrl_stall_flag; // @[src/main/scala/riscv/core/fivestage/CPU.scala 245:28] + assign ctrl_io_stall_flag_bus = io_stall_flag_bus; // @[src/main/scala/riscv/core/fivestage/CPU.scala 246:26] + assign ctrl_io_rs1_id = id_io_regs_reg1_read_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 247:18] + assign ctrl_io_rs2_id = id_io_regs_reg2_read_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 248:18] + assign ctrl_io_memory_read_enable_ex = id2ex_io_output_memory_read_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 249:33] + assign ctrl_io_rd_ex = id2ex_io_output_regs_write_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 250:17] + assign ctrl_io_memory_read_enable_mem = ex2mem_io_output_memory_read_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 251:34] + assign ctrl_io_rd_mem = ex2mem_io_output_regs_write_address[4:0]; // @[src/main/scala/riscv/core/fivestage/CPU.scala 252:18] + assign ctrl_io_csr_start_paging = csr_regs_io_start_paging; // @[src/main/scala/riscv/core/fivestage/CPU.scala 253:28] + assign regs_clock = clock; + assign regs_reset = reset; + assign regs_io_write_enable = mem2wb_io_output_regs_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 255:24] + assign regs_io_write_address = mem2wb_io_output_regs_write_address[4:0]; // @[src/main/scala/riscv/core/fivestage/CPU.scala 256:25] + assign regs_io_write_data = wb_io_regs_write_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 257:22] + assign regs_io_read_address1 = id_io_regs_reg1_read_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 258:25] + assign regs_io_read_address2 = id_io_regs_reg2_read_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 259:25] + assign inst_fetch_clock = clock; + assign inst_fetch_reset = reset; + assign inst_fetch_io_stall_flag_ctrl = ctrl_io_pc_stall; // @[src/main/scala/riscv/core/fivestage/CPU.scala 264:33] + assign inst_fetch_io_jump_flag_id = id_io_if_jump_flag; // @[src/main/scala/riscv/core/fivestage/CPU.scala 265:30] + assign inst_fetch_io_jump_address_id = id_io_if_jump_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 266:33] + assign inst_fetch_io_physical_address = physical_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 236:34] + assign inst_fetch_io_bus_read_data = _inst_fetch_io_bus_read_valid_T_1 ? axi4_master_io_bundle_read_data : 32'h0; // @[src/main/scala/riscv/core/fivestage/CPU.scala 173:37] + assign inst_fetch_io_bus_read_valid = _inst_fetch_io_bus_read_valid_T_1 & axi4_master_io_bundle_read_valid; // @[src/main/scala/riscv/core/fivestage/CPU.scala 168:38] + assign inst_fetch_io_bus_granted = bus_granted == 3'h1; // @[src/main/scala/riscv/core/fivestage/CPU.scala 235:44] + assign if2id_clock = clock; + assign if2id_reset = reset; + assign if2id_io_stall_flag = ctrl_io_if_stall; // @[src/main/scala/riscv/core/fivestage/CPU.scala 268:23] + assign if2id_io_flush_enable = ctrl_io_if_flush; // @[src/main/scala/riscv/core/fivestage/CPU.scala 269:25] + assign if2id_io_instruction = inst_fetch_io_id_instruction; // @[src/main/scala/riscv/core/fivestage/CPU.scala 270:24] + assign if2id_io_instruction_address = inst_fetch_io_id_instruction_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 271:32] + assign if2id_io_interrupt_flag = io_interrupt_flag; // @[src/main/scala/riscv/core/fivestage/CPU.scala 272:27] + assign id_io_instruction = if2id_io_output_instruction; // @[src/main/scala/riscv/core/fivestage/CPU.scala 274:21] + assign id_io_instruction_address = if2id_io_output_instruction_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 275:29] + assign id_io_reg1_data = regs_io_read_data1; // @[src/main/scala/riscv/core/fivestage/CPU.scala 276:19] + assign id_io_reg2_data = regs_io_read_data2; // @[src/main/scala/riscv/core/fivestage/CPU.scala 277:19] + assign id_io_forward_from_mem = mem_io_forward_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 278:26] + assign id_io_forward_from_wb = wb_io_regs_write_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 279:25] + assign id_io_reg1_forward = forwarding_io_reg1_forward_id; // @[src/main/scala/riscv/core/fivestage/CPU.scala 280:22] + assign id_io_reg2_forward = forwarding_io_reg2_forward_id; // @[src/main/scala/riscv/core/fivestage/CPU.scala 281:22] + assign id_io_interrupt_assert = clint_io_id_interrupt_assert; // @[src/main/scala/riscv/core/fivestage/CPU.scala 282:26] + assign id_io_interrupt_handler_address = clint_io_id_interrupt_handler_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 283:35] + assign id2ex_clock = clock; + assign id2ex_reset = reset; + assign id2ex_io_stall_flag = ctrl_io_id_stall; // @[src/main/scala/riscv/core/fivestage/CPU.scala 285:23] + assign id2ex_io_flush_enable = ctrl_io_id_flush; // @[src/main/scala/riscv/core/fivestage/CPU.scala 286:25] + assign id2ex_io_instruction = if2id_io_output_instruction; // @[src/main/scala/riscv/core/fivestage/CPU.scala 287:24] + assign id2ex_io_instruction_address = if2id_io_output_instruction_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 288:32] + assign id2ex_io_regs_write_enable = id_io_ex_reg_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 289:30] + assign id2ex_io_regs_write_address = id_io_ex_reg_write_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 290:31] + assign id2ex_io_regs_write_source = id_io_ex_reg_write_source; // @[src/main/scala/riscv/core/fivestage/CPU.scala 291:30] + assign id2ex_io_reg1_data = regs_io_read_data1; // @[src/main/scala/riscv/core/fivestage/CPU.scala 292:22] + assign id2ex_io_reg2_data = regs_io_read_data2; // @[src/main/scala/riscv/core/fivestage/CPU.scala 293:22] + assign id2ex_io_immediate = id_io_ex_immediate; // @[src/main/scala/riscv/core/fivestage/CPU.scala 294:22] + assign id2ex_io_aluop1_source = id_io_ex_aluop1_source; // @[src/main/scala/riscv/core/fivestage/CPU.scala 295:26] + assign id2ex_io_aluop2_source = id_io_ex_aluop2_source; // @[src/main/scala/riscv/core/fivestage/CPU.scala 296:26] + assign id2ex_io_csr_write_enable = id_io_ex_csr_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 297:29] + assign id2ex_io_csr_address = id_io_ex_csr_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 298:24] + assign id2ex_io_memory_read_enable = id_io_ex_memory_read_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 299:31] + assign id2ex_io_memory_write_enable = id_io_ex_memory_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 300:32] + assign id2ex_io_csr_read_data = csr_regs_io_id_reg_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 301:26] + assign ex_io_instruction = id2ex_io_output_instruction; // @[src/main/scala/riscv/core/fivestage/CPU.scala 303:21] + assign ex_io_instruction_address = id2ex_io_output_instruction_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 304:29] + assign ex_io_reg1_data = id2ex_io_output_reg1_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 305:19] + assign ex_io_reg2_data = id2ex_io_output_reg2_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 306:19] + assign ex_io_immediate = id2ex_io_output_immediate; // @[src/main/scala/riscv/core/fivestage/CPU.scala 307:19] + assign ex_io_aluop1_source = id2ex_io_output_aluop1_source; // @[src/main/scala/riscv/core/fivestage/CPU.scala 308:23] + assign ex_io_aluop2_source = id2ex_io_output_aluop2_source; // @[src/main/scala/riscv/core/fivestage/CPU.scala 309:23] + assign ex_io_csr_read_data = id2ex_io_output_csr_read_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 310:23] + assign ex_io_forward_from_mem = mem_io_forward_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 311:26] + assign ex_io_forward_from_wb = wb_io_regs_write_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 312:25] + assign ex_io_reg1_forward = forwarding_io_reg1_forward_ex; // @[src/main/scala/riscv/core/fivestage/CPU.scala 313:22] + assign ex_io_reg2_forward = forwarding_io_reg2_forward_ex; // @[src/main/scala/riscv/core/fivestage/CPU.scala 314:22] + assign ex2mem_clock = clock; + assign ex2mem_reset = reset; + assign ex2mem_io_stall_flag = ctrl_io_ex_stall; // @[src/main/scala/riscv/core/fivestage/CPU.scala 316:24] + assign ex2mem_io_regs_write_enable = id2ex_io_output_regs_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 318:31] + assign ex2mem_io_regs_write_source = id2ex_io_output_regs_write_source; // @[src/main/scala/riscv/core/fivestage/CPU.scala 319:31] + assign ex2mem_io_regs_write_address = {{27'd0}, id2ex_io_output_regs_write_address}; // @[src/main/scala/riscv/core/fivestage/CPU.scala 320:32] + assign ex2mem_io_instruction_address = id2ex_io_output_instruction_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 321:33] + assign ex2mem_io_instruction = id2ex_io_output_instruction; // @[src/main/scala/riscv/core/fivestage/CPU.scala 322:25] + assign ex2mem_io_reg1_data = id2ex_io_output_reg1_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 323:23] + assign ex2mem_io_reg2_data = id2ex_io_output_reg2_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 324:23] + assign ex2mem_io_memory_read_enable = id2ex_io_output_memory_read_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 325:32] + assign ex2mem_io_memory_write_enable = id2ex_io_output_memory_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 326:33] + assign ex2mem_io_alu_result = ex_io_mem_alu_result; // @[src/main/scala/riscv/core/fivestage/CPU.scala 327:24] + assign ex2mem_io_csr_read_data = id2ex_io_output_csr_read_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 328:27] + assign mem_clock = clock; + assign mem_reset = reset; + assign mem_io_alu_result = ex2mem_io_output_alu_result; // @[src/main/scala/riscv/core/fivestage/CPU.scala 330:21] + assign mem_io_reg2_data = ex2mem_io_output_reg2_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 331:20] + assign mem_io_memory_read_enable = ex2mem_io_output_memory_read_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 332:29] + assign mem_io_memory_write_enable = ex2mem_io_output_memory_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 333:30] + assign mem_io_funct3 = ex2mem_io_output_instruction[14:12]; // @[src/main/scala/riscv/core/fivestage/CPU.scala 334:48] + assign mem_io_regs_write_source = ex2mem_io_output_regs_write_source; // @[src/main/scala/riscv/core/fivestage/CPU.scala 335:28] + assign mem_io_csr_read_data = ex2mem_io_output_csr_read_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 336:24] + assign mem_io_clint_exception_token = clint_io_exception_token; // @[src/main/scala/riscv/core/fivestage/CPU.scala 337:32] + assign mem_io_physical_address = physical_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 239:27] + assign mem_io_bus_read_data = _T_18 ? axi4_master_io_bundle_read_data : 32'h0; // @[src/main/scala/riscv/core/fivestage/CPU.scala 189:30] + assign mem_io_bus_read_valid = _T_18 & axi4_master_io_bundle_read_valid; // @[src/main/scala/riscv/core/fivestage/CPU.scala 184:31] + assign mem_io_bus_write_valid = _T_18 & axi4_master_io_bundle_write_valid; // @[src/main/scala/riscv/core/fivestage/CPU.scala 194:32] + assign mem_io_bus_granted = bus_granted == 3'h2; // @[src/main/scala/riscv/core/fivestage/CPU.scala 238:37] + assign mem2wb_clock = clock; + assign mem2wb_reset = reset; + assign mem2wb_io_instruction_address = ex2mem_io_output_instruction_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 339:33] + assign mem2wb_io_alu_result = ex2mem_io_output_alu_result; // @[src/main/scala/riscv/core/fivestage/CPU.scala 340:24] + assign mem2wb_io_regs_write_enable = ex2mem_io_output_regs_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 341:31] + assign mem2wb_io_regs_write_source = ex2mem_io_output_regs_write_source; // @[src/main/scala/riscv/core/fivestage/CPU.scala 342:31] + assign mem2wb_io_regs_write_address = ex2mem_io_output_regs_write_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 343:32] + assign mem2wb_io_memory_read_data = mem_io_wb_memory_read_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 344:30] + assign mem2wb_io_csr_read_data = ex2mem_io_output_csr_read_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 345:27] + assign wb_io_instruction_address = mem2wb_io_output_instruction_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 347:29] + assign wb_io_alu_result = mem2wb_io_output_alu_result; // @[src/main/scala/riscv/core/fivestage/CPU.scala 348:20] + assign wb_io_memory_read_data = mem2wb_io_output_memory_read_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 349:26] + assign wb_io_regs_write_source = mem2wb_io_output_regs_write_source; // @[src/main/scala/riscv/core/fivestage/CPU.scala 350:27] + assign wb_io_csr_read_data = mem2wb_io_output_csr_read_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 351:23] + assign forwarding_io_rs1_id = id_io_regs_reg1_read_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 353:24] + assign forwarding_io_rs2_id = id_io_regs_reg2_read_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 354:24] + assign forwarding_io_rs1_ex = id2ex_io_output_instruction[19:15]; // @[src/main/scala/riscv/core/fivestage/CPU.scala 355:54] + assign forwarding_io_rs2_ex = id2ex_io_output_instruction[24:20]; // @[src/main/scala/riscv/core/fivestage/CPU.scala 356:54] + assign forwarding_io_rd_mem = ex2mem_io_output_regs_write_address[4:0]; // @[src/main/scala/riscv/core/fivestage/CPU.scala 357:24] + assign forwarding_io_reg_write_enable_mem = ex2mem_io_output_regs_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 358:38] + assign forwarding_io_rd_wb = mem2wb_io_output_regs_write_address[4:0]; // @[src/main/scala/riscv/core/fivestage/CPU.scala 359:23] + assign forwarding_io_reg_write_enable_wb = mem2wb_io_output_regs_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 360:37] + assign clint_clock = clock; + assign clint_reset = reset; + assign clint_io_interrupt_flag = if2id_io_output_interrupt_flag; // @[src/main/scala/riscv/core/fivestage/CPU.scala 370:27] + assign clint_io_instruction = if2id_io_output_instruction; // @[src/main/scala/riscv/core/fivestage/CPU.scala 362:24] + assign clint_io_instruction_address_if = inst_fetch_io_id_instruction_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 363:35] + assign clint_io_exception_signal = mmu_io_page_fault_signals; // @[src/main/scala/riscv/core/fivestage/CPU.scala 372:29] + assign clint_io_instruction_address_cause_exception = mmu_io_epc; // @[src/main/scala/riscv/core/fivestage/CPU.scala 373:48] + assign clint_io_exception_cause = mmu_io_ecause; // @[src/main/scala/riscv/core/fivestage/CPU.scala 375:28] + assign clint_io_exception_val = mmu_io_va_cause_page_fault; // @[src/main/scala/riscv/core/fivestage/CPU.scala 374:26] + assign clint_io_jump_flag = id_io_if_jump_flag; // @[src/main/scala/riscv/core/fivestage/CPU.scala 364:22] + assign clint_io_jump_address = id_io_clint_jump_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 365:25] + assign clint_io_csr_mtvec = csr_regs_io_clint_csr_mtvec; // @[src/main/scala/riscv/core/fivestage/CPU.scala 367:22] + assign clint_io_csr_mepc = csr_regs_io_clint_csr_mepc; // @[src/main/scala/riscv/core/fivestage/CPU.scala 366:21] + assign clint_io_csr_mstatus = csr_regs_io_clint_csr_mstatus; // @[src/main/scala/riscv/core/fivestage/CPU.scala 368:24] + assign clint_io_interrupt_enable = csr_regs_io_interrupt_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 369:29] + assign csr_regs_clock = clock; + assign csr_regs_reset = reset; + assign csr_regs_io_reg_write_enable_ex = id2ex_io_output_csr_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 377:35] + assign csr_regs_io_reg_read_address_id = id_io_ex_csr_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 380:35] + assign csr_regs_io_reg_write_address_ex = id2ex_io_output_csr_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 378:36] + assign csr_regs_io_reg_write_data_ex = ex_io_csr_write_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 379:33] + assign csr_regs_io_reg_write_enable_clint = clint_io_csr_reg_write_enable; // @[src/main/scala/riscv/core/fivestage/CPU.scala 381:38] + assign csr_regs_io_reg_write_address_clint = clint_io_csr_reg_write_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 382:39] + assign csr_regs_io_reg_write_data_clint = clint_io_csr_reg_write_data; // @[src/main/scala/riscv/core/fivestage/CPU.scala 383:36] + assign axi4_master_clock = clock; + assign axi4_master_reset = reset; + assign axi4_master_io_channels_write_address_channel_AWREADY = io_axi4_channels_write_address_channel_AWREADY; // @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + assign axi4_master_io_channels_write_data_channel_WREADY = io_axi4_channels_write_data_channel_WREADY; // @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + assign axi4_master_io_channels_write_response_channel_BVALID = io_axi4_channels_write_response_channel_BVALID; // @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + assign axi4_master_io_channels_read_address_channel_ARREADY = io_axi4_channels_read_address_channel_ARREADY; // @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + assign axi4_master_io_channels_read_data_channel_RVALID = io_axi4_channels_read_data_channel_RVALID; // @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + assign axi4_master_io_channels_read_data_channel_RDATA = io_axi4_channels_read_data_channel_RDATA; // @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + assign axi4_master_io_channels_read_data_channel_RRESP = 2'h0; // @[src/main/scala/riscv/core/fivestage/CPU.scala 49:27] + assign axi4_master_io_bundle_read = bus_granted == 3'h4 | bus_granted == 3'h3 ? mmu_io_bus_read : _GEN_80; // @[src/main/scala/riscv/core/fivestage/CPU.scala 145:97 147:32] + assign axi4_master_io_bundle_write = bus_granted == 3'h4 | bus_granted == 3'h3 ? mmu_io_bus_write : _GEN_81; // @[src/main/scala/riscv/core/fivestage/CPU.scala 145:97 149:33] + assign axi4_master_io_bundle_write_data = bus_granted == 3'h4 | bus_granted == 3'h3 ? mmu_io_bus_write_data : _GEN_82; // @[src/main/scala/riscv/core/fivestage/CPU.scala 145:97 150:38] + assign axi4_master_io_bundle_write_strobe_0 = bus_granted == 3'h4 | bus_granted == 3'h3 ? mmu_io_bus_write_strobe_0 : + _GEN_83; // @[src/main/scala/riscv/core/fivestage/CPU.scala 145:97 151:40] + assign axi4_master_io_bundle_write_strobe_1 = bus_granted == 3'h4 | bus_granted == 3'h3 ? mmu_io_bus_write_strobe_1 : + _GEN_84; // @[src/main/scala/riscv/core/fivestage/CPU.scala 145:97 151:40] + assign axi4_master_io_bundle_write_strobe_2 = bus_granted == 3'h4 | bus_granted == 3'h3 ? mmu_io_bus_write_strobe_2 : + _GEN_85; // @[src/main/scala/riscv/core/fivestage/CPU.scala 145:97 151:40] + assign axi4_master_io_bundle_write_strobe_3 = bus_granted == 3'h4 | bus_granted == 3'h3 ? mmu_io_bus_write_strobe_3 : + _GEN_86; // @[src/main/scala/riscv/core/fivestage/CPU.scala 145:97 151:40] + assign axi4_master_io_bundle_address = bus_granted == 3'h4 | bus_granted == 3'h3 ? mmu_io_bus_address : _GEN_79; // @[src/main/scala/riscv/core/fivestage/CPU.scala 145:97 146:20] + assign mmu_clock = clock; + assign mmu_reset = reset; + assign mmu_io_instructions = ex2mem_io_output_instruction; // @[src/main/scala/riscv/core/fivestage/CPU.scala 225:23] + assign mmu_io_instructions_address = ex2mem_io_output_instruction_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 226:31] + assign mmu_io_ppn_from_satp = csr_regs_io_mmu_csr_satp[19:0]; // @[src/main/scala/riscv/core/fivestage/CPU.scala 230:24] + assign mmu_io_virtual_address = virtual_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 227:26] + assign mmu_io_mmu_occupied_by_mem = bus_granted == 3'h3; // @[src/main/scala/riscv/core/fivestage/CPU.scala 232:45] + assign mmu_io_restart = mmu_restart; // @[src/main/scala/riscv/core/fivestage/CPU.scala 233:18] + assign mmu_io_page_fault_responed = clint_io_exception_token; // @[src/main/scala/riscv/core/fivestage/CPU.scala 231:30] + assign mmu_io_bus_read_data = _T_17 ? axi4_master_io_bundle_read_data : 32'h0; // @[src/main/scala/riscv/core/fivestage/CPU.scala 209:30] + assign mmu_io_bus_read_valid = _T_17 & axi4_master_io_bundle_read_valid; // @[src/main/scala/riscv/core/fivestage/CPU.scala 204:31] + assign mmu_io_bus_write_valid = _T_17 & axi4_master_io_bundle_write_valid; // @[src/main/scala/riscv/core/fivestage/CPU.scala 214:32] + assign mmu_io_bus_granted = _T_16 | _T_15; // @[src/main/scala/riscv/core/fivestage/CPU.scala 228:68] + always @(posedge clock) begin + if (reset) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 58:28] + bus_granted <= 3'h0; // @[src/main/scala/riscv/core/fivestage/CPU.scala 58:28] + end else if (mem_access_state == 3'h0) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 66:50] + if (~axi4_master_io_bundle_busy & ~axi4_master_io_bundle_read_valid) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 68:76] + if (csr_regs_io_mmu_enable) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 69:36] + bus_granted <= _GEN_4; + end else begin + bus_granted <= {{1'd0}, _GEN_11}; + end + end else begin + bus_granted <= 3'h0; // @[src/main/scala/riscv/core/fivestage/CPU.scala 67:17] + end + end else if (mem_access_state == 3'h2) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 91:73] + if (clint_io_exception_token) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 92:36] + bus_granted <= 3'h4; // @[src/main/scala/riscv/core/fivestage/CPU.scala 94:19] + end else begin + bus_granted <= _GEN_21; + end + end else if (mem_access_state == 3'h1) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 101:72] + bus_granted <= _GEN_49; + end else begin + bus_granted <= _GEN_60; + end + if (reset) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 59:33] + mem_access_state <= 3'h0; // @[src/main/scala/riscv/core/fivestage/CPU.scala 59:33] + end else if (mem_access_state == 3'h0) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 66:50] + if (~axi4_master_io_bundle_busy & ~axi4_master_io_bundle_read_valid) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 68:76] + if (csr_regs_io_mmu_enable) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 69:36] + mem_access_state <= _GEN_3; + end else begin + mem_access_state <= _GEN_9; + end + end + end else if (mem_access_state == 3'h2) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 91:73] + if (clint_io_exception_token) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 92:36] + mem_access_state <= 3'h1; // @[src/main/scala/riscv/core/fivestage/CPU.scala 93:24] + end else begin + mem_access_state <= _GEN_20; + end + end else if (mem_access_state == 3'h1) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 101:72] + mem_access_state <= _GEN_48; + end else begin + mem_access_state <= _GEN_59; + end + if (reset) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 60:32] + virtual_address <= 32'h0; // @[src/main/scala/riscv/core/fivestage/CPU.scala 60:32] + end else if (mem_access_state == 3'h0) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 66:50] + if (~axi4_master_io_bundle_busy & ~axi4_master_io_bundle_read_valid) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 68:76] + if (csr_regs_io_mmu_enable) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 69:36] + virtual_address <= _GEN_5; + end + end + end else if (mem_access_state == 3'h2) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 91:73] + if (clint_io_exception_token) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 92:36] + virtual_address <= id_io_if_jump_address; // @[src/main/scala/riscv/core/fivestage/CPU.scala 95:23] + end + end else if (mem_access_state == 3'h1) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 101:72] + virtual_address <= _GEN_50; + end + if (reset) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 61:33] + physical_address <= 32'h0; // @[src/main/scala/riscv/core/fivestage/CPU.scala 61:33] + end else if (mem_access_state == 3'h0) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 66:50] + if (~axi4_master_io_bundle_busy & ~axi4_master_io_bundle_read_valid) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 68:76] + if (!(csr_regs_io_mmu_enable)) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 69:36] + physical_address <= _GEN_10; + end + end + end else if (mem_access_state == 3'h2) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 91:73] + if (!(clint_io_exception_token)) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 92:36] + physical_address <= _GEN_22; + end + end else if (mem_access_state == 3'h1) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 101:72] + physical_address <= _GEN_52; + end + if (reset) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 62:28] + mmu_restart <= 1'h0; // @[src/main/scala/riscv/core/fivestage/CPU.scala 62:28] + end else if (!(mem_access_state == 3'h0)) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 66:50] + if (!(mem_access_state == 3'h2)) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 91:73] + if (mem_access_state == 3'h1) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 101:72] + mmu_restart <= _GEN_47; + end + end + end + if (reset) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 63:24] + pending <= 1'h0; // @[src/main/scala/riscv/core/fivestage/CPU.scala 63:24] + end else if (!(mem_access_state == 3'h0)) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 66:50] + if (!(mem_access_state == 3'h2)) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 91:73] + if (mem_access_state == 3'h1) begin // @[src/main/scala/riscv/core/fivestage/CPU.scala 101:72] + pending <= _GEN_51; + end + end + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + bus_granted = _RAND_0[2:0]; + _RAND_1 = {1{`RANDOM}}; + mem_access_state = _RAND_1[2:0]; + _RAND_2 = {1{`RANDOM}}; + virtual_address = _RAND_2[31:0]; + _RAND_3 = {1{`RANDOM}}; + physical_address = _RAND_3[31:0]; + _RAND_4 = {1{`RANDOM}}; + mmu_restart = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + pending = _RAND_5[0:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module CPU_1( + input clock, + input reset, + output io_axi4_channels_write_address_channel_AWVALID, // @[src/main/scala/riscv/core/CPU.scala 23:14] + input io_axi4_channels_write_address_channel_AWREADY, // @[src/main/scala/riscv/core/CPU.scala 23:14] + output [31:0] io_axi4_channels_write_address_channel_AWADDR, // @[src/main/scala/riscv/core/CPU.scala 23:14] + output io_axi4_channels_write_data_channel_WVALID, // @[src/main/scala/riscv/core/CPU.scala 23:14] + input io_axi4_channels_write_data_channel_WREADY, // @[src/main/scala/riscv/core/CPU.scala 23:14] + output [31:0] io_axi4_channels_write_data_channel_WDATA, // @[src/main/scala/riscv/core/CPU.scala 23:14] + output [3:0] io_axi4_channels_write_data_channel_WSTRB, // @[src/main/scala/riscv/core/CPU.scala 23:14] + input io_axi4_channels_write_response_channel_BVALID, // @[src/main/scala/riscv/core/CPU.scala 23:14] + output io_axi4_channels_write_response_channel_BREADY, // @[src/main/scala/riscv/core/CPU.scala 23:14] + output io_axi4_channels_read_address_channel_ARVALID, // @[src/main/scala/riscv/core/CPU.scala 23:14] + input io_axi4_channels_read_address_channel_ARREADY, // @[src/main/scala/riscv/core/CPU.scala 23:14] + output [31:0] io_axi4_channels_read_address_channel_ARADDR, // @[src/main/scala/riscv/core/CPU.scala 23:14] + input io_axi4_channels_read_data_channel_RVALID, // @[src/main/scala/riscv/core/CPU.scala 23:14] + output io_axi4_channels_read_data_channel_RREADY, // @[src/main/scala/riscv/core/CPU.scala 23:14] + input [31:0] io_axi4_channels_read_data_channel_RDATA, // @[src/main/scala/riscv/core/CPU.scala 23:14] + output [31:0] io_bus_address, // @[src/main/scala/riscv/core/CPU.scala 23:14] + input [31:0] io_interrupt_flag, // @[src/main/scala/riscv/core/CPU.scala 23:14] + input io_stall_flag_bus, // @[src/main/scala/riscv/core/CPU.scala 23:14] + input io_instruction_valid // @[src/main/scala/riscv/core/CPU.scala 23:14] +); + wire cpu_clock; // @[src/main/scala/riscv/core/CPU.scala 29:23] + wire cpu_reset; // @[src/main/scala/riscv/core/CPU.scala 29:23] + wire cpu_io_axi4_channels_write_address_channel_AWVALID; // @[src/main/scala/riscv/core/CPU.scala 29:23] + wire cpu_io_axi4_channels_write_address_channel_AWREADY; // @[src/main/scala/riscv/core/CPU.scala 29:23] + wire [31:0] cpu_io_axi4_channels_write_address_channel_AWADDR; // @[src/main/scala/riscv/core/CPU.scala 29:23] + wire cpu_io_axi4_channels_write_data_channel_WVALID; // @[src/main/scala/riscv/core/CPU.scala 29:23] + wire cpu_io_axi4_channels_write_data_channel_WREADY; // @[src/main/scala/riscv/core/CPU.scala 29:23] + wire [31:0] cpu_io_axi4_channels_write_data_channel_WDATA; // @[src/main/scala/riscv/core/CPU.scala 29:23] + wire [3:0] cpu_io_axi4_channels_write_data_channel_WSTRB; // @[src/main/scala/riscv/core/CPU.scala 29:23] + wire cpu_io_axi4_channels_write_response_channel_BVALID; // @[src/main/scala/riscv/core/CPU.scala 29:23] + wire cpu_io_axi4_channels_write_response_channel_BREADY; // @[src/main/scala/riscv/core/CPU.scala 29:23] + wire cpu_io_axi4_channels_read_address_channel_ARVALID; // @[src/main/scala/riscv/core/CPU.scala 29:23] + wire cpu_io_axi4_channels_read_address_channel_ARREADY; // @[src/main/scala/riscv/core/CPU.scala 29:23] + wire [31:0] cpu_io_axi4_channels_read_address_channel_ARADDR; // @[src/main/scala/riscv/core/CPU.scala 29:23] + wire cpu_io_axi4_channels_read_data_channel_RVALID; // @[src/main/scala/riscv/core/CPU.scala 29:23] + wire cpu_io_axi4_channels_read_data_channel_RREADY; // @[src/main/scala/riscv/core/CPU.scala 29:23] + wire [31:0] cpu_io_axi4_channels_read_data_channel_RDATA; // @[src/main/scala/riscv/core/CPU.scala 29:23] + wire [31:0] cpu_io_bus_address; // @[src/main/scala/riscv/core/CPU.scala 29:23] + wire [31:0] cpu_io_interrupt_flag; // @[src/main/scala/riscv/core/CPU.scala 29:23] + wire cpu_io_stall_flag_bus; // @[src/main/scala/riscv/core/CPU.scala 29:23] + wire cpu_io_instruction_valid; // @[src/main/scala/riscv/core/CPU.scala 29:23] + CPU cpu ( // @[src/main/scala/riscv/core/CPU.scala 29:23] + .clock(cpu_clock), + .reset(cpu_reset), + .io_axi4_channels_write_address_channel_AWVALID(cpu_io_axi4_channels_write_address_channel_AWVALID), + .io_axi4_channels_write_address_channel_AWREADY(cpu_io_axi4_channels_write_address_channel_AWREADY), + .io_axi4_channels_write_address_channel_AWADDR(cpu_io_axi4_channels_write_address_channel_AWADDR), + .io_axi4_channels_write_data_channel_WVALID(cpu_io_axi4_channels_write_data_channel_WVALID), + .io_axi4_channels_write_data_channel_WREADY(cpu_io_axi4_channels_write_data_channel_WREADY), + .io_axi4_channels_write_data_channel_WDATA(cpu_io_axi4_channels_write_data_channel_WDATA), + .io_axi4_channels_write_data_channel_WSTRB(cpu_io_axi4_channels_write_data_channel_WSTRB), + .io_axi4_channels_write_response_channel_BVALID(cpu_io_axi4_channels_write_response_channel_BVALID), + .io_axi4_channels_write_response_channel_BREADY(cpu_io_axi4_channels_write_response_channel_BREADY), + .io_axi4_channels_read_address_channel_ARVALID(cpu_io_axi4_channels_read_address_channel_ARVALID), + .io_axi4_channels_read_address_channel_ARREADY(cpu_io_axi4_channels_read_address_channel_ARREADY), + .io_axi4_channels_read_address_channel_ARADDR(cpu_io_axi4_channels_read_address_channel_ARADDR), + .io_axi4_channels_read_data_channel_RVALID(cpu_io_axi4_channels_read_data_channel_RVALID), + .io_axi4_channels_read_data_channel_RREADY(cpu_io_axi4_channels_read_data_channel_RREADY), + .io_axi4_channels_read_data_channel_RDATA(cpu_io_axi4_channels_read_data_channel_RDATA), + .io_bus_address(cpu_io_bus_address), + .io_interrupt_flag(cpu_io_interrupt_flag), + .io_stall_flag_bus(cpu_io_stall_flag_bus), + .io_instruction_valid(cpu_io_instruction_valid) + ); + assign io_axi4_channels_write_address_channel_AWVALID = cpu_io_axi4_channels_write_address_channel_AWVALID; // @[src/main/scala/riscv/core/CPU.scala 30:14] + assign io_axi4_channels_write_address_channel_AWADDR = cpu_io_axi4_channels_write_address_channel_AWADDR; // @[src/main/scala/riscv/core/CPU.scala 30:14] + assign io_axi4_channels_write_data_channel_WVALID = cpu_io_axi4_channels_write_data_channel_WVALID; // @[src/main/scala/riscv/core/CPU.scala 30:14] + assign io_axi4_channels_write_data_channel_WDATA = cpu_io_axi4_channels_write_data_channel_WDATA; // @[src/main/scala/riscv/core/CPU.scala 30:14] + assign io_axi4_channels_write_data_channel_WSTRB = cpu_io_axi4_channels_write_data_channel_WSTRB; // @[src/main/scala/riscv/core/CPU.scala 30:14] + assign io_axi4_channels_write_response_channel_BREADY = cpu_io_axi4_channels_write_response_channel_BREADY; // @[src/main/scala/riscv/core/CPU.scala 30:14] + assign io_axi4_channels_read_address_channel_ARVALID = cpu_io_axi4_channels_read_address_channel_ARVALID; // @[src/main/scala/riscv/core/CPU.scala 30:14] + assign io_axi4_channels_read_address_channel_ARADDR = cpu_io_axi4_channels_read_address_channel_ARADDR; // @[src/main/scala/riscv/core/CPU.scala 30:14] + assign io_axi4_channels_read_data_channel_RREADY = cpu_io_axi4_channels_read_data_channel_RREADY; // @[src/main/scala/riscv/core/CPU.scala 30:14] + assign io_bus_address = cpu_io_bus_address; // @[src/main/scala/riscv/core/CPU.scala 30:14] + assign cpu_clock = clock; + assign cpu_reset = reset; + assign cpu_io_axi4_channels_write_address_channel_AWREADY = io_axi4_channels_write_address_channel_AWREADY; // @[src/main/scala/riscv/core/CPU.scala 30:14] + assign cpu_io_axi4_channels_write_data_channel_WREADY = io_axi4_channels_write_data_channel_WREADY; // @[src/main/scala/riscv/core/CPU.scala 30:14] + assign cpu_io_axi4_channels_write_response_channel_BVALID = io_axi4_channels_write_response_channel_BVALID; // @[src/main/scala/riscv/core/CPU.scala 30:14] + assign cpu_io_axi4_channels_read_address_channel_ARREADY = io_axi4_channels_read_address_channel_ARREADY; // @[src/main/scala/riscv/core/CPU.scala 30:14] + assign cpu_io_axi4_channels_read_data_channel_RVALID = io_axi4_channels_read_data_channel_RVALID; // @[src/main/scala/riscv/core/CPU.scala 30:14] + assign cpu_io_axi4_channels_read_data_channel_RDATA = io_axi4_channels_read_data_channel_RDATA; // @[src/main/scala/riscv/core/CPU.scala 30:14] + assign cpu_io_interrupt_flag = io_interrupt_flag; // @[src/main/scala/riscv/core/CPU.scala 30:14] + assign cpu_io_stall_flag_bus = io_stall_flag_bus; // @[src/main/scala/riscv/core/CPU.scala 30:14] + assign cpu_io_instruction_valid = io_instruction_valid; // @[src/main/scala/riscv/core/CPU.scala 30:14] +endmodule +module BlockRAM( + input clock, + input [31:0] io_read_address, // @[src/main/scala/peripheral/Memory.scala 24:14] + input [31:0] io_write_address, // @[src/main/scala/peripheral/Memory.scala 24:14] + input [31:0] io_write_data, // @[src/main/scala/peripheral/Memory.scala 24:14] + input io_write_enable, // @[src/main/scala/peripheral/Memory.scala 24:14] + input io_write_strobe_0, // @[src/main/scala/peripheral/Memory.scala 24:14] + input io_write_strobe_1, // @[src/main/scala/peripheral/Memory.scala 24:14] + input io_write_strobe_2, // @[src/main/scala/peripheral/Memory.scala 24:14] + input io_write_strobe_3, // @[src/main/scala/peripheral/Memory.scala 24:14] + output [31:0] io_read_data // @[src/main/scala/peripheral/Memory.scala 24:14] +); +`ifdef RANDOMIZE_MEM_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_5; + reg [31:0] _RAND_10; + reg [31:0] _RAND_15; +`endif // RANDOMIZE_MEM_INIT +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; +`endif // RANDOMIZE_REG_INIT + reg [7:0] mem_0 [0:8191]; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire mem_0_io_read_data_MPORT_en; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire [12:0] mem_0_io_read_data_MPORT_addr; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire [7:0] mem_0_io_read_data_MPORT_data; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire mem_0_io_debug_read_data_MPORT_en; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire [12:0] mem_0_io_debug_read_data_MPORT_addr; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire [7:0] mem_0_io_debug_read_data_MPORT_data; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire [7:0] mem_0_MPORT_data; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire [12:0] mem_0_MPORT_addr; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire mem_0_MPORT_mask; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire mem_0_MPORT_en; // @[src/main/scala/peripheral/Memory.scala 36:24] + reg mem_0_io_read_data_MPORT_en_pipe_0; + reg [12:0] mem_0_io_read_data_MPORT_addr_pipe_0; + reg mem_0_io_debug_read_data_MPORT_en_pipe_0; + reg [12:0] mem_0_io_debug_read_data_MPORT_addr_pipe_0; + reg [7:0] mem_1 [0:8191]; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire mem_1_io_read_data_MPORT_en; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire [12:0] mem_1_io_read_data_MPORT_addr; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire [7:0] mem_1_io_read_data_MPORT_data; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire mem_1_io_debug_read_data_MPORT_en; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire [12:0] mem_1_io_debug_read_data_MPORT_addr; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire [7:0] mem_1_io_debug_read_data_MPORT_data; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire [7:0] mem_1_MPORT_data; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire [12:0] mem_1_MPORT_addr; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire mem_1_MPORT_mask; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire mem_1_MPORT_en; // @[src/main/scala/peripheral/Memory.scala 36:24] + reg mem_1_io_read_data_MPORT_en_pipe_0; + reg [12:0] mem_1_io_read_data_MPORT_addr_pipe_0; + reg mem_1_io_debug_read_data_MPORT_en_pipe_0; + reg [12:0] mem_1_io_debug_read_data_MPORT_addr_pipe_0; + reg [7:0] mem_2 [0:8191]; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire mem_2_io_read_data_MPORT_en; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire [12:0] mem_2_io_read_data_MPORT_addr; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire [7:0] mem_2_io_read_data_MPORT_data; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire mem_2_io_debug_read_data_MPORT_en; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire [12:0] mem_2_io_debug_read_data_MPORT_addr; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire [7:0] mem_2_io_debug_read_data_MPORT_data; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire [7:0] mem_2_MPORT_data; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire [12:0] mem_2_MPORT_addr; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire mem_2_MPORT_mask; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire mem_2_MPORT_en; // @[src/main/scala/peripheral/Memory.scala 36:24] + reg mem_2_io_read_data_MPORT_en_pipe_0; + reg [12:0] mem_2_io_read_data_MPORT_addr_pipe_0; + reg mem_2_io_debug_read_data_MPORT_en_pipe_0; + reg [12:0] mem_2_io_debug_read_data_MPORT_addr_pipe_0; + reg [7:0] mem_3 [0:8191]; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire mem_3_io_read_data_MPORT_en; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire [12:0] mem_3_io_read_data_MPORT_addr; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire [7:0] mem_3_io_read_data_MPORT_data; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire mem_3_io_debug_read_data_MPORT_en; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire [12:0] mem_3_io_debug_read_data_MPORT_addr; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire [7:0] mem_3_io_debug_read_data_MPORT_data; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire [7:0] mem_3_MPORT_data; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire [12:0] mem_3_MPORT_addr; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire mem_3_MPORT_mask; // @[src/main/scala/peripheral/Memory.scala 36:24] + wire mem_3_MPORT_en; // @[src/main/scala/peripheral/Memory.scala 36:24] + reg mem_3_io_read_data_MPORT_en_pipe_0; + reg [12:0] mem_3_io_read_data_MPORT_addr_pipe_0; + reg mem_3_io_debug_read_data_MPORT_en_pipe_0; + reg [12:0] mem_3_io_debug_read_data_MPORT_addr_pipe_0; + wire [31:0] _T = {{2'd0}, io_write_address[31:2]}; // @[src/main/scala/peripheral/Memory.scala 42:33] + wire [31:0] _io_read_data_T = {{2'd0}, io_read_address[31:2]}; // @[src/main/scala/peripheral/Memory.scala 44:45] + wire [15:0] io_read_data_lo = {mem_1_io_read_data_MPORT_data,mem_0_io_read_data_MPORT_data}; // @[src/main/scala/peripheral/Memory.scala 44:69] + wire [15:0] io_read_data_hi = {mem_3_io_read_data_MPORT_data,mem_2_io_read_data_MPORT_data}; // @[src/main/scala/peripheral/Memory.scala 44:69] + assign mem_0_io_read_data_MPORT_en = mem_0_io_read_data_MPORT_en_pipe_0; + assign mem_0_io_read_data_MPORT_addr = mem_0_io_read_data_MPORT_addr_pipe_0; + assign mem_0_io_read_data_MPORT_data = mem_0[mem_0_io_read_data_MPORT_addr]; // @[src/main/scala/peripheral/Memory.scala 36:24] + assign mem_0_io_debug_read_data_MPORT_en = mem_0_io_debug_read_data_MPORT_en_pipe_0; + assign mem_0_io_debug_read_data_MPORT_addr = mem_0_io_debug_read_data_MPORT_addr_pipe_0; + assign mem_0_io_debug_read_data_MPORT_data = mem_0[mem_0_io_debug_read_data_MPORT_addr]; // @[src/main/scala/peripheral/Memory.scala 36:24] + assign mem_0_MPORT_data = io_write_data[7:0]; + assign mem_0_MPORT_addr = _T[12:0]; + assign mem_0_MPORT_mask = io_write_strobe_0; + assign mem_0_MPORT_en = io_write_enable; + assign mem_1_io_read_data_MPORT_en = mem_1_io_read_data_MPORT_en_pipe_0; + assign mem_1_io_read_data_MPORT_addr = mem_1_io_read_data_MPORT_addr_pipe_0; + assign mem_1_io_read_data_MPORT_data = mem_1[mem_1_io_read_data_MPORT_addr]; // @[src/main/scala/peripheral/Memory.scala 36:24] + assign mem_1_io_debug_read_data_MPORT_en = mem_1_io_debug_read_data_MPORT_en_pipe_0; + assign mem_1_io_debug_read_data_MPORT_addr = mem_1_io_debug_read_data_MPORT_addr_pipe_0; + assign mem_1_io_debug_read_data_MPORT_data = mem_1[mem_1_io_debug_read_data_MPORT_addr]; // @[src/main/scala/peripheral/Memory.scala 36:24] + assign mem_1_MPORT_data = io_write_data[15:8]; + assign mem_1_MPORT_addr = _T[12:0]; + assign mem_1_MPORT_mask = io_write_strobe_1; + assign mem_1_MPORT_en = io_write_enable; + assign mem_2_io_read_data_MPORT_en = mem_2_io_read_data_MPORT_en_pipe_0; + assign mem_2_io_read_data_MPORT_addr = mem_2_io_read_data_MPORT_addr_pipe_0; + assign mem_2_io_read_data_MPORT_data = mem_2[mem_2_io_read_data_MPORT_addr]; // @[src/main/scala/peripheral/Memory.scala 36:24] + assign mem_2_io_debug_read_data_MPORT_en = mem_2_io_debug_read_data_MPORT_en_pipe_0; + assign mem_2_io_debug_read_data_MPORT_addr = mem_2_io_debug_read_data_MPORT_addr_pipe_0; + assign mem_2_io_debug_read_data_MPORT_data = mem_2[mem_2_io_debug_read_data_MPORT_addr]; // @[src/main/scala/peripheral/Memory.scala 36:24] + assign mem_2_MPORT_data = io_write_data[23:16]; + assign mem_2_MPORT_addr = _T[12:0]; + assign mem_2_MPORT_mask = io_write_strobe_2; + assign mem_2_MPORT_en = io_write_enable; + assign mem_3_io_read_data_MPORT_en = mem_3_io_read_data_MPORT_en_pipe_0; + assign mem_3_io_read_data_MPORT_addr = mem_3_io_read_data_MPORT_addr_pipe_0; + assign mem_3_io_read_data_MPORT_data = mem_3[mem_3_io_read_data_MPORT_addr]; // @[src/main/scala/peripheral/Memory.scala 36:24] + assign mem_3_io_debug_read_data_MPORT_en = mem_3_io_debug_read_data_MPORT_en_pipe_0; + assign mem_3_io_debug_read_data_MPORT_addr = mem_3_io_debug_read_data_MPORT_addr_pipe_0; + assign mem_3_io_debug_read_data_MPORT_data = mem_3[mem_3_io_debug_read_data_MPORT_addr]; // @[src/main/scala/peripheral/Memory.scala 36:24] + assign mem_3_MPORT_data = io_write_data[31:24]; + assign mem_3_MPORT_addr = _T[12:0]; + assign mem_3_MPORT_mask = io_write_strobe_3; + assign mem_3_MPORT_en = io_write_enable; + assign io_read_data = {io_read_data_hi,io_read_data_lo}; // @[src/main/scala/peripheral/Memory.scala 44:69] + always @(posedge clock) begin + if (mem_0_MPORT_en & mem_0_MPORT_mask) begin + mem_0[mem_0_MPORT_addr] <= mem_0_MPORT_data; // @[src/main/scala/peripheral/Memory.scala 36:24] + end + mem_0_io_read_data_MPORT_en_pipe_0 <= 1'h1; + if (1'h1) begin + mem_0_io_read_data_MPORT_addr_pipe_0 <= _io_read_data_T[12:0]; + end + mem_0_io_debug_read_data_MPORT_en_pipe_0 <= 1'h1; + if (1'h1) begin + mem_0_io_debug_read_data_MPORT_addr_pipe_0 <= 13'h0; + end + if (mem_1_MPORT_en & mem_1_MPORT_mask) begin + mem_1[mem_1_MPORT_addr] <= mem_1_MPORT_data; // @[src/main/scala/peripheral/Memory.scala 36:24] + end + mem_1_io_read_data_MPORT_en_pipe_0 <= 1'h1; + if (1'h1) begin + mem_1_io_read_data_MPORT_addr_pipe_0 <= _io_read_data_T[12:0]; + end + mem_1_io_debug_read_data_MPORT_en_pipe_0 <= 1'h1; + if (1'h1) begin + mem_1_io_debug_read_data_MPORT_addr_pipe_0 <= 13'h0; + end + if (mem_2_MPORT_en & mem_2_MPORT_mask) begin + mem_2[mem_2_MPORT_addr] <= mem_2_MPORT_data; // @[src/main/scala/peripheral/Memory.scala 36:24] + end + mem_2_io_read_data_MPORT_en_pipe_0 <= 1'h1; + if (1'h1) begin + mem_2_io_read_data_MPORT_addr_pipe_0 <= _io_read_data_T[12:0]; + end + mem_2_io_debug_read_data_MPORT_en_pipe_0 <= 1'h1; + if (1'h1) begin + mem_2_io_debug_read_data_MPORT_addr_pipe_0 <= 13'h0; + end + if (mem_3_MPORT_en & mem_3_MPORT_mask) begin + mem_3[mem_3_MPORT_addr] <= mem_3_MPORT_data; // @[src/main/scala/peripheral/Memory.scala 36:24] + end + mem_3_io_read_data_MPORT_en_pipe_0 <= 1'h1; + if (1'h1) begin + mem_3_io_read_data_MPORT_addr_pipe_0 <= _io_read_data_T[12:0]; + end + mem_3_io_debug_read_data_MPORT_en_pipe_0 <= 1'h1; + if (1'h1) begin + mem_3_io_debug_read_data_MPORT_addr_pipe_0 <= 13'h0; + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_MEM_INIT + _RAND_0 = {1{`RANDOM}}; + for (initvar = 0; initvar < 8192; initvar = initvar+1) + mem_0[initvar] = _RAND_0[7:0]; + _RAND_5 = {1{`RANDOM}}; + for (initvar = 0; initvar < 8192; initvar = initvar+1) + mem_1[initvar] = _RAND_5[7:0]; + _RAND_10 = {1{`RANDOM}}; + for (initvar = 0; initvar < 8192; initvar = initvar+1) + mem_2[initvar] = _RAND_10[7:0]; + _RAND_15 = {1{`RANDOM}}; + for (initvar = 0; initvar < 8192; initvar = initvar+1) + mem_3[initvar] = _RAND_15[7:0]; +`endif // RANDOMIZE_MEM_INIT +`ifdef RANDOMIZE_REG_INIT + _RAND_1 = {1{`RANDOM}}; + mem_0_io_read_data_MPORT_en_pipe_0 = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + mem_0_io_read_data_MPORT_addr_pipe_0 = _RAND_2[12:0]; + _RAND_3 = {1{`RANDOM}}; + mem_0_io_debug_read_data_MPORT_en_pipe_0 = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + mem_0_io_debug_read_data_MPORT_addr_pipe_0 = _RAND_4[12:0]; + _RAND_6 = {1{`RANDOM}}; + mem_1_io_read_data_MPORT_en_pipe_0 = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + mem_1_io_read_data_MPORT_addr_pipe_0 = _RAND_7[12:0]; + _RAND_8 = {1{`RANDOM}}; + mem_1_io_debug_read_data_MPORT_en_pipe_0 = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + mem_1_io_debug_read_data_MPORT_addr_pipe_0 = _RAND_9[12:0]; + _RAND_11 = {1{`RANDOM}}; + mem_2_io_read_data_MPORT_en_pipe_0 = _RAND_11[0:0]; + _RAND_12 = {1{`RANDOM}}; + mem_2_io_read_data_MPORT_addr_pipe_0 = _RAND_12[12:0]; + _RAND_13 = {1{`RANDOM}}; + mem_2_io_debug_read_data_MPORT_en_pipe_0 = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + mem_2_io_debug_read_data_MPORT_addr_pipe_0 = _RAND_14[12:0]; + _RAND_16 = {1{`RANDOM}}; + mem_3_io_read_data_MPORT_en_pipe_0 = _RAND_16[0:0]; + _RAND_17 = {1{`RANDOM}}; + mem_3_io_read_data_MPORT_addr_pipe_0 = _RAND_17[12:0]; + _RAND_18 = {1{`RANDOM}}; + mem_3_io_debug_read_data_MPORT_en_pipe_0 = _RAND_18[0:0]; + _RAND_19 = {1{`RANDOM}}; + mem_3_io_debug_read_data_MPORT_addr_pipe_0 = _RAND_19[12:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module AXI4LiteSlave_1( + input clock, + input reset, + input io_channels_write_address_channel_AWVALID, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + output io_channels_write_address_channel_AWREADY, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + input [31:0] io_channels_write_address_channel_AWADDR, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + input io_channels_write_data_channel_WVALID, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + output io_channels_write_data_channel_WREADY, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + input [31:0] io_channels_write_data_channel_WDATA, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + input [3:0] io_channels_write_data_channel_WSTRB, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + output io_channels_write_response_channel_BVALID, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + input io_channels_write_response_channel_BREADY, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + input io_channels_read_address_channel_ARVALID, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + output io_channels_read_address_channel_ARREADY, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + input [31:0] io_channels_read_address_channel_ARADDR, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + output io_channels_read_data_channel_RVALID, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + input io_channels_read_data_channel_RREADY, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + output [31:0] io_channels_read_data_channel_RDATA, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + output io_bundle_write, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + input [31:0] io_bundle_read_data, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + output [31:0] io_bundle_write_data, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + output io_bundle_write_strobe_0, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + output io_bundle_write_strobe_1, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + output io_bundle_write_strobe_2, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + output io_bundle_write_strobe_3, // @[src/main/scala/bus/AXI4Lite.scala 121:14] + output [31:0] io_bundle_address // @[src/main/scala/bus/AXI4Lite.scala 121:14] +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; +`endif // RANDOMIZE_REG_INIT + reg [2:0] state; // @[src/main/scala/bus/AXI4Lite.scala 125:22] + reg [31:0] addr; // @[src/main/scala/bus/AXI4Lite.scala 126:21] + reg write; // @[src/main/scala/bus/AXI4Lite.scala 130:22] + reg [31:0] write_data; // @[src/main/scala/bus/AXI4Lite.scala 132:27] + reg write_strobe_0; // @[src/main/scala/bus/AXI4Lite.scala 134:29] + reg write_strobe_1; // @[src/main/scala/bus/AXI4Lite.scala 134:29] + reg write_strobe_2; // @[src/main/scala/bus/AXI4Lite.scala 134:29] + reg write_strobe_3; // @[src/main/scala/bus/AXI4Lite.scala 134:29] + reg ARREADY; // @[src/main/scala/bus/AXI4Lite.scala 137:24] + reg RVALID; // @[src/main/scala/bus/AXI4Lite.scala 139:23] + reg AWREADY; // @[src/main/scala/bus/AXI4Lite.scala 146:24] + reg WREADY; // @[src/main/scala/bus/AXI4Lite.scala 148:23] + reg BVALID; // @[src/main/scala/bus/AXI4Lite.scala 151:23] + wire [2:0] _GEN_6 = io_channels_read_data_channel_RREADY & RVALID ? 3'h0 : state; // @[src/main/scala/bus/AXI4Lite.scala 179:60 180:15 125:22] + wire _GEN_7 = io_channels_read_data_channel_RREADY & RVALID ? 1'h0 : 1'h1; // @[src/main/scala/bus/AXI4Lite.scala 178:14 179:60 181:16] + wire [31:0] _GEN_8 = io_channels_write_address_channel_AWVALID & AWREADY ? io_channels_write_address_channel_AWADDR : + addr; // @[src/main/scala/bus/AXI4Lite.scala 186:66 187:14 126:21] + wire [2:0] _GEN_9 = io_channels_write_address_channel_AWVALID & AWREADY ? 3'h4 : state; // @[src/main/scala/bus/AXI4Lite.scala 186:66 188:15 125:22] + wire _GEN_10 = io_channels_write_address_channel_AWVALID & AWREADY ? 1'h0 : 1'h1; // @[src/main/scala/bus/AXI4Lite.scala 185:15 186:66 189:17] + wire [2:0] _GEN_11 = io_channels_write_data_channel_WVALID & WREADY ? 3'h5 : state; // @[src/main/scala/bus/AXI4Lite.scala 194:61 195:15 125:22] + wire _GEN_13 = io_channels_write_data_channel_WVALID & WREADY ? io_channels_write_data_channel_WSTRB[0] : + write_strobe_0; // @[src/main/scala/bus/AXI4Lite.scala 194:61 197:22 134:29] + wire _GEN_14 = io_channels_write_data_channel_WVALID & WREADY ? io_channels_write_data_channel_WSTRB[1] : + write_strobe_1; // @[src/main/scala/bus/AXI4Lite.scala 194:61 197:22 134:29] + wire _GEN_15 = io_channels_write_data_channel_WVALID & WREADY ? io_channels_write_data_channel_WSTRB[2] : + write_strobe_2; // @[src/main/scala/bus/AXI4Lite.scala 194:61 197:22 134:29] + wire _GEN_16 = io_channels_write_data_channel_WVALID & WREADY ? io_channels_write_data_channel_WSTRB[3] : + write_strobe_3; // @[src/main/scala/bus/AXI4Lite.scala 194:61 197:22 134:29] + wire _GEN_17 = io_channels_write_data_channel_WVALID & WREADY | write; // @[src/main/scala/bus/AXI4Lite.scala 194:61 198:15 130:22] + wire _GEN_18 = io_channels_write_data_channel_WVALID & WREADY ? 1'h0 : 1'h1; // @[src/main/scala/bus/AXI4Lite.scala 193:14 194:61 199:16] + wire [2:0] _GEN_19 = io_channels_write_response_channel_BREADY & BVALID ? 3'h0 : state; // @[src/main/scala/bus/AXI4Lite.scala 205:65 206:15 125:22] + wire _GEN_20 = io_channels_write_response_channel_BREADY & BVALID ? 1'h0 : write; // @[src/main/scala/bus/AXI4Lite.scala 205:65 207:15 130:22] + wire _GEN_21 = io_channels_write_response_channel_BREADY & BVALID ? 1'h0 : 1'h1; // @[src/main/scala/bus/AXI4Lite.scala 204:14 205:65 208:16] + wire _GEN_22 = 3'h5 == state ? 1'h0 : WREADY; // @[src/main/scala/bus/AXI4Lite.scala 156:17 203:14 148:23] + wire _GEN_23 = 3'h5 == state ? _GEN_21 : BVALID; // @[src/main/scala/bus/AXI4Lite.scala 156:17 151:23] + wire [2:0] _GEN_24 = 3'h5 == state ? _GEN_19 : state; // @[src/main/scala/bus/AXI4Lite.scala 156:17 125:22] + wire _GEN_25 = 3'h5 == state ? _GEN_20 : write; // @[src/main/scala/bus/AXI4Lite.scala 156:17 130:22] + wire _GEN_26 = 3'h4 == state ? _GEN_18 : _GEN_22; // @[src/main/scala/bus/AXI4Lite.scala 156:17] + wire [2:0] _GEN_27 = 3'h4 == state ? _GEN_11 : _GEN_24; // @[src/main/scala/bus/AXI4Lite.scala 156:17] + wire _GEN_29 = 3'h4 == state ? _GEN_13 : write_strobe_0; // @[src/main/scala/bus/AXI4Lite.scala 156:17 134:29] + wire _GEN_30 = 3'h4 == state ? _GEN_14 : write_strobe_1; // @[src/main/scala/bus/AXI4Lite.scala 156:17 134:29] + wire _GEN_31 = 3'h4 == state ? _GEN_15 : write_strobe_2; // @[src/main/scala/bus/AXI4Lite.scala 156:17 134:29] + wire _GEN_32 = 3'h4 == state ? _GEN_16 : write_strobe_3; // @[src/main/scala/bus/AXI4Lite.scala 156:17 134:29] + wire _GEN_33 = 3'h4 == state ? _GEN_17 : _GEN_25; // @[src/main/scala/bus/AXI4Lite.scala 156:17] + wire _GEN_34 = 3'h4 == state ? BVALID : _GEN_23; // @[src/main/scala/bus/AXI4Lite.scala 156:17 151:23] + wire _GEN_35 = 3'h3 == state ? _GEN_10 : AWREADY; // @[src/main/scala/bus/AXI4Lite.scala 156:17 146:24] + wire [31:0] _GEN_36 = 3'h3 == state ? _GEN_8 : addr; // @[src/main/scala/bus/AXI4Lite.scala 156:17 126:21] + wire [2:0] _GEN_37 = 3'h3 == state ? _GEN_9 : _GEN_27; // @[src/main/scala/bus/AXI4Lite.scala 156:17] + wire _GEN_38 = 3'h3 == state ? WREADY : _GEN_26; // @[src/main/scala/bus/AXI4Lite.scala 156:17 148:23] + wire _GEN_40 = 3'h3 == state ? write_strobe_0 : _GEN_29; // @[src/main/scala/bus/AXI4Lite.scala 156:17 134:29] + wire _GEN_41 = 3'h3 == state ? write_strobe_1 : _GEN_30; // @[src/main/scala/bus/AXI4Lite.scala 156:17 134:29] + wire _GEN_42 = 3'h3 == state ? write_strobe_2 : _GEN_31; // @[src/main/scala/bus/AXI4Lite.scala 156:17 134:29] + wire _GEN_43 = 3'h3 == state ? write_strobe_3 : _GEN_32; // @[src/main/scala/bus/AXI4Lite.scala 156:17 134:29] + wire _GEN_44 = 3'h3 == state ? write : _GEN_33; // @[src/main/scala/bus/AXI4Lite.scala 156:17 130:22] + wire _GEN_45 = 3'h3 == state ? BVALID : _GEN_34; // @[src/main/scala/bus/AXI4Lite.scala 156:17 151:23] + assign io_channels_write_address_channel_AWREADY = AWREADY; // @[src/main/scala/bus/AXI4Lite.scala 147:45] + assign io_channels_write_data_channel_WREADY = WREADY; // @[src/main/scala/bus/AXI4Lite.scala 149:41] + assign io_channels_write_response_channel_BVALID = BVALID; // @[src/main/scala/bus/AXI4Lite.scala 152:45] + assign io_channels_read_address_channel_ARREADY = ARREADY; // @[src/main/scala/bus/AXI4Lite.scala 138:44] + assign io_channels_read_data_channel_RVALID = RVALID; // @[src/main/scala/bus/AXI4Lite.scala 140:40] + assign io_channels_read_data_channel_RDATA = io_bundle_read_data; // @[src/main/scala/bus/AXI4Lite.scala 144:39] + assign io_bundle_write = write; // @[src/main/scala/bus/AXI4Lite.scala 131:19] + assign io_bundle_write_data = write_data; // @[src/main/scala/bus/AXI4Lite.scala 133:24] + assign io_bundle_write_strobe_0 = write_strobe_0; // @[src/main/scala/bus/AXI4Lite.scala 135:26] + assign io_bundle_write_strobe_1 = write_strobe_1; // @[src/main/scala/bus/AXI4Lite.scala 135:26] + assign io_bundle_write_strobe_2 = write_strobe_2; // @[src/main/scala/bus/AXI4Lite.scala 135:26] + assign io_bundle_write_strobe_3 = write_strobe_3; // @[src/main/scala/bus/AXI4Lite.scala 135:26] + assign io_bundle_address = addr; // @[src/main/scala/bus/AXI4Lite.scala 127:21] + always @(posedge clock) begin + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 125:22] + state <= 3'h0; // @[src/main/scala/bus/AXI4Lite.scala 125:22] + end else if (3'h0 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (io_channels_write_address_channel_AWVALID) begin // @[src/main/scala/bus/AXI4Lite.scala 162:55] + state <= 3'h3; // @[src/main/scala/bus/AXI4Lite.scala 163:15] + end else if (io_channels_read_address_channel_ARVALID) begin // @[src/main/scala/bus/AXI4Lite.scala 164:60] + state <= 3'h1; // @[src/main/scala/bus/AXI4Lite.scala 165:15] + end + end else if (3'h1 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (io_channels_read_address_channel_ARVALID & ARREADY) begin // @[src/main/scala/bus/AXI4Lite.scala 170:65] + state <= 3'h2; // @[src/main/scala/bus/AXI4Lite.scala 171:15] + end + end else if (3'h2 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + state <= _GEN_6; + end else begin + state <= _GEN_37; + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 126:21] + addr <= 32'h0; // @[src/main/scala/bus/AXI4Lite.scala 126:21] + end else if (!(3'h0 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (3'h1 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (io_channels_read_address_channel_ARVALID & ARREADY) begin // @[src/main/scala/bus/AXI4Lite.scala 170:65] + addr <= io_channels_read_address_channel_ARADDR; // @[src/main/scala/bus/AXI4Lite.scala 172:14] + end + end else if (!(3'h2 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + addr <= _GEN_36; + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 130:22] + write <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 130:22] + end else if (3'h0 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + write <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 159:13] + end else if (!(3'h1 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (!(3'h2 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + write <= _GEN_44; + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 132:27] + write_data <= 32'h0; // @[src/main/scala/bus/AXI4Lite.scala 132:27] + end else begin + write_data <= io_channels_write_data_channel_WDATA; + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 134:29] + write_strobe_0 <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 134:29] + end else if (!(3'h0 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (!(3'h1 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (!(3'h2 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + write_strobe_0 <= _GEN_40; + end + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 134:29] + write_strobe_1 <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 134:29] + end else if (!(3'h0 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (!(3'h1 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (!(3'h2 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + write_strobe_1 <= _GEN_41; + end + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 134:29] + write_strobe_2 <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 134:29] + end else if (!(3'h0 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (!(3'h1 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (!(3'h2 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + write_strobe_2 <= _GEN_42; + end + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 134:29] + write_strobe_3 <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 134:29] + end else if (!(3'h0 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (!(3'h1 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (!(3'h2 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + write_strobe_3 <= _GEN_43; + end + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 137:24] + ARREADY <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 137:24] + end else if (!(3'h0 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (3'h1 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (io_channels_read_address_channel_ARVALID & ARREADY) begin // @[src/main/scala/bus/AXI4Lite.scala 170:65] + ARREADY <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 174:17] + end else begin + ARREADY <= 1'h1; // @[src/main/scala/bus/AXI4Lite.scala 169:15] + end + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 139:23] + RVALID <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 139:23] + end else if (3'h0 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + RVALID <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 160:14] + end else if (!(3'h1 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (3'h2 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + RVALID <= _GEN_7; + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 146:24] + AWREADY <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 146:24] + end else if (!(3'h0 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (!(3'h1 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (!(3'h2 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + AWREADY <= _GEN_35; + end + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 148:23] + WREADY <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 148:23] + end else if (!(3'h0 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (!(3'h1 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (!(3'h2 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + WREADY <= _GEN_38; + end + end + end + if (reset) begin // @[src/main/scala/bus/AXI4Lite.scala 151:23] + BVALID <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 151:23] + end else if (3'h0 == state) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + BVALID <= 1'h0; // @[src/main/scala/bus/AXI4Lite.scala 161:14] + end else if (!(3'h1 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + if (!(3'h2 == state)) begin // @[src/main/scala/bus/AXI4Lite.scala 156:17] + BVALID <= _GEN_45; + end + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + state = _RAND_0[2:0]; + _RAND_1 = {1{`RANDOM}}; + addr = _RAND_1[31:0]; + _RAND_2 = {1{`RANDOM}}; + write = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + write_data = _RAND_3[31:0]; + _RAND_4 = {1{`RANDOM}}; + write_strobe_0 = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + write_strobe_1 = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + write_strobe_2 = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + write_strobe_3 = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + ARREADY = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + RVALID = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + AWREADY = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + WREADY = _RAND_11[0:0]; + _RAND_12 = {1{`RANDOM}}; + BVALID = _RAND_12[0:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module Memory( + input clock, + input reset, + input io_channels_write_address_channel_AWVALID, // @[src/main/scala/peripheral/Memory.scala 50:14] + output io_channels_write_address_channel_AWREADY, // @[src/main/scala/peripheral/Memory.scala 50:14] + input [31:0] io_channels_write_address_channel_AWADDR, // @[src/main/scala/peripheral/Memory.scala 50:14] + input io_channels_write_data_channel_WVALID, // @[src/main/scala/peripheral/Memory.scala 50:14] + output io_channels_write_data_channel_WREADY, // @[src/main/scala/peripheral/Memory.scala 50:14] + input [31:0] io_channels_write_data_channel_WDATA, // @[src/main/scala/peripheral/Memory.scala 50:14] + input [3:0] io_channels_write_data_channel_WSTRB, // @[src/main/scala/peripheral/Memory.scala 50:14] + output io_channels_write_response_channel_BVALID, // @[src/main/scala/peripheral/Memory.scala 50:14] + input io_channels_write_response_channel_BREADY, // @[src/main/scala/peripheral/Memory.scala 50:14] + input io_channels_read_address_channel_ARVALID, // @[src/main/scala/peripheral/Memory.scala 50:14] + output io_channels_read_address_channel_ARREADY, // @[src/main/scala/peripheral/Memory.scala 50:14] + input [31:0] io_channels_read_address_channel_ARADDR, // @[src/main/scala/peripheral/Memory.scala 50:14] + output io_channels_read_data_channel_RVALID, // @[src/main/scala/peripheral/Memory.scala 50:14] + input io_channels_read_data_channel_RREADY, // @[src/main/scala/peripheral/Memory.scala 50:14] + output [31:0] io_channels_read_data_channel_RDATA // @[src/main/scala/peripheral/Memory.scala 50:14] +); + wire mem_clock; // @[src/main/scala/peripheral/Memory.scala 57:19] + wire [31:0] mem_io_read_address; // @[src/main/scala/peripheral/Memory.scala 57:19] + wire [31:0] mem_io_write_address; // @[src/main/scala/peripheral/Memory.scala 57:19] + wire [31:0] mem_io_write_data; // @[src/main/scala/peripheral/Memory.scala 57:19] + wire mem_io_write_enable; // @[src/main/scala/peripheral/Memory.scala 57:19] + wire mem_io_write_strobe_0; // @[src/main/scala/peripheral/Memory.scala 57:19] + wire mem_io_write_strobe_1; // @[src/main/scala/peripheral/Memory.scala 57:19] + wire mem_io_write_strobe_2; // @[src/main/scala/peripheral/Memory.scala 57:19] + wire mem_io_write_strobe_3; // @[src/main/scala/peripheral/Memory.scala 57:19] + wire [31:0] mem_io_read_data; // @[src/main/scala/peripheral/Memory.scala 57:19] + wire slave_clock; // @[src/main/scala/peripheral/Memory.scala 58:21] + wire slave_reset; // @[src/main/scala/peripheral/Memory.scala 58:21] + wire slave_io_channels_write_address_channel_AWVALID; // @[src/main/scala/peripheral/Memory.scala 58:21] + wire slave_io_channels_write_address_channel_AWREADY; // @[src/main/scala/peripheral/Memory.scala 58:21] + wire [31:0] slave_io_channels_write_address_channel_AWADDR; // @[src/main/scala/peripheral/Memory.scala 58:21] + wire slave_io_channels_write_data_channel_WVALID; // @[src/main/scala/peripheral/Memory.scala 58:21] + wire slave_io_channels_write_data_channel_WREADY; // @[src/main/scala/peripheral/Memory.scala 58:21] + wire [31:0] slave_io_channels_write_data_channel_WDATA; // @[src/main/scala/peripheral/Memory.scala 58:21] + wire [3:0] slave_io_channels_write_data_channel_WSTRB; // @[src/main/scala/peripheral/Memory.scala 58:21] + wire slave_io_channels_write_response_channel_BVALID; // @[src/main/scala/peripheral/Memory.scala 58:21] + wire slave_io_channels_write_response_channel_BREADY; // @[src/main/scala/peripheral/Memory.scala 58:21] + wire slave_io_channels_read_address_channel_ARVALID; // @[src/main/scala/peripheral/Memory.scala 58:21] + wire slave_io_channels_read_address_channel_ARREADY; // @[src/main/scala/peripheral/Memory.scala 58:21] + wire [31:0] slave_io_channels_read_address_channel_ARADDR; // @[src/main/scala/peripheral/Memory.scala 58:21] + wire slave_io_channels_read_data_channel_RVALID; // @[src/main/scala/peripheral/Memory.scala 58:21] + wire slave_io_channels_read_data_channel_RREADY; // @[src/main/scala/peripheral/Memory.scala 58:21] + wire [31:0] slave_io_channels_read_data_channel_RDATA; // @[src/main/scala/peripheral/Memory.scala 58:21] + wire slave_io_bundle_write; // @[src/main/scala/peripheral/Memory.scala 58:21] + wire [31:0] slave_io_bundle_read_data; // @[src/main/scala/peripheral/Memory.scala 58:21] + wire [31:0] slave_io_bundle_write_data; // @[src/main/scala/peripheral/Memory.scala 58:21] + wire slave_io_bundle_write_strobe_0; // @[src/main/scala/peripheral/Memory.scala 58:21] + wire slave_io_bundle_write_strobe_1; // @[src/main/scala/peripheral/Memory.scala 58:21] + wire slave_io_bundle_write_strobe_2; // @[src/main/scala/peripheral/Memory.scala 58:21] + wire slave_io_bundle_write_strobe_3; // @[src/main/scala/peripheral/Memory.scala 58:21] + wire [31:0] slave_io_bundle_address; // @[src/main/scala/peripheral/Memory.scala 58:21] + BlockRAM mem ( // @[src/main/scala/peripheral/Memory.scala 57:19] + .clock(mem_clock), + .io_read_address(mem_io_read_address), + .io_write_address(mem_io_write_address), + .io_write_data(mem_io_write_data), + .io_write_enable(mem_io_write_enable), + .io_write_strobe_0(mem_io_write_strobe_0), + .io_write_strobe_1(mem_io_write_strobe_1), + .io_write_strobe_2(mem_io_write_strobe_2), + .io_write_strobe_3(mem_io_write_strobe_3), + .io_read_data(mem_io_read_data) + ); + AXI4LiteSlave_1 slave ( // @[src/main/scala/peripheral/Memory.scala 58:21] + .clock(slave_clock), + .reset(slave_reset), + .io_channels_write_address_channel_AWVALID(slave_io_channels_write_address_channel_AWVALID), + .io_channels_write_address_channel_AWREADY(slave_io_channels_write_address_channel_AWREADY), + .io_channels_write_address_channel_AWADDR(slave_io_channels_write_address_channel_AWADDR), + .io_channels_write_data_channel_WVALID(slave_io_channels_write_data_channel_WVALID), + .io_channels_write_data_channel_WREADY(slave_io_channels_write_data_channel_WREADY), + .io_channels_write_data_channel_WDATA(slave_io_channels_write_data_channel_WDATA), + .io_channels_write_data_channel_WSTRB(slave_io_channels_write_data_channel_WSTRB), + .io_channels_write_response_channel_BVALID(slave_io_channels_write_response_channel_BVALID), + .io_channels_write_response_channel_BREADY(slave_io_channels_write_response_channel_BREADY), + .io_channels_read_address_channel_ARVALID(slave_io_channels_read_address_channel_ARVALID), + .io_channels_read_address_channel_ARREADY(slave_io_channels_read_address_channel_ARREADY), + .io_channels_read_address_channel_ARADDR(slave_io_channels_read_address_channel_ARADDR), + .io_channels_read_data_channel_RVALID(slave_io_channels_read_data_channel_RVALID), + .io_channels_read_data_channel_RREADY(slave_io_channels_read_data_channel_RREADY), + .io_channels_read_data_channel_RDATA(slave_io_channels_read_data_channel_RDATA), + .io_bundle_write(slave_io_bundle_write), + .io_bundle_read_data(slave_io_bundle_read_data), + .io_bundle_write_data(slave_io_bundle_write_data), + .io_bundle_write_strobe_0(slave_io_bundle_write_strobe_0), + .io_bundle_write_strobe_1(slave_io_bundle_write_strobe_1), + .io_bundle_write_strobe_2(slave_io_bundle_write_strobe_2), + .io_bundle_write_strobe_3(slave_io_bundle_write_strobe_3), + .io_bundle_address(slave_io_bundle_address) + ); + assign io_channels_write_address_channel_AWREADY = slave_io_channels_write_address_channel_AWREADY; // @[src/main/scala/peripheral/Memory.scala 59:21] + assign io_channels_write_data_channel_WREADY = slave_io_channels_write_data_channel_WREADY; // @[src/main/scala/peripheral/Memory.scala 59:21] + assign io_channels_write_response_channel_BVALID = slave_io_channels_write_response_channel_BVALID; // @[src/main/scala/peripheral/Memory.scala 59:21] + assign io_channels_read_address_channel_ARREADY = slave_io_channels_read_address_channel_ARREADY; // @[src/main/scala/peripheral/Memory.scala 59:21] + assign io_channels_read_data_channel_RVALID = slave_io_channels_read_data_channel_RVALID; // @[src/main/scala/peripheral/Memory.scala 59:21] + assign io_channels_read_data_channel_RDATA = slave_io_channels_read_data_channel_RDATA; // @[src/main/scala/peripheral/Memory.scala 59:21] + assign mem_clock = clock; + assign mem_io_read_address = slave_io_bundle_address; // @[src/main/scala/peripheral/Memory.scala 67:23] + assign mem_io_write_address = slave_io_bundle_address; // @[src/main/scala/peripheral/Memory.scala 64:24] + assign mem_io_write_data = slave_io_bundle_write_data; // @[src/main/scala/peripheral/Memory.scala 63:21] + assign mem_io_write_enable = slave_io_bundle_write; // @[src/main/scala/peripheral/Memory.scala 62:23] + assign mem_io_write_strobe_0 = slave_io_bundle_write_strobe_0; // @[src/main/scala/peripheral/Memory.scala 65:23] + assign mem_io_write_strobe_1 = slave_io_bundle_write_strobe_1; // @[src/main/scala/peripheral/Memory.scala 65:23] + assign mem_io_write_strobe_2 = slave_io_bundle_write_strobe_2; // @[src/main/scala/peripheral/Memory.scala 65:23] + assign mem_io_write_strobe_3 = slave_io_bundle_write_strobe_3; // @[src/main/scala/peripheral/Memory.scala 65:23] + assign slave_clock = clock; + assign slave_reset = reset; + assign slave_io_channels_write_address_channel_AWVALID = io_channels_write_address_channel_AWVALID; // @[src/main/scala/peripheral/Memory.scala 59:21] + assign slave_io_channels_write_address_channel_AWADDR = io_channels_write_address_channel_AWADDR; // @[src/main/scala/peripheral/Memory.scala 59:21] + assign slave_io_channels_write_data_channel_WVALID = io_channels_write_data_channel_WVALID; // @[src/main/scala/peripheral/Memory.scala 59:21] + assign slave_io_channels_write_data_channel_WDATA = io_channels_write_data_channel_WDATA; // @[src/main/scala/peripheral/Memory.scala 59:21] + assign slave_io_channels_write_data_channel_WSTRB = io_channels_write_data_channel_WSTRB; // @[src/main/scala/peripheral/Memory.scala 59:21] + assign slave_io_channels_write_response_channel_BREADY = io_channels_write_response_channel_BREADY; // @[src/main/scala/peripheral/Memory.scala 59:21] + assign slave_io_channels_read_address_channel_ARVALID = io_channels_read_address_channel_ARVALID; // @[src/main/scala/peripheral/Memory.scala 59:21] + assign slave_io_channels_read_address_channel_ARADDR = io_channels_read_address_channel_ARADDR; // @[src/main/scala/peripheral/Memory.scala 59:21] + assign slave_io_channels_read_data_channel_RREADY = io_channels_read_data_channel_RREADY; // @[src/main/scala/peripheral/Memory.scala 59:21] + assign slave_io_bundle_read_data = mem_io_read_data; // @[src/main/scala/peripheral/Memory.scala 68:29] +endmodule +module Timer( + input clock, + input reset, + input io_channels_write_address_channel_AWVALID, // @[src/main/scala/peripheral/Timer.scala 23:14] + output io_channels_write_address_channel_AWREADY, // @[src/main/scala/peripheral/Timer.scala 23:14] + input [7:0] io_channels_write_address_channel_AWADDR, // @[src/main/scala/peripheral/Timer.scala 23:14] + input io_channels_write_data_channel_WVALID, // @[src/main/scala/peripheral/Timer.scala 23:14] + output io_channels_write_data_channel_WREADY, // @[src/main/scala/peripheral/Timer.scala 23:14] + input [31:0] io_channels_write_data_channel_WDATA, // @[src/main/scala/peripheral/Timer.scala 23:14] + output io_channels_write_response_channel_BVALID, // @[src/main/scala/peripheral/Timer.scala 23:14] + input io_channels_write_response_channel_BREADY, // @[src/main/scala/peripheral/Timer.scala 23:14] + input io_channels_read_address_channel_ARVALID, // @[src/main/scala/peripheral/Timer.scala 23:14] + output io_channels_read_address_channel_ARREADY, // @[src/main/scala/peripheral/Timer.scala 23:14] + input [7:0] io_channels_read_address_channel_ARADDR, // @[src/main/scala/peripheral/Timer.scala 23:14] + output io_channels_read_data_channel_RVALID, // @[src/main/scala/peripheral/Timer.scala 23:14] + input io_channels_read_data_channel_RREADY, // @[src/main/scala/peripheral/Timer.scala 23:14] + output [31:0] io_channels_read_data_channel_RDATA, // @[src/main/scala/peripheral/Timer.scala 23:14] + output io_signal_interrupt // @[src/main/scala/peripheral/Timer.scala 23:14] +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; +`endif // RANDOMIZE_REG_INIT + wire slave_clock; // @[src/main/scala/peripheral/Timer.scala 30:21] + wire slave_reset; // @[src/main/scala/peripheral/Timer.scala 30:21] + wire slave_io_channels_write_address_channel_AWVALID; // @[src/main/scala/peripheral/Timer.scala 30:21] + wire slave_io_channels_write_address_channel_AWREADY; // @[src/main/scala/peripheral/Timer.scala 30:21] + wire [7:0] slave_io_channels_write_address_channel_AWADDR; // @[src/main/scala/peripheral/Timer.scala 30:21] + wire slave_io_channels_write_data_channel_WVALID; // @[src/main/scala/peripheral/Timer.scala 30:21] + wire slave_io_channels_write_data_channel_WREADY; // @[src/main/scala/peripheral/Timer.scala 30:21] + wire [31:0] slave_io_channels_write_data_channel_WDATA; // @[src/main/scala/peripheral/Timer.scala 30:21] + wire slave_io_channels_write_response_channel_BVALID; // @[src/main/scala/peripheral/Timer.scala 30:21] + wire slave_io_channels_write_response_channel_BREADY; // @[src/main/scala/peripheral/Timer.scala 30:21] + wire slave_io_channels_read_address_channel_ARVALID; // @[src/main/scala/peripheral/Timer.scala 30:21] + wire slave_io_channels_read_address_channel_ARREADY; // @[src/main/scala/peripheral/Timer.scala 30:21] + wire [7:0] slave_io_channels_read_address_channel_ARADDR; // @[src/main/scala/peripheral/Timer.scala 30:21] + wire slave_io_channels_read_data_channel_RVALID; // @[src/main/scala/peripheral/Timer.scala 30:21] + wire slave_io_channels_read_data_channel_RREADY; // @[src/main/scala/peripheral/Timer.scala 30:21] + wire [31:0] slave_io_channels_read_data_channel_RDATA; // @[src/main/scala/peripheral/Timer.scala 30:21] + wire slave_io_bundle_read; // @[src/main/scala/peripheral/Timer.scala 30:21] + wire slave_io_bundle_write; // @[src/main/scala/peripheral/Timer.scala 30:21] + wire [31:0] slave_io_bundle_read_data; // @[src/main/scala/peripheral/Timer.scala 30:21] + wire [31:0] slave_io_bundle_write_data; // @[src/main/scala/peripheral/Timer.scala 30:21] + wire [7:0] slave_io_bundle_address; // @[src/main/scala/peripheral/Timer.scala 30:21] + reg [31:0] count; // @[src/main/scala/peripheral/Timer.scala 33:22] + reg [31:0] limit; // @[src/main/scala/peripheral/Timer.scala 34:22] + reg enabled; // @[src/main/scala/peripheral/Timer.scala 36:24] + wire [31:0] _slave_io_bundle_read_data_T_1 = 8'h4 == slave_io_bundle_address ? limit : 32'h0; // @[src/main/scala/peripheral/Timer.scala 42:73] + wire [31:0] _slave_io_bundle_read_data_T_3 = 8'h8 == slave_io_bundle_address ? {{31'd0}, enabled} : + _slave_io_bundle_read_data_T_1; // @[src/main/scala/peripheral/Timer.scala 42:73] + wire _GEN_1 = slave_io_bundle_address == 8'h8 ? slave_io_bundle_write_data != 32'h0 : enabled; // @[src/main/scala/peripheral/Timer.scala 53:51 54:15 36:24] + wire _GEN_4 = slave_io_bundle_address == 8'h4 ? enabled : _GEN_1; // @[src/main/scala/peripheral/Timer.scala 36:24 50:45] + wire _GEN_7 = slave_io_bundle_write ? _GEN_4 : enabled; // @[src/main/scala/peripheral/Timer.scala 36:24 49:31] + wire [31:0] _io_signal_interrupt_T_1 = limit - 32'ha; // @[src/main/scala/peripheral/Timer.scala 58:54] + wire [31:0] _count_T_1 = count + 32'h1; // @[src/main/scala/peripheral/Timer.scala 63:20] + AXI4LiteSlave slave ( // @[src/main/scala/peripheral/Timer.scala 30:21] + .clock(slave_clock), + .reset(slave_reset), + .io_channels_write_address_channel_AWVALID(slave_io_channels_write_address_channel_AWVALID), + .io_channels_write_address_channel_AWREADY(slave_io_channels_write_address_channel_AWREADY), + .io_channels_write_address_channel_AWADDR(slave_io_channels_write_address_channel_AWADDR), + .io_channels_write_data_channel_WVALID(slave_io_channels_write_data_channel_WVALID), + .io_channels_write_data_channel_WREADY(slave_io_channels_write_data_channel_WREADY), + .io_channels_write_data_channel_WDATA(slave_io_channels_write_data_channel_WDATA), + .io_channels_write_response_channel_BVALID(slave_io_channels_write_response_channel_BVALID), + .io_channels_write_response_channel_BREADY(slave_io_channels_write_response_channel_BREADY), + .io_channels_read_address_channel_ARVALID(slave_io_channels_read_address_channel_ARVALID), + .io_channels_read_address_channel_ARREADY(slave_io_channels_read_address_channel_ARREADY), + .io_channels_read_address_channel_ARADDR(slave_io_channels_read_address_channel_ARADDR), + .io_channels_read_data_channel_RVALID(slave_io_channels_read_data_channel_RVALID), + .io_channels_read_data_channel_RREADY(slave_io_channels_read_data_channel_RREADY), + .io_channels_read_data_channel_RDATA(slave_io_channels_read_data_channel_RDATA), + .io_bundle_read(slave_io_bundle_read), + .io_bundle_write(slave_io_bundle_write), + .io_bundle_read_data(slave_io_bundle_read_data), + .io_bundle_write_data(slave_io_bundle_write_data), + .io_bundle_address(slave_io_bundle_address) + ); + assign io_channels_write_address_channel_AWREADY = slave_io_channels_write_address_channel_AWREADY; // @[src/main/scala/peripheral/Timer.scala 31:21] + assign io_channels_write_data_channel_WREADY = slave_io_channels_write_data_channel_WREADY; // @[src/main/scala/peripheral/Timer.scala 31:21] + assign io_channels_write_response_channel_BVALID = slave_io_channels_write_response_channel_BVALID; // @[src/main/scala/peripheral/Timer.scala 31:21] + assign io_channels_read_address_channel_ARREADY = slave_io_channels_read_address_channel_ARREADY; // @[src/main/scala/peripheral/Timer.scala 31:21] + assign io_channels_read_data_channel_RVALID = slave_io_channels_read_data_channel_RVALID; // @[src/main/scala/peripheral/Timer.scala 31:21] + assign io_channels_read_data_channel_RDATA = slave_io_channels_read_data_channel_RDATA; // @[src/main/scala/peripheral/Timer.scala 31:21] + assign io_signal_interrupt = enabled & count >= _io_signal_interrupt_T_1; // @[src/main/scala/peripheral/Timer.scala 58:34] + assign slave_clock = clock; + assign slave_reset = reset; + assign slave_io_channels_write_address_channel_AWVALID = io_channels_write_address_channel_AWVALID; // @[src/main/scala/peripheral/Timer.scala 31:21] + assign slave_io_channels_write_address_channel_AWADDR = io_channels_write_address_channel_AWADDR; // @[src/main/scala/peripheral/Timer.scala 31:21] + assign slave_io_channels_write_data_channel_WVALID = io_channels_write_data_channel_WVALID; // @[src/main/scala/peripheral/Timer.scala 31:21] + assign slave_io_channels_write_data_channel_WDATA = io_channels_write_data_channel_WDATA; // @[src/main/scala/peripheral/Timer.scala 31:21] + assign slave_io_channels_write_response_channel_BREADY = io_channels_write_response_channel_BREADY; // @[src/main/scala/peripheral/Timer.scala 31:21] + assign slave_io_channels_read_address_channel_ARVALID = io_channels_read_address_channel_ARVALID; // @[src/main/scala/peripheral/Timer.scala 31:21] + assign slave_io_channels_read_address_channel_ARADDR = io_channels_read_address_channel_ARADDR; // @[src/main/scala/peripheral/Timer.scala 31:21] + assign slave_io_channels_read_data_channel_RREADY = io_channels_read_data_channel_RREADY; // @[src/main/scala/peripheral/Timer.scala 31:21] + assign slave_io_bundle_read_data = slave_io_bundle_read ? _slave_io_bundle_read_data_T_3 : 32'h0; // @[src/main/scala/peripheral/Timer.scala 39:29 41:30 42:31] + always @(posedge clock) begin + if (reset) begin // @[src/main/scala/peripheral/Timer.scala 33:22] + count <= 32'h0; // @[src/main/scala/peripheral/Timer.scala 33:22] + end else if (count >= limit) begin // @[src/main/scala/peripheral/Timer.scala 60:24] + count <= 32'h0; // @[src/main/scala/peripheral/Timer.scala 61:11] + end else begin + count <= _count_T_1; // @[src/main/scala/peripheral/Timer.scala 63:11] + end + if (reset) begin // @[src/main/scala/peripheral/Timer.scala 34:22] + limit <= 32'h5f5e100; // @[src/main/scala/peripheral/Timer.scala 34:22] + end else if (slave_io_bundle_write) begin // @[src/main/scala/peripheral/Timer.scala 49:31] + if (slave_io_bundle_address == 8'h4) begin // @[src/main/scala/peripheral/Timer.scala 50:45] + limit <= slave_io_bundle_write_data; // @[src/main/scala/peripheral/Timer.scala 51:13] + end + end + enabled <= reset | _GEN_7; // @[src/main/scala/peripheral/Timer.scala 36:{24,24}] + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + count = _RAND_0[31:0]; + _RAND_1 = {1{`RANDOM}}; + limit = _RAND_1[31:0]; + _RAND_2 = {1{`RANDOM}}; + enabled = _RAND_2[0:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module DummySlave( + input clock, + input reset, + input io_channels_write_address_channel_AWVALID, // @[src/main/scala/peripheral/DummySlave.scala 24:14] + output io_channels_write_address_channel_AWREADY, // @[src/main/scala/peripheral/DummySlave.scala 24:14] + input [3:0] io_channels_write_address_channel_AWADDR, // @[src/main/scala/peripheral/DummySlave.scala 24:14] + input io_channels_write_data_channel_WVALID, // @[src/main/scala/peripheral/DummySlave.scala 24:14] + output io_channels_write_data_channel_WREADY, // @[src/main/scala/peripheral/DummySlave.scala 24:14] + input [31:0] io_channels_write_data_channel_WDATA, // @[src/main/scala/peripheral/DummySlave.scala 24:14] + input [3:0] io_channels_write_data_channel_WSTRB, // @[src/main/scala/peripheral/DummySlave.scala 24:14] + output io_channels_write_response_channel_BVALID, // @[src/main/scala/peripheral/DummySlave.scala 24:14] + input io_channels_write_response_channel_BREADY, // @[src/main/scala/peripheral/DummySlave.scala 24:14] + input io_channels_read_address_channel_ARVALID, // @[src/main/scala/peripheral/DummySlave.scala 24:14] + output io_channels_read_address_channel_ARREADY, // @[src/main/scala/peripheral/DummySlave.scala 24:14] + input [3:0] io_channels_read_address_channel_ARADDR, // @[src/main/scala/peripheral/DummySlave.scala 24:14] + output io_channels_read_data_channel_RVALID, // @[src/main/scala/peripheral/DummySlave.scala 24:14] + input io_channels_read_data_channel_RREADY, // @[src/main/scala/peripheral/DummySlave.scala 24:14] + output [31:0] io_channels_read_data_channel_RDATA // @[src/main/scala/peripheral/DummySlave.scala 24:14] +); + wire slave_clock; // @[src/main/scala/peripheral/DummySlave.scala 28:21] + wire slave_reset; // @[src/main/scala/peripheral/DummySlave.scala 28:21] + wire slave_io_channels_write_address_channel_AWVALID; // @[src/main/scala/peripheral/DummySlave.scala 28:21] + wire slave_io_channels_write_address_channel_AWREADY; // @[src/main/scala/peripheral/DummySlave.scala 28:21] + wire [31:0] slave_io_channels_write_address_channel_AWADDR; // @[src/main/scala/peripheral/DummySlave.scala 28:21] + wire slave_io_channels_write_data_channel_WVALID; // @[src/main/scala/peripheral/DummySlave.scala 28:21] + wire slave_io_channels_write_data_channel_WREADY; // @[src/main/scala/peripheral/DummySlave.scala 28:21] + wire [31:0] slave_io_channels_write_data_channel_WDATA; // @[src/main/scala/peripheral/DummySlave.scala 28:21] + wire [3:0] slave_io_channels_write_data_channel_WSTRB; // @[src/main/scala/peripheral/DummySlave.scala 28:21] + wire slave_io_channels_write_response_channel_BVALID; // @[src/main/scala/peripheral/DummySlave.scala 28:21] + wire slave_io_channels_write_response_channel_BREADY; // @[src/main/scala/peripheral/DummySlave.scala 28:21] + wire slave_io_channels_read_address_channel_ARVALID; // @[src/main/scala/peripheral/DummySlave.scala 28:21] + wire slave_io_channels_read_address_channel_ARREADY; // @[src/main/scala/peripheral/DummySlave.scala 28:21] + wire [31:0] slave_io_channels_read_address_channel_ARADDR; // @[src/main/scala/peripheral/DummySlave.scala 28:21] + wire slave_io_channels_read_data_channel_RVALID; // @[src/main/scala/peripheral/DummySlave.scala 28:21] + wire slave_io_channels_read_data_channel_RREADY; // @[src/main/scala/peripheral/DummySlave.scala 28:21] + wire [31:0] slave_io_channels_read_data_channel_RDATA; // @[src/main/scala/peripheral/DummySlave.scala 28:21] + wire slave_io_bundle_write; // @[src/main/scala/peripheral/DummySlave.scala 28:21] + wire [31:0] slave_io_bundle_read_data; // @[src/main/scala/peripheral/DummySlave.scala 28:21] + wire [31:0] slave_io_bundle_write_data; // @[src/main/scala/peripheral/DummySlave.scala 28:21] + wire slave_io_bundle_write_strobe_0; // @[src/main/scala/peripheral/DummySlave.scala 28:21] + wire slave_io_bundle_write_strobe_1; // @[src/main/scala/peripheral/DummySlave.scala 28:21] + wire slave_io_bundle_write_strobe_2; // @[src/main/scala/peripheral/DummySlave.scala 28:21] + wire slave_io_bundle_write_strobe_3; // @[src/main/scala/peripheral/DummySlave.scala 28:21] + wire [31:0] slave_io_bundle_address; // @[src/main/scala/peripheral/DummySlave.scala 28:21] + AXI4LiteSlave_1 slave ( // @[src/main/scala/peripheral/DummySlave.scala 28:21] + .clock(slave_clock), + .reset(slave_reset), + .io_channels_write_address_channel_AWVALID(slave_io_channels_write_address_channel_AWVALID), + .io_channels_write_address_channel_AWREADY(slave_io_channels_write_address_channel_AWREADY), + .io_channels_write_address_channel_AWADDR(slave_io_channels_write_address_channel_AWADDR), + .io_channels_write_data_channel_WVALID(slave_io_channels_write_data_channel_WVALID), + .io_channels_write_data_channel_WREADY(slave_io_channels_write_data_channel_WREADY), + .io_channels_write_data_channel_WDATA(slave_io_channels_write_data_channel_WDATA), + .io_channels_write_data_channel_WSTRB(slave_io_channels_write_data_channel_WSTRB), + .io_channels_write_response_channel_BVALID(slave_io_channels_write_response_channel_BVALID), + .io_channels_write_response_channel_BREADY(slave_io_channels_write_response_channel_BREADY), + .io_channels_read_address_channel_ARVALID(slave_io_channels_read_address_channel_ARVALID), + .io_channels_read_address_channel_ARREADY(slave_io_channels_read_address_channel_ARREADY), + .io_channels_read_address_channel_ARADDR(slave_io_channels_read_address_channel_ARADDR), + .io_channels_read_data_channel_RVALID(slave_io_channels_read_data_channel_RVALID), + .io_channels_read_data_channel_RREADY(slave_io_channels_read_data_channel_RREADY), + .io_channels_read_data_channel_RDATA(slave_io_channels_read_data_channel_RDATA), + .io_bundle_write(slave_io_bundle_write), + .io_bundle_read_data(slave_io_bundle_read_data), + .io_bundle_write_data(slave_io_bundle_write_data), + .io_bundle_write_strobe_0(slave_io_bundle_write_strobe_0), + .io_bundle_write_strobe_1(slave_io_bundle_write_strobe_1), + .io_bundle_write_strobe_2(slave_io_bundle_write_strobe_2), + .io_bundle_write_strobe_3(slave_io_bundle_write_strobe_3), + .io_bundle_address(slave_io_bundle_address) + ); + assign io_channels_write_address_channel_AWREADY = slave_io_channels_write_address_channel_AWREADY; // @[src/main/scala/peripheral/DummySlave.scala 29:21] + assign io_channels_write_data_channel_WREADY = slave_io_channels_write_data_channel_WREADY; // @[src/main/scala/peripheral/DummySlave.scala 29:21] + assign io_channels_write_response_channel_BVALID = slave_io_channels_write_response_channel_BVALID; // @[src/main/scala/peripheral/DummySlave.scala 29:21] + assign io_channels_read_address_channel_ARREADY = slave_io_channels_read_address_channel_ARREADY; // @[src/main/scala/peripheral/DummySlave.scala 29:21] + assign io_channels_read_data_channel_RVALID = slave_io_channels_read_data_channel_RVALID; // @[src/main/scala/peripheral/DummySlave.scala 29:21] + assign io_channels_read_data_channel_RDATA = slave_io_channels_read_data_channel_RDATA; // @[src/main/scala/peripheral/DummySlave.scala 29:21] + assign slave_clock = clock; + assign slave_reset = reset; + assign slave_io_channels_write_address_channel_AWVALID = io_channels_write_address_channel_AWVALID; // @[src/main/scala/peripheral/DummySlave.scala 29:21] + assign slave_io_channels_write_address_channel_AWADDR = {{28'd0}, io_channels_write_address_channel_AWADDR}; // @[src/main/scala/peripheral/DummySlave.scala 29:21] + assign slave_io_channels_write_data_channel_WVALID = io_channels_write_data_channel_WVALID; // @[src/main/scala/peripheral/DummySlave.scala 29:21] + assign slave_io_channels_write_data_channel_WDATA = io_channels_write_data_channel_WDATA; // @[src/main/scala/peripheral/DummySlave.scala 29:21] + assign slave_io_channels_write_data_channel_WSTRB = io_channels_write_data_channel_WSTRB; // @[src/main/scala/peripheral/DummySlave.scala 29:21] + assign slave_io_channels_write_response_channel_BREADY = io_channels_write_response_channel_BREADY; // @[src/main/scala/peripheral/DummySlave.scala 29:21] + assign slave_io_channels_read_address_channel_ARVALID = io_channels_read_address_channel_ARVALID; // @[src/main/scala/peripheral/DummySlave.scala 29:21] + assign slave_io_channels_read_address_channel_ARADDR = {{28'd0}, io_channels_read_address_channel_ARADDR}; // @[src/main/scala/peripheral/DummySlave.scala 29:21] + assign slave_io_channels_read_data_channel_RREADY = io_channels_read_data_channel_RREADY; // @[src/main/scala/peripheral/DummySlave.scala 29:21] + assign slave_io_bundle_read_data = 32'hdeadbeef; // @[src/main/scala/peripheral/DummySlave.scala 31:29] +endmodule +module DummyMaster( + input clock, + input reset, + output io_channels_write_address_channel_AWVALID, // @[src/main/scala/peripheral/DummyMaster.scala 23:14] + input io_channels_write_address_channel_AWREADY, // @[src/main/scala/peripheral/DummyMaster.scala 23:14] + output [31:0] io_channels_write_address_channel_AWADDR, // @[src/main/scala/peripheral/DummyMaster.scala 23:14] + output io_channels_write_data_channel_WVALID, // @[src/main/scala/peripheral/DummyMaster.scala 23:14] + input io_channels_write_data_channel_WREADY, // @[src/main/scala/peripheral/DummyMaster.scala 23:14] + output [31:0] io_channels_write_data_channel_WDATA, // @[src/main/scala/peripheral/DummyMaster.scala 23:14] + output [3:0] io_channels_write_data_channel_WSTRB, // @[src/main/scala/peripheral/DummyMaster.scala 23:14] + input io_channels_write_response_channel_BVALID, // @[src/main/scala/peripheral/DummyMaster.scala 23:14] + output io_channels_write_response_channel_BREADY, // @[src/main/scala/peripheral/DummyMaster.scala 23:14] + output io_channels_read_address_channel_ARVALID, // @[src/main/scala/peripheral/DummyMaster.scala 23:14] + input io_channels_read_address_channel_ARREADY, // @[src/main/scala/peripheral/DummyMaster.scala 23:14] + output [31:0] io_channels_read_address_channel_ARADDR, // @[src/main/scala/peripheral/DummyMaster.scala 23:14] + input io_channels_read_data_channel_RVALID, // @[src/main/scala/peripheral/DummyMaster.scala 23:14] + output io_channels_read_data_channel_RREADY, // @[src/main/scala/peripheral/DummyMaster.scala 23:14] + input [31:0] io_channels_read_data_channel_RDATA // @[src/main/scala/peripheral/DummyMaster.scala 23:14] +); + wire master_clock; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire master_reset; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire master_io_channels_write_address_channel_AWVALID; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire master_io_channels_write_address_channel_AWREADY; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire [31:0] master_io_channels_write_address_channel_AWADDR; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire master_io_channels_write_data_channel_WVALID; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire master_io_channels_write_data_channel_WREADY; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire [31:0] master_io_channels_write_data_channel_WDATA; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire [3:0] master_io_channels_write_data_channel_WSTRB; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire master_io_channels_write_response_channel_BVALID; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire master_io_channels_write_response_channel_BREADY; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire master_io_channels_read_address_channel_ARVALID; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire master_io_channels_read_address_channel_ARREADY; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire [31:0] master_io_channels_read_address_channel_ARADDR; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire master_io_channels_read_data_channel_RVALID; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire master_io_channels_read_data_channel_RREADY; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire [31:0] master_io_channels_read_data_channel_RDATA; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire [1:0] master_io_channels_read_data_channel_RRESP; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire master_io_bundle_read; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire master_io_bundle_write; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire [31:0] master_io_bundle_read_data; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire [31:0] master_io_bundle_write_data; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire master_io_bundle_write_strobe_0; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire master_io_bundle_write_strobe_1; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire master_io_bundle_write_strobe_2; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire master_io_bundle_write_strobe_3; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire [31:0] master_io_bundle_address; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire master_io_bundle_busy; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire master_io_bundle_read_valid; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + wire master_io_bundle_write_valid; // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + AXI4LiteMaster master ( // @[src/main/scala/peripheral/DummyMaster.scala 26:22] + .clock(master_clock), + .reset(master_reset), + .io_channels_write_address_channel_AWVALID(master_io_channels_write_address_channel_AWVALID), + .io_channels_write_address_channel_AWREADY(master_io_channels_write_address_channel_AWREADY), + .io_channels_write_address_channel_AWADDR(master_io_channels_write_address_channel_AWADDR), + .io_channels_write_data_channel_WVALID(master_io_channels_write_data_channel_WVALID), + .io_channels_write_data_channel_WREADY(master_io_channels_write_data_channel_WREADY), + .io_channels_write_data_channel_WDATA(master_io_channels_write_data_channel_WDATA), + .io_channels_write_data_channel_WSTRB(master_io_channels_write_data_channel_WSTRB), + .io_channels_write_response_channel_BVALID(master_io_channels_write_response_channel_BVALID), + .io_channels_write_response_channel_BREADY(master_io_channels_write_response_channel_BREADY), + .io_channels_read_address_channel_ARVALID(master_io_channels_read_address_channel_ARVALID), + .io_channels_read_address_channel_ARREADY(master_io_channels_read_address_channel_ARREADY), + .io_channels_read_address_channel_ARADDR(master_io_channels_read_address_channel_ARADDR), + .io_channels_read_data_channel_RVALID(master_io_channels_read_data_channel_RVALID), + .io_channels_read_data_channel_RREADY(master_io_channels_read_data_channel_RREADY), + .io_channels_read_data_channel_RDATA(master_io_channels_read_data_channel_RDATA), + .io_channels_read_data_channel_RRESP(master_io_channels_read_data_channel_RRESP), + .io_bundle_read(master_io_bundle_read), + .io_bundle_write(master_io_bundle_write), + .io_bundle_read_data(master_io_bundle_read_data), + .io_bundle_write_data(master_io_bundle_write_data), + .io_bundle_write_strobe_0(master_io_bundle_write_strobe_0), + .io_bundle_write_strobe_1(master_io_bundle_write_strobe_1), + .io_bundle_write_strobe_2(master_io_bundle_write_strobe_2), + .io_bundle_write_strobe_3(master_io_bundle_write_strobe_3), + .io_bundle_address(master_io_bundle_address), + .io_bundle_busy(master_io_bundle_busy), + .io_bundle_read_valid(master_io_bundle_read_valid), + .io_bundle_write_valid(master_io_bundle_write_valid) + ); + assign io_channels_write_address_channel_AWVALID = master_io_channels_write_address_channel_AWVALID; // @[src/main/scala/peripheral/DummyMaster.scala 27:22] + assign io_channels_write_address_channel_AWADDR = master_io_channels_write_address_channel_AWADDR; // @[src/main/scala/peripheral/DummyMaster.scala 27:22] + assign io_channels_write_data_channel_WVALID = master_io_channels_write_data_channel_WVALID; // @[src/main/scala/peripheral/DummyMaster.scala 27:22] + assign io_channels_write_data_channel_WDATA = master_io_channels_write_data_channel_WDATA; // @[src/main/scala/peripheral/DummyMaster.scala 27:22] + assign io_channels_write_data_channel_WSTRB = master_io_channels_write_data_channel_WSTRB; // @[src/main/scala/peripheral/DummyMaster.scala 27:22] + assign io_channels_write_response_channel_BREADY = master_io_channels_write_response_channel_BREADY; // @[src/main/scala/peripheral/DummyMaster.scala 27:22] + assign io_channels_read_address_channel_ARVALID = master_io_channels_read_address_channel_ARVALID; // @[src/main/scala/peripheral/DummyMaster.scala 27:22] + assign io_channels_read_address_channel_ARADDR = master_io_channels_read_address_channel_ARADDR; // @[src/main/scala/peripheral/DummyMaster.scala 27:22] + assign io_channels_read_data_channel_RREADY = master_io_channels_read_data_channel_RREADY; // @[src/main/scala/peripheral/DummyMaster.scala 27:22] + assign master_clock = clock; + assign master_reset = reset; + assign master_io_channels_write_address_channel_AWREADY = io_channels_write_address_channel_AWREADY; // @[src/main/scala/peripheral/DummyMaster.scala 27:22] + assign master_io_channels_write_data_channel_WREADY = io_channels_write_data_channel_WREADY; // @[src/main/scala/peripheral/DummyMaster.scala 27:22] + assign master_io_channels_write_response_channel_BVALID = io_channels_write_response_channel_BVALID; // @[src/main/scala/peripheral/DummyMaster.scala 27:22] + assign master_io_channels_read_address_channel_ARREADY = io_channels_read_address_channel_ARREADY; // @[src/main/scala/peripheral/DummyMaster.scala 27:22] + assign master_io_channels_read_data_channel_RVALID = io_channels_read_data_channel_RVALID; // @[src/main/scala/peripheral/DummyMaster.scala 27:22] + assign master_io_channels_read_data_channel_RDATA = io_channels_read_data_channel_RDATA; // @[src/main/scala/peripheral/DummyMaster.scala 27:22] + assign master_io_channels_read_data_channel_RRESP = 2'h0; // @[src/main/scala/peripheral/DummyMaster.scala 27:22] + assign master_io_bundle_read = 1'h0; // @[src/main/scala/peripheral/DummyMaster.scala 31:25] + assign master_io_bundle_write = 1'h0; // @[src/main/scala/peripheral/DummyMaster.scala 30:26] + assign master_io_bundle_write_data = 32'h0; // @[src/main/scala/peripheral/DummyMaster.scala 29:31] + assign master_io_bundle_write_strobe_0 = 1'h0; // @[src/main/scala/peripheral/DummyMaster.scala 28:{43,43}] + assign master_io_bundle_write_strobe_1 = 1'h0; // @[src/main/scala/peripheral/DummyMaster.scala 28:{43,43}] + assign master_io_bundle_write_strobe_2 = 1'h0; // @[src/main/scala/peripheral/DummyMaster.scala 28:{43,43}] + assign master_io_bundle_write_strobe_3 = 1'h0; // @[src/main/scala/peripheral/DummyMaster.scala 28:{43,43}] + assign master_io_bundle_address = 32'h0; // @[src/main/scala/peripheral/DummyMaster.scala 32:28] +endmodule +module BusSwitch( + input clock, + input reset, + input [31:0] io_address, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output io_slaves_0_write_address_channel_AWVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_0_write_address_channel_AWREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output [31:0] io_slaves_0_write_address_channel_AWADDR, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output io_slaves_0_write_data_channel_WVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_0_write_data_channel_WREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output [31:0] io_slaves_0_write_data_channel_WDATA, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output [3:0] io_slaves_0_write_data_channel_WSTRB, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_0_write_response_channel_BVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output io_slaves_0_write_response_channel_BREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output io_slaves_0_read_address_channel_ARVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_0_read_address_channel_ARREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output [31:0] io_slaves_0_read_address_channel_ARADDR, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_0_read_data_channel_RVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output io_slaves_0_read_data_channel_RREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input [31:0] io_slaves_0_read_data_channel_RDATA, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_1_write_address_channel_AWREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_1_write_data_channel_WREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_1_write_response_channel_BVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_1_read_address_channel_ARREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_1_read_data_channel_RVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input [31:0] io_slaves_1_read_data_channel_RDATA, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output io_slaves_2_write_address_channel_AWVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_2_write_address_channel_AWREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output [31:0] io_slaves_2_write_address_channel_AWADDR, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output io_slaves_2_write_data_channel_WVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_2_write_data_channel_WREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output [31:0] io_slaves_2_write_data_channel_WDATA, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_2_write_response_channel_BVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output io_slaves_2_write_response_channel_BREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output io_slaves_2_read_address_channel_ARVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_2_read_address_channel_ARREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output [31:0] io_slaves_2_read_address_channel_ARADDR, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_2_read_data_channel_RVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output io_slaves_2_read_data_channel_RREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input [31:0] io_slaves_2_read_data_channel_RDATA, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_3_write_address_channel_AWREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_3_write_data_channel_WREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_3_write_response_channel_BVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_3_read_address_channel_ARREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_3_read_data_channel_RVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input [31:0] io_slaves_3_read_data_channel_RDATA, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output io_slaves_4_write_address_channel_AWVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_4_write_address_channel_AWREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output [31:0] io_slaves_4_write_address_channel_AWADDR, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output io_slaves_4_write_data_channel_WVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_4_write_data_channel_WREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output [31:0] io_slaves_4_write_data_channel_WDATA, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_4_write_response_channel_BVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output io_slaves_4_write_response_channel_BREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output io_slaves_4_read_address_channel_ARVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_4_read_address_channel_ARREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output [31:0] io_slaves_4_read_address_channel_ARADDR, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_4_read_data_channel_RVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output io_slaves_4_read_data_channel_RREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input [31:0] io_slaves_4_read_data_channel_RDATA, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_5_write_address_channel_AWREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_5_write_data_channel_WREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_5_write_response_channel_BVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_5_read_address_channel_ARREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_5_read_data_channel_RVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input [31:0] io_slaves_5_read_data_channel_RDATA, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_6_write_address_channel_AWREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_6_write_data_channel_WREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_6_write_response_channel_BVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_6_read_address_channel_ARREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_6_read_data_channel_RVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input [31:0] io_slaves_6_read_data_channel_RDATA, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_7_write_address_channel_AWREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_7_write_data_channel_WREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_7_write_response_channel_BVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_7_read_address_channel_ARREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_slaves_7_read_data_channel_RVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input [31:0] io_slaves_7_read_data_channel_RDATA, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_master_write_address_channel_AWVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output io_master_write_address_channel_AWREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input [31:0] io_master_write_address_channel_AWADDR, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_master_write_data_channel_WVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output io_master_write_data_channel_WREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input [31:0] io_master_write_data_channel_WDATA, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input [3:0] io_master_write_data_channel_WSTRB, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output io_master_write_response_channel_BVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_master_write_response_channel_BREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_master_read_address_channel_ARVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output io_master_read_address_channel_ARREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input [31:0] io_master_read_address_channel_ARADDR, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output io_master_read_data_channel_RVALID, // @[src/main/scala/bus/BusSwitch.scala 22:14] + input io_master_read_data_channel_RREADY, // @[src/main/scala/bus/BusSwitch.scala 22:14] + output [31:0] io_master_read_data_channel_RDATA // @[src/main/scala/bus/BusSwitch.scala 22:14] +); + wire dummy_clock; // @[src/main/scala/bus/BusSwitch.scala 27:21] + wire dummy_reset; // @[src/main/scala/bus/BusSwitch.scala 27:21] + wire dummy_io_channels_write_address_channel_AWVALID; // @[src/main/scala/bus/BusSwitch.scala 27:21] + wire dummy_io_channels_write_address_channel_AWREADY; // @[src/main/scala/bus/BusSwitch.scala 27:21] + wire [31:0] dummy_io_channels_write_address_channel_AWADDR; // @[src/main/scala/bus/BusSwitch.scala 27:21] + wire dummy_io_channels_write_data_channel_WVALID; // @[src/main/scala/bus/BusSwitch.scala 27:21] + wire dummy_io_channels_write_data_channel_WREADY; // @[src/main/scala/bus/BusSwitch.scala 27:21] + wire [31:0] dummy_io_channels_write_data_channel_WDATA; // @[src/main/scala/bus/BusSwitch.scala 27:21] + wire [3:0] dummy_io_channels_write_data_channel_WSTRB; // @[src/main/scala/bus/BusSwitch.scala 27:21] + wire dummy_io_channels_write_response_channel_BVALID; // @[src/main/scala/bus/BusSwitch.scala 27:21] + wire dummy_io_channels_write_response_channel_BREADY; // @[src/main/scala/bus/BusSwitch.scala 27:21] + wire dummy_io_channels_read_address_channel_ARVALID; // @[src/main/scala/bus/BusSwitch.scala 27:21] + wire dummy_io_channels_read_address_channel_ARREADY; // @[src/main/scala/bus/BusSwitch.scala 27:21] + wire [31:0] dummy_io_channels_read_address_channel_ARADDR; // @[src/main/scala/bus/BusSwitch.scala 27:21] + wire dummy_io_channels_read_data_channel_RVALID; // @[src/main/scala/bus/BusSwitch.scala 27:21] + wire dummy_io_channels_read_data_channel_RREADY; // @[src/main/scala/bus/BusSwitch.scala 27:21] + wire [31:0] dummy_io_channels_read_data_channel_RDATA; // @[src/main/scala/bus/BusSwitch.scala 27:21] + wire [2:0] index = io_address[31:29]; // @[src/main/scala/bus/BusSwitch.scala 28:25] + wire _GEN_9 = 3'h1 == index ? io_slaves_1_write_address_channel_AWREADY : io_slaves_0_write_address_channel_AWREADY; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_10 = 3'h2 == index ? io_slaves_2_write_address_channel_AWREADY : _GEN_9; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_11 = 3'h3 == index ? io_slaves_3_write_address_channel_AWREADY : _GEN_10; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_12 = 3'h4 == index ? io_slaves_4_write_address_channel_AWREADY : _GEN_11; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_13 = 3'h5 == index ? io_slaves_5_write_address_channel_AWREADY : _GEN_12; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_14 = 3'h6 == index ? io_slaves_6_write_address_channel_AWREADY : _GEN_13; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_41 = 3'h1 == index ? io_slaves_1_write_data_channel_WREADY : io_slaves_0_write_data_channel_WREADY; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_42 = 3'h2 == index ? io_slaves_2_write_data_channel_WREADY : _GEN_41; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_43 = 3'h3 == index ? io_slaves_3_write_data_channel_WREADY : _GEN_42; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_44 = 3'h4 == index ? io_slaves_4_write_data_channel_WREADY : _GEN_43; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_45 = 3'h5 == index ? io_slaves_5_write_data_channel_WREADY : _GEN_44; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_46 = 3'h6 == index ? io_slaves_6_write_data_channel_WREADY : _GEN_45; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_65 = 3'h1 == index ? io_slaves_1_write_response_channel_BVALID : io_slaves_0_write_response_channel_BVALID; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_66 = 3'h2 == index ? io_slaves_2_write_response_channel_BVALID : _GEN_65; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_67 = 3'h3 == index ? io_slaves_3_write_response_channel_BVALID : _GEN_66; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_68 = 3'h4 == index ? io_slaves_4_write_response_channel_BVALID : _GEN_67; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_69 = 3'h5 == index ? io_slaves_5_write_response_channel_BVALID : _GEN_68; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_70 = 3'h6 == index ? io_slaves_6_write_response_channel_BVALID : _GEN_69; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_97 = 3'h1 == index ? io_slaves_1_read_address_channel_ARREADY : io_slaves_0_read_address_channel_ARREADY; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_98 = 3'h2 == index ? io_slaves_2_read_address_channel_ARREADY : _GEN_97; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_99 = 3'h3 == index ? io_slaves_3_read_address_channel_ARREADY : _GEN_98; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_100 = 3'h4 == index ? io_slaves_4_read_address_channel_ARREADY : _GEN_99; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_101 = 3'h5 == index ? io_slaves_5_read_address_channel_ARREADY : _GEN_100; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_102 = 3'h6 == index ? io_slaves_6_read_address_channel_ARREADY : _GEN_101; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_121 = 3'h1 == index ? io_slaves_1_read_data_channel_RVALID : io_slaves_0_read_data_channel_RVALID; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_122 = 3'h2 == index ? io_slaves_2_read_data_channel_RVALID : _GEN_121; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_123 = 3'h3 == index ? io_slaves_3_read_data_channel_RVALID : _GEN_122; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_124 = 3'h4 == index ? io_slaves_4_read_data_channel_RVALID : _GEN_123; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_125 = 3'h5 == index ? io_slaves_5_read_data_channel_RVALID : _GEN_124; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire _GEN_126 = 3'h6 == index ? io_slaves_6_read_data_channel_RVALID : _GEN_125; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire [31:0] _GEN_137 = 3'h1 == index ? io_slaves_1_read_data_channel_RDATA : io_slaves_0_read_data_channel_RDATA; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire [31:0] _GEN_138 = 3'h2 == index ? io_slaves_2_read_data_channel_RDATA : _GEN_137; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire [31:0] _GEN_139 = 3'h3 == index ? io_slaves_3_read_data_channel_RDATA : _GEN_138; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire [31:0] _GEN_140 = 3'h4 == index ? io_slaves_4_read_data_channel_RDATA : _GEN_139; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire [31:0] _GEN_141 = 3'h5 == index ? io_slaves_5_read_data_channel_RDATA : _GEN_140; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + wire [31:0] _GEN_142 = 3'h6 == index ? io_slaves_6_read_data_channel_RDATA : _GEN_141; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + DummyMaster dummy ( // @[src/main/scala/bus/BusSwitch.scala 27:21] + .clock(dummy_clock), + .reset(dummy_reset), + .io_channels_write_address_channel_AWVALID(dummy_io_channels_write_address_channel_AWVALID), + .io_channels_write_address_channel_AWREADY(dummy_io_channels_write_address_channel_AWREADY), + .io_channels_write_address_channel_AWADDR(dummy_io_channels_write_address_channel_AWADDR), + .io_channels_write_data_channel_WVALID(dummy_io_channels_write_data_channel_WVALID), + .io_channels_write_data_channel_WREADY(dummy_io_channels_write_data_channel_WREADY), + .io_channels_write_data_channel_WDATA(dummy_io_channels_write_data_channel_WDATA), + .io_channels_write_data_channel_WSTRB(dummy_io_channels_write_data_channel_WSTRB), + .io_channels_write_response_channel_BVALID(dummy_io_channels_write_response_channel_BVALID), + .io_channels_write_response_channel_BREADY(dummy_io_channels_write_response_channel_BREADY), + .io_channels_read_address_channel_ARVALID(dummy_io_channels_read_address_channel_ARVALID), + .io_channels_read_address_channel_ARREADY(dummy_io_channels_read_address_channel_ARREADY), + .io_channels_read_address_channel_ARADDR(dummy_io_channels_read_address_channel_ARADDR), + .io_channels_read_data_channel_RVALID(dummy_io_channels_read_data_channel_RVALID), + .io_channels_read_data_channel_RREADY(dummy_io_channels_read_data_channel_RREADY), + .io_channels_read_data_channel_RDATA(dummy_io_channels_read_data_channel_RDATA) + ); + assign io_slaves_0_write_address_channel_AWVALID = 3'h0 == index ? io_master_write_address_channel_AWVALID : + dummy_io_channels_write_address_channel_AWVALID; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13} 30:18] + assign io_slaves_0_write_address_channel_AWADDR = 3'h0 == index ? io_master_write_address_channel_AWADDR : + dummy_io_channels_write_address_channel_AWADDR; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13} 30:18] + assign io_slaves_0_write_data_channel_WVALID = 3'h0 == index ? io_master_write_data_channel_WVALID : + dummy_io_channels_write_data_channel_WVALID; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13} 30:18] + assign io_slaves_0_write_data_channel_WDATA = 3'h0 == index ? io_master_write_data_channel_WDATA : + dummy_io_channels_write_data_channel_WDATA; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13} 30:18] + assign io_slaves_0_write_data_channel_WSTRB = 3'h0 == index ? io_master_write_data_channel_WSTRB : + dummy_io_channels_write_data_channel_WSTRB; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13} 30:18] + assign io_slaves_0_write_response_channel_BREADY = 3'h0 == index ? io_master_write_response_channel_BREADY : + dummy_io_channels_write_response_channel_BREADY; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13} 30:18] + assign io_slaves_0_read_address_channel_ARVALID = 3'h0 == index ? io_master_read_address_channel_ARVALID : + dummy_io_channels_read_address_channel_ARVALID; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13} 30:18] + assign io_slaves_0_read_address_channel_ARADDR = 3'h0 == index ? io_master_read_address_channel_ARADDR : + dummy_io_channels_read_address_channel_ARADDR; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13} 30:18] + assign io_slaves_0_read_data_channel_RREADY = 3'h0 == index ? io_master_read_data_channel_RREADY : + dummy_io_channels_read_data_channel_RREADY; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13} 30:18] + assign io_slaves_2_write_address_channel_AWVALID = 3'h2 == index ? io_master_write_address_channel_AWVALID : + dummy_io_channels_write_address_channel_AWVALID; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13} 30:18] + assign io_slaves_2_write_address_channel_AWADDR = 3'h2 == index ? io_master_write_address_channel_AWADDR : + dummy_io_channels_write_address_channel_AWADDR; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13} 30:18] + assign io_slaves_2_write_data_channel_WVALID = 3'h2 == index ? io_master_write_data_channel_WVALID : + dummy_io_channels_write_data_channel_WVALID; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13} 30:18] + assign io_slaves_2_write_data_channel_WDATA = 3'h2 == index ? io_master_write_data_channel_WDATA : + dummy_io_channels_write_data_channel_WDATA; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13} 30:18] + assign io_slaves_2_write_response_channel_BREADY = 3'h2 == index ? io_master_write_response_channel_BREADY : + dummy_io_channels_write_response_channel_BREADY; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13} 30:18] + assign io_slaves_2_read_address_channel_ARVALID = 3'h2 == index ? io_master_read_address_channel_ARVALID : + dummy_io_channels_read_address_channel_ARVALID; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13} 30:18] + assign io_slaves_2_read_address_channel_ARADDR = 3'h2 == index ? io_master_read_address_channel_ARADDR : + dummy_io_channels_read_address_channel_ARADDR; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13} 30:18] + assign io_slaves_2_read_data_channel_RREADY = 3'h2 == index ? io_master_read_data_channel_RREADY : + dummy_io_channels_read_data_channel_RREADY; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13} 30:18] + assign io_slaves_4_write_address_channel_AWVALID = 3'h4 == index ? io_master_write_address_channel_AWVALID : + dummy_io_channels_write_address_channel_AWVALID; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13} 30:18] + assign io_slaves_4_write_address_channel_AWADDR = 3'h4 == index ? io_master_write_address_channel_AWADDR : + dummy_io_channels_write_address_channel_AWADDR; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13} 30:18] + assign io_slaves_4_write_data_channel_WVALID = 3'h4 == index ? io_master_write_data_channel_WVALID : + dummy_io_channels_write_data_channel_WVALID; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13} 30:18] + assign io_slaves_4_write_data_channel_WDATA = 3'h4 == index ? io_master_write_data_channel_WDATA : + dummy_io_channels_write_data_channel_WDATA; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13} 30:18] + assign io_slaves_4_write_response_channel_BREADY = 3'h4 == index ? io_master_write_response_channel_BREADY : + dummy_io_channels_write_response_channel_BREADY; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13} 30:18] + assign io_slaves_4_read_address_channel_ARVALID = 3'h4 == index ? io_master_read_address_channel_ARVALID : + dummy_io_channels_read_address_channel_ARVALID; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13} 30:18] + assign io_slaves_4_read_address_channel_ARADDR = 3'h4 == index ? io_master_read_address_channel_ARADDR : + dummy_io_channels_read_address_channel_ARADDR; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13} 30:18] + assign io_slaves_4_read_data_channel_RREADY = 3'h4 == index ? io_master_read_data_channel_RREADY : + dummy_io_channels_read_data_channel_RREADY; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13} 30:18] + assign io_master_write_address_channel_AWREADY = 3'h7 == index ? io_slaves_7_write_address_channel_AWREADY : _GEN_14; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + assign io_master_write_data_channel_WREADY = 3'h7 == index ? io_slaves_7_write_data_channel_WREADY : _GEN_46; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + assign io_master_write_response_channel_BVALID = 3'h7 == index ? io_slaves_7_write_response_channel_BVALID : _GEN_70; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + assign io_master_read_address_channel_ARREADY = 3'h7 == index ? io_slaves_7_read_address_channel_ARREADY : _GEN_102; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + assign io_master_read_data_channel_RVALID = 3'h7 == index ? io_slaves_7_read_data_channel_RVALID : _GEN_126; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + assign io_master_read_data_channel_RDATA = 3'h7 == index ? io_slaves_7_read_data_channel_RDATA : _GEN_142; // @[src/main/scala/bus/BusSwitch.scala 32:{13,13}] + assign dummy_clock = clock; + assign dummy_reset = reset; + assign dummy_io_channels_write_address_channel_AWREADY = io_slaves_7_write_address_channel_AWREADY; // @[src/main/scala/bus/BusSwitch.scala 30:18] + assign dummy_io_channels_write_data_channel_WREADY = io_slaves_7_write_data_channel_WREADY; // @[src/main/scala/bus/BusSwitch.scala 30:18] + assign dummy_io_channels_write_response_channel_BVALID = io_slaves_7_write_response_channel_BVALID; // @[src/main/scala/bus/BusSwitch.scala 30:18] + assign dummy_io_channels_read_address_channel_ARREADY = io_slaves_7_read_address_channel_ARREADY; // @[src/main/scala/bus/BusSwitch.scala 30:18] + assign dummy_io_channels_read_data_channel_RVALID = io_slaves_7_read_data_channel_RVALID; // @[src/main/scala/bus/BusSwitch.scala 30:18] + assign dummy_io_channels_read_data_channel_RDATA = io_slaves_7_read_data_channel_RDATA; // @[src/main/scala/bus/BusSwitch.scala 30:18] +endmodule +module InstructionROM( + input clock, + input [31:0] io_address, // @[src/main/scala/peripheral/InstructionROM.scala 28:14] + output [31:0] io_data // @[src/main/scala/peripheral/InstructionROM.scala 28:14] +); +`ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [31:0] _RAND_0; +`endif // RANDOMIZE_GARBAGE_ASSIGN +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; +`endif // RANDOMIZE_REG_INIT + reg [31:0] mem [0:1050]; // @[src/main/scala/peripheral/InstructionROM.scala 34:24] + wire mem_io_data_MPORT_en; // @[src/main/scala/peripheral/InstructionROM.scala 34:24] + wire [10:0] mem_io_data_MPORT_addr; // @[src/main/scala/peripheral/InstructionROM.scala 34:24] + wire [31:0] mem_io_data_MPORT_data; // @[src/main/scala/peripheral/InstructionROM.scala 34:24] + reg mem_io_data_MPORT_en_pipe_0; + reg [10:0] mem_io_data_MPORT_addr_pipe_0; + assign mem_io_data_MPORT_en = mem_io_data_MPORT_en_pipe_0; + assign mem_io_data_MPORT_addr = mem_io_data_MPORT_addr_pipe_0; + `ifndef RANDOMIZE_GARBAGE_ASSIGN + assign mem_io_data_MPORT_data = mem[mem_io_data_MPORT_addr]; // @[src/main/scala/peripheral/InstructionROM.scala 34:24] + `else + assign mem_io_data_MPORT_data = mem_io_data_MPORT_addr >= 11'h41b ? _RAND_0[31:0] : mem[mem_io_data_MPORT_addr]; // @[src/main/scala/peripheral/InstructionROM.scala 34:24] + `endif // RANDOMIZE_GARBAGE_ASSIGN + assign io_data = mem_io_data_MPORT_data; // @[src/main/scala/peripheral/InstructionROM.scala 40:11] + always @(posedge clock) begin + mem_io_data_MPORT_en_pipe_0 <= 1'h1; + if (1'h1) begin + mem_io_data_MPORT_addr_pipe_0 <= io_address[10:0]; + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif + integer initvar; +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_GARBAGE_ASSIGN + _RAND_0 = {1{`RANDOM}}; +`endif // RANDOMIZE_GARBAGE_ASSIGN +`ifdef RANDOMIZE_REG_INIT + _RAND_1 = {1{`RANDOM}}; + mem_io_data_MPORT_en_pipe_0 = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + mem_io_data_MPORT_addr_pipe_0 = _RAND_2[10:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +initial begin + $readmemh("/workspaces/2023-fall-yatcpu-repo/mini-yatcpu/verilog/say_goodbye.asmbin.txt", mem); +end +endmodule +module ROMLoader( + input clock, + input reset, + output io_channels_write_address_channel_AWVALID, // @[src/main/scala/peripheral/ROMLoader.scala 22:14] + input io_channels_write_address_channel_AWREADY, // @[src/main/scala/peripheral/ROMLoader.scala 22:14] + output [31:0] io_channels_write_address_channel_AWADDR, // @[src/main/scala/peripheral/ROMLoader.scala 22:14] + output io_channels_write_data_channel_WVALID, // @[src/main/scala/peripheral/ROMLoader.scala 22:14] + input io_channels_write_data_channel_WREADY, // @[src/main/scala/peripheral/ROMLoader.scala 22:14] + output [31:0] io_channels_write_data_channel_WDATA, // @[src/main/scala/peripheral/ROMLoader.scala 22:14] + output [3:0] io_channels_write_data_channel_WSTRB, // @[src/main/scala/peripheral/ROMLoader.scala 22:14] + input io_channels_write_response_channel_BVALID, // @[src/main/scala/peripheral/ROMLoader.scala 22:14] + output io_channels_write_response_channel_BREADY, // @[src/main/scala/peripheral/ROMLoader.scala 22:14] + output io_channels_read_address_channel_ARVALID, // @[src/main/scala/peripheral/ROMLoader.scala 22:14] + input io_channels_read_address_channel_ARREADY, // @[src/main/scala/peripheral/ROMLoader.scala 22:14] + output [31:0] io_channels_read_address_channel_ARADDR, // @[src/main/scala/peripheral/ROMLoader.scala 22:14] + input io_channels_read_data_channel_RVALID, // @[src/main/scala/peripheral/ROMLoader.scala 22:14] + output io_channels_read_data_channel_RREADY, // @[src/main/scala/peripheral/ROMLoader.scala 22:14] + input [31:0] io_channels_read_data_channel_RDATA, // @[src/main/scala/peripheral/ROMLoader.scala 22:14] + output [31:0] io_rom_address, // @[src/main/scala/peripheral/ROMLoader.scala 22:14] + input [31:0] io_rom_data, // @[src/main/scala/peripheral/ROMLoader.scala 22:14] + input io_load_start, // @[src/main/scala/peripheral/ROMLoader.scala 22:14] + output io_load_finished // @[src/main/scala/peripheral/ROMLoader.scala 22:14] +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; +`endif // RANDOMIZE_REG_INIT + wire master_clock; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire master_reset; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire master_io_channels_write_address_channel_AWVALID; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire master_io_channels_write_address_channel_AWREADY; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire [31:0] master_io_channels_write_address_channel_AWADDR; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire master_io_channels_write_data_channel_WVALID; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire master_io_channels_write_data_channel_WREADY; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire [31:0] master_io_channels_write_data_channel_WDATA; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire [3:0] master_io_channels_write_data_channel_WSTRB; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire master_io_channels_write_response_channel_BVALID; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire master_io_channels_write_response_channel_BREADY; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire master_io_channels_read_address_channel_ARVALID; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire master_io_channels_read_address_channel_ARREADY; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire [31:0] master_io_channels_read_address_channel_ARADDR; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire master_io_channels_read_data_channel_RVALID; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire master_io_channels_read_data_channel_RREADY; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire [31:0] master_io_channels_read_data_channel_RDATA; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire [1:0] master_io_channels_read_data_channel_RRESP; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire master_io_bundle_read; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire master_io_bundle_write; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire [31:0] master_io_bundle_read_data; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire [31:0] master_io_bundle_write_data; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire master_io_bundle_write_strobe_0; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire master_io_bundle_write_strobe_1; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire master_io_bundle_write_strobe_2; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire master_io_bundle_write_strobe_3; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire [31:0] master_io_bundle_address; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire master_io_bundle_busy; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire master_io_bundle_read_valid; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + wire master_io_bundle_write_valid; // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + reg [31:0] address; // @[src/main/scala/peripheral/ROMLoader.scala 35:24] + reg valid; // @[src/main/scala/peripheral/ROMLoader.scala 36:22] + reg loading; // @[src/main/scala/peripheral/ROMLoader.scala 37:24] + wire _GEN_1 = io_load_start | loading; // @[src/main/scala/peripheral/ROMLoader.scala 42:23 44:13 37:24] + wire [31:0] _GEN_2 = io_load_start ? 32'h0 : address; // @[src/main/scala/peripheral/ROMLoader.scala 42:23 45:13 35:24] + wire _T_1 = ~master_io_bundle_busy; // @[src/main/scala/peripheral/ROMLoader.scala 53:20] + wire _T_3 = address >= 32'h41a; // @[src/main/scala/peripheral/ROMLoader.scala 53:54] + wire [33:0] _GEN_34 = {address, 2'h0}; // @[src/main/scala/peripheral/ROMLoader.scala 63:46] + wire [34:0] _master_io_bundle_address_T = {{1'd0}, _GEN_34}; // @[src/main/scala/peripheral/ROMLoader.scala 63:46] + wire [34:0] _master_io_bundle_address_T_2 = _master_io_bundle_address_T + 35'h1000; // @[src/main/scala/peripheral/ROMLoader.scala 63:61] + wire [31:0] _GEN_5 = valid ? io_rom_data : 32'h0; // @[src/main/scala/peripheral/ROMLoader.scala 59:19 49:31 61:37] + wire [34:0] _GEN_10 = valid ? _master_io_bundle_address_T_2 : 35'h0; // @[src/main/scala/peripheral/ROMLoader.scala 59:19 51:28 63:34] + wire _GEN_11 = _T_1 & ~master_io_bundle_write_valid & valid; // @[src/main/scala/peripheral/ROMLoader.scala 48:26 58:67] + wire [31:0] _GEN_12 = _T_1 & ~master_io_bundle_write_valid ? _GEN_5 : 32'h0; // @[src/main/scala/peripheral/ROMLoader.scala 49:31 58:67] + wire [34:0] _GEN_17 = _T_1 & ~master_io_bundle_write_valid ? _GEN_10 : 35'h0; // @[src/main/scala/peripheral/ROMLoader.scala 51:28 58:67] + wire [31:0] _address_T_1 = address + 32'h1; // @[src/main/scala/peripheral/ROMLoader.scala 71:28] + wire [34:0] _GEN_31 = loading ? _GEN_17 : 35'h0; // @[src/main/scala/peripheral/ROMLoader.scala 56:17 51:28] + AXI4LiteMaster master ( // @[src/main/scala/peripheral/ROMLoader.scala 32:22] + .clock(master_clock), + .reset(master_reset), + .io_channels_write_address_channel_AWVALID(master_io_channels_write_address_channel_AWVALID), + .io_channels_write_address_channel_AWREADY(master_io_channels_write_address_channel_AWREADY), + .io_channels_write_address_channel_AWADDR(master_io_channels_write_address_channel_AWADDR), + .io_channels_write_data_channel_WVALID(master_io_channels_write_data_channel_WVALID), + .io_channels_write_data_channel_WREADY(master_io_channels_write_data_channel_WREADY), + .io_channels_write_data_channel_WDATA(master_io_channels_write_data_channel_WDATA), + .io_channels_write_data_channel_WSTRB(master_io_channels_write_data_channel_WSTRB), + .io_channels_write_response_channel_BVALID(master_io_channels_write_response_channel_BVALID), + .io_channels_write_response_channel_BREADY(master_io_channels_write_response_channel_BREADY), + .io_channels_read_address_channel_ARVALID(master_io_channels_read_address_channel_ARVALID), + .io_channels_read_address_channel_ARREADY(master_io_channels_read_address_channel_ARREADY), + .io_channels_read_address_channel_ARADDR(master_io_channels_read_address_channel_ARADDR), + .io_channels_read_data_channel_RVALID(master_io_channels_read_data_channel_RVALID), + .io_channels_read_data_channel_RREADY(master_io_channels_read_data_channel_RREADY), + .io_channels_read_data_channel_RDATA(master_io_channels_read_data_channel_RDATA), + .io_channels_read_data_channel_RRESP(master_io_channels_read_data_channel_RRESP), + .io_bundle_read(master_io_bundle_read), + .io_bundle_write(master_io_bundle_write), + .io_bundle_read_data(master_io_bundle_read_data), + .io_bundle_write_data(master_io_bundle_write_data), + .io_bundle_write_strobe_0(master_io_bundle_write_strobe_0), + .io_bundle_write_strobe_1(master_io_bundle_write_strobe_1), + .io_bundle_write_strobe_2(master_io_bundle_write_strobe_2), + .io_bundle_write_strobe_3(master_io_bundle_write_strobe_3), + .io_bundle_address(master_io_bundle_address), + .io_bundle_busy(master_io_bundle_busy), + .io_bundle_read_valid(master_io_bundle_read_valid), + .io_bundle_write_valid(master_io_bundle_write_valid) + ); + assign io_channels_write_address_channel_AWVALID = master_io_channels_write_address_channel_AWVALID; // @[src/main/scala/peripheral/ROMLoader.scala 33:22] + assign io_channels_write_address_channel_AWADDR = master_io_channels_write_address_channel_AWADDR; // @[src/main/scala/peripheral/ROMLoader.scala 33:22] + assign io_channels_write_data_channel_WVALID = master_io_channels_write_data_channel_WVALID; // @[src/main/scala/peripheral/ROMLoader.scala 33:22] + assign io_channels_write_data_channel_WDATA = master_io_channels_write_data_channel_WDATA; // @[src/main/scala/peripheral/ROMLoader.scala 33:22] + assign io_channels_write_data_channel_WSTRB = master_io_channels_write_data_channel_WSTRB; // @[src/main/scala/peripheral/ROMLoader.scala 33:22] + assign io_channels_write_response_channel_BREADY = master_io_channels_write_response_channel_BREADY; // @[src/main/scala/peripheral/ROMLoader.scala 33:22] + assign io_channels_read_address_channel_ARVALID = master_io_channels_read_address_channel_ARVALID; // @[src/main/scala/peripheral/ROMLoader.scala 33:22] + assign io_channels_read_address_channel_ARADDR = master_io_channels_read_address_channel_ARADDR; // @[src/main/scala/peripheral/ROMLoader.scala 33:22] + assign io_channels_read_data_channel_RREADY = master_io_channels_read_data_channel_RREADY; // @[src/main/scala/peripheral/ROMLoader.scala 33:22] + assign io_rom_address = address; // @[src/main/scala/peripheral/ROMLoader.scala 78:18] + assign io_load_finished = ~loading & ~master_io_bundle_busy & address >= 32'h41a; // @[src/main/scala/peripheral/ROMLoader.scala 53:43] + assign master_clock = clock; + assign master_reset = reset; + assign master_io_channels_write_address_channel_AWREADY = io_channels_write_address_channel_AWREADY; // @[src/main/scala/peripheral/ROMLoader.scala 33:22] + assign master_io_channels_write_data_channel_WREADY = io_channels_write_data_channel_WREADY; // @[src/main/scala/peripheral/ROMLoader.scala 33:22] + assign master_io_channels_write_response_channel_BVALID = io_channels_write_response_channel_BVALID; // @[src/main/scala/peripheral/ROMLoader.scala 33:22] + assign master_io_channels_read_address_channel_ARREADY = io_channels_read_address_channel_ARREADY; // @[src/main/scala/peripheral/ROMLoader.scala 33:22] + assign master_io_channels_read_data_channel_RVALID = io_channels_read_data_channel_RVALID; // @[src/main/scala/peripheral/ROMLoader.scala 33:22] + assign master_io_channels_read_data_channel_RDATA = io_channels_read_data_channel_RDATA; // @[src/main/scala/peripheral/ROMLoader.scala 33:22] + assign master_io_channels_read_data_channel_RRESP = 2'h0; // @[src/main/scala/peripheral/ROMLoader.scala 33:22] + assign master_io_bundle_read = 1'h0; // @[src/main/scala/peripheral/ROMLoader.scala 39:25] + assign master_io_bundle_write = loading & _GEN_11; // @[src/main/scala/peripheral/ROMLoader.scala 56:17 48:26] + assign master_io_bundle_write_data = loading ? _GEN_12 : 32'h0; // @[src/main/scala/peripheral/ROMLoader.scala 56:17 49:31] + assign master_io_bundle_write_strobe_0 = loading & _GEN_11; // @[src/main/scala/peripheral/ROMLoader.scala 56:17 50:33] + assign master_io_bundle_write_strobe_1 = loading & _GEN_11; // @[src/main/scala/peripheral/ROMLoader.scala 56:17 50:33] + assign master_io_bundle_write_strobe_2 = loading & _GEN_11; // @[src/main/scala/peripheral/ROMLoader.scala 56:17 50:33] + assign master_io_bundle_write_strobe_3 = loading & _GEN_11; // @[src/main/scala/peripheral/ROMLoader.scala 56:17 50:33] + assign master_io_bundle_address = _GEN_31[31:0]; + always @(posedge clock) begin + if (reset) begin // @[src/main/scala/peripheral/ROMLoader.scala 35:24] + address <= 32'h0; // @[src/main/scala/peripheral/ROMLoader.scala 35:24] + end else if (loading) begin // @[src/main/scala/peripheral/ROMLoader.scala 56:17] + if (master_io_bundle_write_valid) begin // @[src/main/scala/peripheral/ROMLoader.scala 66:40] + if (_T_3) begin // @[src/main/scala/peripheral/ROMLoader.scala 67:41] + address <= _GEN_2; + end else begin + address <= _address_T_1; // @[src/main/scala/peripheral/ROMLoader.scala 71:17] + end + end + end else begin + address <= _GEN_2; + end + if (reset) begin // @[src/main/scala/peripheral/ROMLoader.scala 36:22] + valid <= 1'h0; // @[src/main/scala/peripheral/ROMLoader.scala 36:22] + end else if (loading) begin // @[src/main/scala/peripheral/ROMLoader.scala 56:17] + if (master_io_bundle_write_valid) begin // @[src/main/scala/peripheral/ROMLoader.scala 66:40] + valid <= _T_3; + end else begin + valid <= 1'h1; // @[src/main/scala/peripheral/ROMLoader.scala 57:11] + end + end else if (io_load_start) begin // @[src/main/scala/peripheral/ROMLoader.scala 42:23] + valid <= 1'h0; // @[src/main/scala/peripheral/ROMLoader.scala 43:11] + end + if (reset) begin // @[src/main/scala/peripheral/ROMLoader.scala 37:24] + loading <= 1'h0; // @[src/main/scala/peripheral/ROMLoader.scala 37:24] + end else if (loading) begin // @[src/main/scala/peripheral/ROMLoader.scala 56:17] + if (master_io_bundle_write_valid) begin // @[src/main/scala/peripheral/ROMLoader.scala 66:40] + if (_T_3) begin // @[src/main/scala/peripheral/ROMLoader.scala 67:41] + loading <= 1'h0; // @[src/main/scala/peripheral/ROMLoader.scala 68:17] + end else begin + loading <= 1'h1; // @[src/main/scala/peripheral/ROMLoader.scala 70:17] + end + end else begin + loading <= _GEN_1; + end + end else begin + loading <= _GEN_1; + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + address = _RAND_0[31:0]; + _RAND_1 = {1{`RANDOM}}; + valid = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + loading = _RAND_2[0:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module Top( + input clock, + input reset, + output io_led, // @[src/main/scala/board/z710/z710/Top.scala 26:14] + output io_tx, // @[src/main/scala/board/z710/z710/Top.scala 26:14] + input io_rx // @[src/main/scala/board/z710/z710/Top.scala 26:14] +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; +`endif // RANDOMIZE_REG_INIT + wire uart_clock; // @[src/main/scala/board/z710/z710/Top.scala 39:20] + wire uart_reset; // @[src/main/scala/board/z710/z710/Top.scala 39:20] + wire uart_io_channels_write_address_channel_AWVALID; // @[src/main/scala/board/z710/z710/Top.scala 39:20] + wire uart_io_channels_write_address_channel_AWREADY; // @[src/main/scala/board/z710/z710/Top.scala 39:20] + wire [7:0] uart_io_channels_write_address_channel_AWADDR; // @[src/main/scala/board/z710/z710/Top.scala 39:20] + wire uart_io_channels_write_data_channel_WVALID; // @[src/main/scala/board/z710/z710/Top.scala 39:20] + wire uart_io_channels_write_data_channel_WREADY; // @[src/main/scala/board/z710/z710/Top.scala 39:20] + wire [31:0] uart_io_channels_write_data_channel_WDATA; // @[src/main/scala/board/z710/z710/Top.scala 39:20] + wire uart_io_channels_write_response_channel_BVALID; // @[src/main/scala/board/z710/z710/Top.scala 39:20] + wire uart_io_channels_write_response_channel_BREADY; // @[src/main/scala/board/z710/z710/Top.scala 39:20] + wire uart_io_channels_read_address_channel_ARVALID; // @[src/main/scala/board/z710/z710/Top.scala 39:20] + wire uart_io_channels_read_address_channel_ARREADY; // @[src/main/scala/board/z710/z710/Top.scala 39:20] + wire [7:0] uart_io_channels_read_address_channel_ARADDR; // @[src/main/scala/board/z710/z710/Top.scala 39:20] + wire uart_io_channels_read_data_channel_RVALID; // @[src/main/scala/board/z710/z710/Top.scala 39:20] + wire uart_io_channels_read_data_channel_RREADY; // @[src/main/scala/board/z710/z710/Top.scala 39:20] + wire [31:0] uart_io_channels_read_data_channel_RDATA; // @[src/main/scala/board/z710/z710/Top.scala 39:20] + wire uart_io_rxd; // @[src/main/scala/board/z710/z710/Top.scala 39:20] + wire uart_io_txd; // @[src/main/scala/board/z710/z710/Top.scala 39:20] + wire uart_io_signal_interrupt; // @[src/main/scala/board/z710/z710/Top.scala 39:20] + wire cpu_clock; // @[src/main/scala/board/z710/z710/Top.scala 43:19] + wire cpu_reset; // @[src/main/scala/board/z710/z710/Top.scala 43:19] + wire cpu_io_axi4_channels_write_address_channel_AWVALID; // @[src/main/scala/board/z710/z710/Top.scala 43:19] + wire cpu_io_axi4_channels_write_address_channel_AWREADY; // @[src/main/scala/board/z710/z710/Top.scala 43:19] + wire [31:0] cpu_io_axi4_channels_write_address_channel_AWADDR; // @[src/main/scala/board/z710/z710/Top.scala 43:19] + wire cpu_io_axi4_channels_write_data_channel_WVALID; // @[src/main/scala/board/z710/z710/Top.scala 43:19] + wire cpu_io_axi4_channels_write_data_channel_WREADY; // @[src/main/scala/board/z710/z710/Top.scala 43:19] + wire [31:0] cpu_io_axi4_channels_write_data_channel_WDATA; // @[src/main/scala/board/z710/z710/Top.scala 43:19] + wire [3:0] cpu_io_axi4_channels_write_data_channel_WSTRB; // @[src/main/scala/board/z710/z710/Top.scala 43:19] + wire cpu_io_axi4_channels_write_response_channel_BVALID; // @[src/main/scala/board/z710/z710/Top.scala 43:19] + wire cpu_io_axi4_channels_write_response_channel_BREADY; // @[src/main/scala/board/z710/z710/Top.scala 43:19] + wire cpu_io_axi4_channels_read_address_channel_ARVALID; // @[src/main/scala/board/z710/z710/Top.scala 43:19] + wire cpu_io_axi4_channels_read_address_channel_ARREADY; // @[src/main/scala/board/z710/z710/Top.scala 43:19] + wire [31:0] cpu_io_axi4_channels_read_address_channel_ARADDR; // @[src/main/scala/board/z710/z710/Top.scala 43:19] + wire cpu_io_axi4_channels_read_data_channel_RVALID; // @[src/main/scala/board/z710/z710/Top.scala 43:19] + wire cpu_io_axi4_channels_read_data_channel_RREADY; // @[src/main/scala/board/z710/z710/Top.scala 43:19] + wire [31:0] cpu_io_axi4_channels_read_data_channel_RDATA; // @[src/main/scala/board/z710/z710/Top.scala 43:19] + wire [31:0] cpu_io_bus_address; // @[src/main/scala/board/z710/z710/Top.scala 43:19] + wire [31:0] cpu_io_interrupt_flag; // @[src/main/scala/board/z710/z710/Top.scala 43:19] + wire cpu_io_stall_flag_bus; // @[src/main/scala/board/z710/z710/Top.scala 43:19] + wire cpu_io_instruction_valid; // @[src/main/scala/board/z710/z710/Top.scala 43:19] + wire mem_clock; // @[src/main/scala/board/z710/z710/Top.scala 44:19] + wire mem_reset; // @[src/main/scala/board/z710/z710/Top.scala 44:19] + wire mem_io_channels_write_address_channel_AWVALID; // @[src/main/scala/board/z710/z710/Top.scala 44:19] + wire mem_io_channels_write_address_channel_AWREADY; // @[src/main/scala/board/z710/z710/Top.scala 44:19] + wire [31:0] mem_io_channels_write_address_channel_AWADDR; // @[src/main/scala/board/z710/z710/Top.scala 44:19] + wire mem_io_channels_write_data_channel_WVALID; // @[src/main/scala/board/z710/z710/Top.scala 44:19] + wire mem_io_channels_write_data_channel_WREADY; // @[src/main/scala/board/z710/z710/Top.scala 44:19] + wire [31:0] mem_io_channels_write_data_channel_WDATA; // @[src/main/scala/board/z710/z710/Top.scala 44:19] + wire [3:0] mem_io_channels_write_data_channel_WSTRB; // @[src/main/scala/board/z710/z710/Top.scala 44:19] + wire mem_io_channels_write_response_channel_BVALID; // @[src/main/scala/board/z710/z710/Top.scala 44:19] + wire mem_io_channels_write_response_channel_BREADY; // @[src/main/scala/board/z710/z710/Top.scala 44:19] + wire mem_io_channels_read_address_channel_ARVALID; // @[src/main/scala/board/z710/z710/Top.scala 44:19] + wire mem_io_channels_read_address_channel_ARREADY; // @[src/main/scala/board/z710/z710/Top.scala 44:19] + wire [31:0] mem_io_channels_read_address_channel_ARADDR; // @[src/main/scala/board/z710/z710/Top.scala 44:19] + wire mem_io_channels_read_data_channel_RVALID; // @[src/main/scala/board/z710/z710/Top.scala 44:19] + wire mem_io_channels_read_data_channel_RREADY; // @[src/main/scala/board/z710/z710/Top.scala 44:19] + wire [31:0] mem_io_channels_read_data_channel_RDATA; // @[src/main/scala/board/z710/z710/Top.scala 44:19] + wire timer_clock; // @[src/main/scala/board/z710/z710/Top.scala 45:21] + wire timer_reset; // @[src/main/scala/board/z710/z710/Top.scala 45:21] + wire timer_io_channels_write_address_channel_AWVALID; // @[src/main/scala/board/z710/z710/Top.scala 45:21] + wire timer_io_channels_write_address_channel_AWREADY; // @[src/main/scala/board/z710/z710/Top.scala 45:21] + wire [7:0] timer_io_channels_write_address_channel_AWADDR; // @[src/main/scala/board/z710/z710/Top.scala 45:21] + wire timer_io_channels_write_data_channel_WVALID; // @[src/main/scala/board/z710/z710/Top.scala 45:21] + wire timer_io_channels_write_data_channel_WREADY; // @[src/main/scala/board/z710/z710/Top.scala 45:21] + wire [31:0] timer_io_channels_write_data_channel_WDATA; // @[src/main/scala/board/z710/z710/Top.scala 45:21] + wire timer_io_channels_write_response_channel_BVALID; // @[src/main/scala/board/z710/z710/Top.scala 45:21] + wire timer_io_channels_write_response_channel_BREADY; // @[src/main/scala/board/z710/z710/Top.scala 45:21] + wire timer_io_channels_read_address_channel_ARVALID; // @[src/main/scala/board/z710/z710/Top.scala 45:21] + wire timer_io_channels_read_address_channel_ARREADY; // @[src/main/scala/board/z710/z710/Top.scala 45:21] + wire [7:0] timer_io_channels_read_address_channel_ARADDR; // @[src/main/scala/board/z710/z710/Top.scala 45:21] + wire timer_io_channels_read_data_channel_RVALID; // @[src/main/scala/board/z710/z710/Top.scala 45:21] + wire timer_io_channels_read_data_channel_RREADY; // @[src/main/scala/board/z710/z710/Top.scala 45:21] + wire [31:0] timer_io_channels_read_data_channel_RDATA; // @[src/main/scala/board/z710/z710/Top.scala 45:21] + wire timer_io_signal_interrupt; // @[src/main/scala/board/z710/z710/Top.scala 45:21] + wire dummy_clock; // @[src/main/scala/board/z710/z710/Top.scala 46:21] + wire dummy_reset; // @[src/main/scala/board/z710/z710/Top.scala 46:21] + wire dummy_io_channels_write_address_channel_AWVALID; // @[src/main/scala/board/z710/z710/Top.scala 46:21] + wire dummy_io_channels_write_address_channel_AWREADY; // @[src/main/scala/board/z710/z710/Top.scala 46:21] + wire [3:0] dummy_io_channels_write_address_channel_AWADDR; // @[src/main/scala/board/z710/z710/Top.scala 46:21] + wire dummy_io_channels_write_data_channel_WVALID; // @[src/main/scala/board/z710/z710/Top.scala 46:21] + wire dummy_io_channels_write_data_channel_WREADY; // @[src/main/scala/board/z710/z710/Top.scala 46:21] + wire [31:0] dummy_io_channels_write_data_channel_WDATA; // @[src/main/scala/board/z710/z710/Top.scala 46:21] + wire [3:0] dummy_io_channels_write_data_channel_WSTRB; // @[src/main/scala/board/z710/z710/Top.scala 46:21] + wire dummy_io_channels_write_response_channel_BVALID; // @[src/main/scala/board/z710/z710/Top.scala 46:21] + wire dummy_io_channels_write_response_channel_BREADY; // @[src/main/scala/board/z710/z710/Top.scala 46:21] + wire dummy_io_channels_read_address_channel_ARVALID; // @[src/main/scala/board/z710/z710/Top.scala 46:21] + wire dummy_io_channels_read_address_channel_ARREADY; // @[src/main/scala/board/z710/z710/Top.scala 46:21] + wire [3:0] dummy_io_channels_read_address_channel_ARADDR; // @[src/main/scala/board/z710/z710/Top.scala 46:21] + wire dummy_io_channels_read_data_channel_RVALID; // @[src/main/scala/board/z710/z710/Top.scala 46:21] + wire dummy_io_channels_read_data_channel_RREADY; // @[src/main/scala/board/z710/z710/Top.scala 46:21] + wire [31:0] dummy_io_channels_read_data_channel_RDATA; // @[src/main/scala/board/z710/z710/Top.scala 46:21] + wire bus_switch_clock; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_reset; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire [31:0] bus_switch_io_address; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_0_write_address_channel_AWVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_0_write_address_channel_AWREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire [31:0] bus_switch_io_slaves_0_write_address_channel_AWADDR; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_0_write_data_channel_WVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_0_write_data_channel_WREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire [31:0] bus_switch_io_slaves_0_write_data_channel_WDATA; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire [3:0] bus_switch_io_slaves_0_write_data_channel_WSTRB; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_0_write_response_channel_BVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_0_write_response_channel_BREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_0_read_address_channel_ARVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_0_read_address_channel_ARREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire [31:0] bus_switch_io_slaves_0_read_address_channel_ARADDR; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_0_read_data_channel_RVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_0_read_data_channel_RREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire [31:0] bus_switch_io_slaves_0_read_data_channel_RDATA; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_1_write_address_channel_AWREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_1_write_data_channel_WREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_1_write_response_channel_BVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_1_read_address_channel_ARREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_1_read_data_channel_RVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire [31:0] bus_switch_io_slaves_1_read_data_channel_RDATA; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_2_write_address_channel_AWVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_2_write_address_channel_AWREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire [31:0] bus_switch_io_slaves_2_write_address_channel_AWADDR; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_2_write_data_channel_WVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_2_write_data_channel_WREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire [31:0] bus_switch_io_slaves_2_write_data_channel_WDATA; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_2_write_response_channel_BVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_2_write_response_channel_BREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_2_read_address_channel_ARVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_2_read_address_channel_ARREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire [31:0] bus_switch_io_slaves_2_read_address_channel_ARADDR; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_2_read_data_channel_RVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_2_read_data_channel_RREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire [31:0] bus_switch_io_slaves_2_read_data_channel_RDATA; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_3_write_address_channel_AWREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_3_write_data_channel_WREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_3_write_response_channel_BVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_3_read_address_channel_ARREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_3_read_data_channel_RVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire [31:0] bus_switch_io_slaves_3_read_data_channel_RDATA; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_4_write_address_channel_AWVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_4_write_address_channel_AWREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire [31:0] bus_switch_io_slaves_4_write_address_channel_AWADDR; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_4_write_data_channel_WVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_4_write_data_channel_WREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire [31:0] bus_switch_io_slaves_4_write_data_channel_WDATA; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_4_write_response_channel_BVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_4_write_response_channel_BREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_4_read_address_channel_ARVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_4_read_address_channel_ARREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire [31:0] bus_switch_io_slaves_4_read_address_channel_ARADDR; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_4_read_data_channel_RVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_4_read_data_channel_RREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire [31:0] bus_switch_io_slaves_4_read_data_channel_RDATA; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_5_write_address_channel_AWREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_5_write_data_channel_WREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_5_write_response_channel_BVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_5_read_address_channel_ARREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_5_read_data_channel_RVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire [31:0] bus_switch_io_slaves_5_read_data_channel_RDATA; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_6_write_address_channel_AWREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_6_write_data_channel_WREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_6_write_response_channel_BVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_6_read_address_channel_ARREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_6_read_data_channel_RVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire [31:0] bus_switch_io_slaves_6_read_data_channel_RDATA; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_7_write_address_channel_AWREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_7_write_data_channel_WREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_7_write_response_channel_BVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_7_read_address_channel_ARREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_slaves_7_read_data_channel_RVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire [31:0] bus_switch_io_slaves_7_read_data_channel_RDATA; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_master_write_address_channel_AWVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_master_write_address_channel_AWREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire [31:0] bus_switch_io_master_write_address_channel_AWADDR; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_master_write_data_channel_WVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_master_write_data_channel_WREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire [31:0] bus_switch_io_master_write_data_channel_WDATA; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire [3:0] bus_switch_io_master_write_data_channel_WSTRB; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_master_write_response_channel_BVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_master_write_response_channel_BREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_master_read_address_channel_ARVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_master_read_address_channel_ARREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire [31:0] bus_switch_io_master_read_address_channel_ARADDR; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_master_read_data_channel_RVALID; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire bus_switch_io_master_read_data_channel_RREADY; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire [31:0] bus_switch_io_master_read_data_channel_RDATA; // @[src/main/scala/board/z710/z710/Top.scala 48:26] + wire instruction_rom_clock; // @[src/main/scala/board/z710/z710/Top.scala 50:31] + wire [31:0] instruction_rom_io_address; // @[src/main/scala/board/z710/z710/Top.scala 50:31] + wire [31:0] instruction_rom_io_data; // @[src/main/scala/board/z710/z710/Top.scala 50:31] + wire rom_loader_clock; // @[src/main/scala/board/z710/z710/Top.scala 51:26] + wire rom_loader_reset; // @[src/main/scala/board/z710/z710/Top.scala 51:26] + wire rom_loader_io_channels_write_address_channel_AWVALID; // @[src/main/scala/board/z710/z710/Top.scala 51:26] + wire rom_loader_io_channels_write_address_channel_AWREADY; // @[src/main/scala/board/z710/z710/Top.scala 51:26] + wire [31:0] rom_loader_io_channels_write_address_channel_AWADDR; // @[src/main/scala/board/z710/z710/Top.scala 51:26] + wire rom_loader_io_channels_write_data_channel_WVALID; // @[src/main/scala/board/z710/z710/Top.scala 51:26] + wire rom_loader_io_channels_write_data_channel_WREADY; // @[src/main/scala/board/z710/z710/Top.scala 51:26] + wire [31:0] rom_loader_io_channels_write_data_channel_WDATA; // @[src/main/scala/board/z710/z710/Top.scala 51:26] + wire [3:0] rom_loader_io_channels_write_data_channel_WSTRB; // @[src/main/scala/board/z710/z710/Top.scala 51:26] + wire rom_loader_io_channels_write_response_channel_BVALID; // @[src/main/scala/board/z710/z710/Top.scala 51:26] + wire rom_loader_io_channels_write_response_channel_BREADY; // @[src/main/scala/board/z710/z710/Top.scala 51:26] + wire rom_loader_io_channels_read_address_channel_ARVALID; // @[src/main/scala/board/z710/z710/Top.scala 51:26] + wire rom_loader_io_channels_read_address_channel_ARREADY; // @[src/main/scala/board/z710/z710/Top.scala 51:26] + wire [31:0] rom_loader_io_channels_read_address_channel_ARADDR; // @[src/main/scala/board/z710/z710/Top.scala 51:26] + wire rom_loader_io_channels_read_data_channel_RVALID; // @[src/main/scala/board/z710/z710/Top.scala 51:26] + wire rom_loader_io_channels_read_data_channel_RREADY; // @[src/main/scala/board/z710/z710/Top.scala 51:26] + wire [31:0] rom_loader_io_channels_read_data_channel_RDATA; // @[src/main/scala/board/z710/z710/Top.scala 51:26] + wire [31:0] rom_loader_io_rom_address; // @[src/main/scala/board/z710/z710/Top.scala 51:26] + wire [31:0] rom_loader_io_rom_data; // @[src/main/scala/board/z710/z710/Top.scala 51:26] + wire rom_loader_io_load_start; // @[src/main/scala/board/z710/z710/Top.scala 51:26] + wire rom_loader_io_load_finished; // @[src/main/scala/board/z710/z710/Top.scala 51:26] + reg [1:0] boot_state; // @[src/main/scala/board/z710/z710/Top.scala 37:27] + wire _GEN_1 = 2'h3 == boot_state ? 1'h0 : 1'h1; // @[src/main/scala/board/z710/z710/Top.scala 68:22 64:25 82:29] + wire _GEN_4 = 2'h1 == boot_state ? rom_loader_io_channels_write_address_channel_AWVALID : + bus_switch_io_slaves_0_write_address_channel_AWVALID; // @[src/main/scala/board/z710/z710/Top.scala 68:22 66:27 76:30] + wire _GEN_5 = 2'h1 == boot_state ? mem_io_channels_write_address_channel_AWREADY : + dummy_io_channels_write_address_channel_AWREADY; // @[src/main/scala/board/z710/z710/Top.scala 68:22 67:26 76:30] + wire [31:0] _GEN_6 = 2'h1 == boot_state ? rom_loader_io_channels_write_address_channel_AWADDR : + bus_switch_io_slaves_0_write_address_channel_AWADDR; // @[src/main/scala/board/z710/z710/Top.scala 68:22 66:27 76:30] + wire _GEN_8 = 2'h1 == boot_state ? rom_loader_io_channels_write_data_channel_WVALID : + bus_switch_io_slaves_0_write_data_channel_WVALID; // @[src/main/scala/board/z710/z710/Top.scala 68:22 66:27 76:30] + wire _GEN_9 = 2'h1 == boot_state ? mem_io_channels_write_data_channel_WREADY : + dummy_io_channels_write_data_channel_WREADY; // @[src/main/scala/board/z710/z710/Top.scala 68:22 67:26 76:30] + wire [31:0] _GEN_10 = 2'h1 == boot_state ? rom_loader_io_channels_write_data_channel_WDATA : + bus_switch_io_slaves_0_write_data_channel_WDATA; // @[src/main/scala/board/z710/z710/Top.scala 68:22 66:27 76:30] + wire [3:0] _GEN_11 = 2'h1 == boot_state ? rom_loader_io_channels_write_data_channel_WSTRB : + bus_switch_io_slaves_0_write_data_channel_WSTRB; // @[src/main/scala/board/z710/z710/Top.scala 68:22 66:27 76:30] + wire _GEN_12 = 2'h1 == boot_state ? mem_io_channels_write_response_channel_BVALID : + dummy_io_channels_write_response_channel_BVALID; // @[src/main/scala/board/z710/z710/Top.scala 68:22 67:26 76:30] + wire _GEN_13 = 2'h1 == boot_state ? rom_loader_io_channels_write_response_channel_BREADY : + bus_switch_io_slaves_0_write_response_channel_BREADY; // @[src/main/scala/board/z710/z710/Top.scala 68:22 66:27 76:30] + wire _GEN_15 = 2'h1 == boot_state ? rom_loader_io_channels_read_address_channel_ARVALID : + bus_switch_io_slaves_0_read_address_channel_ARVALID; // @[src/main/scala/board/z710/z710/Top.scala 68:22 66:27 76:30] + wire _GEN_16 = 2'h1 == boot_state ? mem_io_channels_read_address_channel_ARREADY : + dummy_io_channels_read_address_channel_ARREADY; // @[src/main/scala/board/z710/z710/Top.scala 68:22 67:26 76:30] + wire [31:0] _GEN_17 = 2'h1 == boot_state ? rom_loader_io_channels_read_address_channel_ARADDR : + bus_switch_io_slaves_0_read_address_channel_ARADDR; // @[src/main/scala/board/z710/z710/Top.scala 68:22 66:27 76:30] + wire _GEN_19 = 2'h1 == boot_state ? mem_io_channels_read_data_channel_RVALID : + dummy_io_channels_read_data_channel_RVALID; // @[src/main/scala/board/z710/z710/Top.scala 68:22 67:26 76:30] + wire _GEN_20 = 2'h1 == boot_state ? rom_loader_io_channels_read_data_channel_RREADY : + bus_switch_io_slaves_0_read_data_channel_RREADY; // @[src/main/scala/board/z710/z710/Top.scala 68:22 66:27 76:30] + wire [31:0] _GEN_21 = 2'h1 == boot_state ? mem_io_channels_read_data_channel_RDATA : + dummy_io_channels_read_data_channel_RDATA; // @[src/main/scala/board/z710/z710/Top.scala 68:22 67:26 76:30] + wire _GEN_25 = 2'h1 == boot_state ? 1'h0 : 2'h3 == boot_state; // @[src/main/scala/board/z710/z710/Top.scala 68:22 65:28] + wire [1:0] _cpu_io_interrupt_flag_T = {uart_io_signal_interrupt,timer_io_signal_interrupt}; // @[src/main/scala/board/z710/z710/Top.scala 90:31] + reg [31:0] led_count; // @[src/main/scala/board/z710/z710/Top.scala 99:26] + wire [31:0] _led_count_T_1 = led_count + 32'h1; // @[src/main/scala/board/z710/z710/Top.scala 103:28] + Uart uart ( // @[src/main/scala/board/z710/z710/Top.scala 39:20] + .clock(uart_clock), + .reset(uart_reset), + .io_channels_write_address_channel_AWVALID(uart_io_channels_write_address_channel_AWVALID), + .io_channels_write_address_channel_AWREADY(uart_io_channels_write_address_channel_AWREADY), + .io_channels_write_address_channel_AWADDR(uart_io_channels_write_address_channel_AWADDR), + .io_channels_write_data_channel_WVALID(uart_io_channels_write_data_channel_WVALID), + .io_channels_write_data_channel_WREADY(uart_io_channels_write_data_channel_WREADY), + .io_channels_write_data_channel_WDATA(uart_io_channels_write_data_channel_WDATA), + .io_channels_write_response_channel_BVALID(uart_io_channels_write_response_channel_BVALID), + .io_channels_write_response_channel_BREADY(uart_io_channels_write_response_channel_BREADY), + .io_channels_read_address_channel_ARVALID(uart_io_channels_read_address_channel_ARVALID), + .io_channels_read_address_channel_ARREADY(uart_io_channels_read_address_channel_ARREADY), + .io_channels_read_address_channel_ARADDR(uart_io_channels_read_address_channel_ARADDR), + .io_channels_read_data_channel_RVALID(uart_io_channels_read_data_channel_RVALID), + .io_channels_read_data_channel_RREADY(uart_io_channels_read_data_channel_RREADY), + .io_channels_read_data_channel_RDATA(uart_io_channels_read_data_channel_RDATA), + .io_rxd(uart_io_rxd), + .io_txd(uart_io_txd), + .io_signal_interrupt(uart_io_signal_interrupt) + ); + CPU_1 cpu ( // @[src/main/scala/board/z710/z710/Top.scala 43:19] + .clock(cpu_clock), + .reset(cpu_reset), + .io_axi4_channels_write_address_channel_AWVALID(cpu_io_axi4_channels_write_address_channel_AWVALID), + .io_axi4_channels_write_address_channel_AWREADY(cpu_io_axi4_channels_write_address_channel_AWREADY), + .io_axi4_channels_write_address_channel_AWADDR(cpu_io_axi4_channels_write_address_channel_AWADDR), + .io_axi4_channels_write_data_channel_WVALID(cpu_io_axi4_channels_write_data_channel_WVALID), + .io_axi4_channels_write_data_channel_WREADY(cpu_io_axi4_channels_write_data_channel_WREADY), + .io_axi4_channels_write_data_channel_WDATA(cpu_io_axi4_channels_write_data_channel_WDATA), + .io_axi4_channels_write_data_channel_WSTRB(cpu_io_axi4_channels_write_data_channel_WSTRB), + .io_axi4_channels_write_response_channel_BVALID(cpu_io_axi4_channels_write_response_channel_BVALID), + .io_axi4_channels_write_response_channel_BREADY(cpu_io_axi4_channels_write_response_channel_BREADY), + .io_axi4_channels_read_address_channel_ARVALID(cpu_io_axi4_channels_read_address_channel_ARVALID), + .io_axi4_channels_read_address_channel_ARREADY(cpu_io_axi4_channels_read_address_channel_ARREADY), + .io_axi4_channels_read_address_channel_ARADDR(cpu_io_axi4_channels_read_address_channel_ARADDR), + .io_axi4_channels_read_data_channel_RVALID(cpu_io_axi4_channels_read_data_channel_RVALID), + .io_axi4_channels_read_data_channel_RREADY(cpu_io_axi4_channels_read_data_channel_RREADY), + .io_axi4_channels_read_data_channel_RDATA(cpu_io_axi4_channels_read_data_channel_RDATA), + .io_bus_address(cpu_io_bus_address), + .io_interrupt_flag(cpu_io_interrupt_flag), + .io_stall_flag_bus(cpu_io_stall_flag_bus), + .io_instruction_valid(cpu_io_instruction_valid) + ); + Memory mem ( // @[src/main/scala/board/z710/z710/Top.scala 44:19] + .clock(mem_clock), + .reset(mem_reset), + .io_channels_write_address_channel_AWVALID(mem_io_channels_write_address_channel_AWVALID), + .io_channels_write_address_channel_AWREADY(mem_io_channels_write_address_channel_AWREADY), + .io_channels_write_address_channel_AWADDR(mem_io_channels_write_address_channel_AWADDR), + .io_channels_write_data_channel_WVALID(mem_io_channels_write_data_channel_WVALID), + .io_channels_write_data_channel_WREADY(mem_io_channels_write_data_channel_WREADY), + .io_channels_write_data_channel_WDATA(mem_io_channels_write_data_channel_WDATA), + .io_channels_write_data_channel_WSTRB(mem_io_channels_write_data_channel_WSTRB), + .io_channels_write_response_channel_BVALID(mem_io_channels_write_response_channel_BVALID), + .io_channels_write_response_channel_BREADY(mem_io_channels_write_response_channel_BREADY), + .io_channels_read_address_channel_ARVALID(mem_io_channels_read_address_channel_ARVALID), + .io_channels_read_address_channel_ARREADY(mem_io_channels_read_address_channel_ARREADY), + .io_channels_read_address_channel_ARADDR(mem_io_channels_read_address_channel_ARADDR), + .io_channels_read_data_channel_RVALID(mem_io_channels_read_data_channel_RVALID), + .io_channels_read_data_channel_RREADY(mem_io_channels_read_data_channel_RREADY), + .io_channels_read_data_channel_RDATA(mem_io_channels_read_data_channel_RDATA) + ); + Timer timer ( // @[src/main/scala/board/z710/z710/Top.scala 45:21] + .clock(timer_clock), + .reset(timer_reset), + .io_channels_write_address_channel_AWVALID(timer_io_channels_write_address_channel_AWVALID), + .io_channels_write_address_channel_AWREADY(timer_io_channels_write_address_channel_AWREADY), + .io_channels_write_address_channel_AWADDR(timer_io_channels_write_address_channel_AWADDR), + .io_channels_write_data_channel_WVALID(timer_io_channels_write_data_channel_WVALID), + .io_channels_write_data_channel_WREADY(timer_io_channels_write_data_channel_WREADY), + .io_channels_write_data_channel_WDATA(timer_io_channels_write_data_channel_WDATA), + .io_channels_write_response_channel_BVALID(timer_io_channels_write_response_channel_BVALID), + .io_channels_write_response_channel_BREADY(timer_io_channels_write_response_channel_BREADY), + .io_channels_read_address_channel_ARVALID(timer_io_channels_read_address_channel_ARVALID), + .io_channels_read_address_channel_ARREADY(timer_io_channels_read_address_channel_ARREADY), + .io_channels_read_address_channel_ARADDR(timer_io_channels_read_address_channel_ARADDR), + .io_channels_read_data_channel_RVALID(timer_io_channels_read_data_channel_RVALID), + .io_channels_read_data_channel_RREADY(timer_io_channels_read_data_channel_RREADY), + .io_channels_read_data_channel_RDATA(timer_io_channels_read_data_channel_RDATA), + .io_signal_interrupt(timer_io_signal_interrupt) + ); + DummySlave dummy ( // @[src/main/scala/board/z710/z710/Top.scala 46:21] + .clock(dummy_clock), + .reset(dummy_reset), + .io_channels_write_address_channel_AWVALID(dummy_io_channels_write_address_channel_AWVALID), + .io_channels_write_address_channel_AWREADY(dummy_io_channels_write_address_channel_AWREADY), + .io_channels_write_address_channel_AWADDR(dummy_io_channels_write_address_channel_AWADDR), + .io_channels_write_data_channel_WVALID(dummy_io_channels_write_data_channel_WVALID), + .io_channels_write_data_channel_WREADY(dummy_io_channels_write_data_channel_WREADY), + .io_channels_write_data_channel_WDATA(dummy_io_channels_write_data_channel_WDATA), + .io_channels_write_data_channel_WSTRB(dummy_io_channels_write_data_channel_WSTRB), + .io_channels_write_response_channel_BVALID(dummy_io_channels_write_response_channel_BVALID), + .io_channels_write_response_channel_BREADY(dummy_io_channels_write_response_channel_BREADY), + .io_channels_read_address_channel_ARVALID(dummy_io_channels_read_address_channel_ARVALID), + .io_channels_read_address_channel_ARREADY(dummy_io_channels_read_address_channel_ARREADY), + .io_channels_read_address_channel_ARADDR(dummy_io_channels_read_address_channel_ARADDR), + .io_channels_read_data_channel_RVALID(dummy_io_channels_read_data_channel_RVALID), + .io_channels_read_data_channel_RREADY(dummy_io_channels_read_data_channel_RREADY), + .io_channels_read_data_channel_RDATA(dummy_io_channels_read_data_channel_RDATA) + ); + BusSwitch bus_switch ( // @[src/main/scala/board/z710/z710/Top.scala 48:26] + .clock(bus_switch_clock), + .reset(bus_switch_reset), + .io_address(bus_switch_io_address), + .io_slaves_0_write_address_channel_AWVALID(bus_switch_io_slaves_0_write_address_channel_AWVALID), + .io_slaves_0_write_address_channel_AWREADY(bus_switch_io_slaves_0_write_address_channel_AWREADY), + .io_slaves_0_write_address_channel_AWADDR(bus_switch_io_slaves_0_write_address_channel_AWADDR), + .io_slaves_0_write_data_channel_WVALID(bus_switch_io_slaves_0_write_data_channel_WVALID), + .io_slaves_0_write_data_channel_WREADY(bus_switch_io_slaves_0_write_data_channel_WREADY), + .io_slaves_0_write_data_channel_WDATA(bus_switch_io_slaves_0_write_data_channel_WDATA), + .io_slaves_0_write_data_channel_WSTRB(bus_switch_io_slaves_0_write_data_channel_WSTRB), + .io_slaves_0_write_response_channel_BVALID(bus_switch_io_slaves_0_write_response_channel_BVALID), + .io_slaves_0_write_response_channel_BREADY(bus_switch_io_slaves_0_write_response_channel_BREADY), + .io_slaves_0_read_address_channel_ARVALID(bus_switch_io_slaves_0_read_address_channel_ARVALID), + .io_slaves_0_read_address_channel_ARREADY(bus_switch_io_slaves_0_read_address_channel_ARREADY), + .io_slaves_0_read_address_channel_ARADDR(bus_switch_io_slaves_0_read_address_channel_ARADDR), + .io_slaves_0_read_data_channel_RVALID(bus_switch_io_slaves_0_read_data_channel_RVALID), + .io_slaves_0_read_data_channel_RREADY(bus_switch_io_slaves_0_read_data_channel_RREADY), + .io_slaves_0_read_data_channel_RDATA(bus_switch_io_slaves_0_read_data_channel_RDATA), + .io_slaves_1_write_address_channel_AWREADY(bus_switch_io_slaves_1_write_address_channel_AWREADY), + .io_slaves_1_write_data_channel_WREADY(bus_switch_io_slaves_1_write_data_channel_WREADY), + .io_slaves_1_write_response_channel_BVALID(bus_switch_io_slaves_1_write_response_channel_BVALID), + .io_slaves_1_read_address_channel_ARREADY(bus_switch_io_slaves_1_read_address_channel_ARREADY), + .io_slaves_1_read_data_channel_RVALID(bus_switch_io_slaves_1_read_data_channel_RVALID), + .io_slaves_1_read_data_channel_RDATA(bus_switch_io_slaves_1_read_data_channel_RDATA), + .io_slaves_2_write_address_channel_AWVALID(bus_switch_io_slaves_2_write_address_channel_AWVALID), + .io_slaves_2_write_address_channel_AWREADY(bus_switch_io_slaves_2_write_address_channel_AWREADY), + .io_slaves_2_write_address_channel_AWADDR(bus_switch_io_slaves_2_write_address_channel_AWADDR), + .io_slaves_2_write_data_channel_WVALID(bus_switch_io_slaves_2_write_data_channel_WVALID), + .io_slaves_2_write_data_channel_WREADY(bus_switch_io_slaves_2_write_data_channel_WREADY), + .io_slaves_2_write_data_channel_WDATA(bus_switch_io_slaves_2_write_data_channel_WDATA), + .io_slaves_2_write_response_channel_BVALID(bus_switch_io_slaves_2_write_response_channel_BVALID), + .io_slaves_2_write_response_channel_BREADY(bus_switch_io_slaves_2_write_response_channel_BREADY), + .io_slaves_2_read_address_channel_ARVALID(bus_switch_io_slaves_2_read_address_channel_ARVALID), + .io_slaves_2_read_address_channel_ARREADY(bus_switch_io_slaves_2_read_address_channel_ARREADY), + .io_slaves_2_read_address_channel_ARADDR(bus_switch_io_slaves_2_read_address_channel_ARADDR), + .io_slaves_2_read_data_channel_RVALID(bus_switch_io_slaves_2_read_data_channel_RVALID), + .io_slaves_2_read_data_channel_RREADY(bus_switch_io_slaves_2_read_data_channel_RREADY), + .io_slaves_2_read_data_channel_RDATA(bus_switch_io_slaves_2_read_data_channel_RDATA), + .io_slaves_3_write_address_channel_AWREADY(bus_switch_io_slaves_3_write_address_channel_AWREADY), + .io_slaves_3_write_data_channel_WREADY(bus_switch_io_slaves_3_write_data_channel_WREADY), + .io_slaves_3_write_response_channel_BVALID(bus_switch_io_slaves_3_write_response_channel_BVALID), + .io_slaves_3_read_address_channel_ARREADY(bus_switch_io_slaves_3_read_address_channel_ARREADY), + .io_slaves_3_read_data_channel_RVALID(bus_switch_io_slaves_3_read_data_channel_RVALID), + .io_slaves_3_read_data_channel_RDATA(bus_switch_io_slaves_3_read_data_channel_RDATA), + .io_slaves_4_write_address_channel_AWVALID(bus_switch_io_slaves_4_write_address_channel_AWVALID), + .io_slaves_4_write_address_channel_AWREADY(bus_switch_io_slaves_4_write_address_channel_AWREADY), + .io_slaves_4_write_address_channel_AWADDR(bus_switch_io_slaves_4_write_address_channel_AWADDR), + .io_slaves_4_write_data_channel_WVALID(bus_switch_io_slaves_4_write_data_channel_WVALID), + .io_slaves_4_write_data_channel_WREADY(bus_switch_io_slaves_4_write_data_channel_WREADY), + .io_slaves_4_write_data_channel_WDATA(bus_switch_io_slaves_4_write_data_channel_WDATA), + .io_slaves_4_write_response_channel_BVALID(bus_switch_io_slaves_4_write_response_channel_BVALID), + .io_slaves_4_write_response_channel_BREADY(bus_switch_io_slaves_4_write_response_channel_BREADY), + .io_slaves_4_read_address_channel_ARVALID(bus_switch_io_slaves_4_read_address_channel_ARVALID), + .io_slaves_4_read_address_channel_ARREADY(bus_switch_io_slaves_4_read_address_channel_ARREADY), + .io_slaves_4_read_address_channel_ARADDR(bus_switch_io_slaves_4_read_address_channel_ARADDR), + .io_slaves_4_read_data_channel_RVALID(bus_switch_io_slaves_4_read_data_channel_RVALID), + .io_slaves_4_read_data_channel_RREADY(bus_switch_io_slaves_4_read_data_channel_RREADY), + .io_slaves_4_read_data_channel_RDATA(bus_switch_io_slaves_4_read_data_channel_RDATA), + .io_slaves_5_write_address_channel_AWREADY(bus_switch_io_slaves_5_write_address_channel_AWREADY), + .io_slaves_5_write_data_channel_WREADY(bus_switch_io_slaves_5_write_data_channel_WREADY), + .io_slaves_5_write_response_channel_BVALID(bus_switch_io_slaves_5_write_response_channel_BVALID), + .io_slaves_5_read_address_channel_ARREADY(bus_switch_io_slaves_5_read_address_channel_ARREADY), + .io_slaves_5_read_data_channel_RVALID(bus_switch_io_slaves_5_read_data_channel_RVALID), + .io_slaves_5_read_data_channel_RDATA(bus_switch_io_slaves_5_read_data_channel_RDATA), + .io_slaves_6_write_address_channel_AWREADY(bus_switch_io_slaves_6_write_address_channel_AWREADY), + .io_slaves_6_write_data_channel_WREADY(bus_switch_io_slaves_6_write_data_channel_WREADY), + .io_slaves_6_write_response_channel_BVALID(bus_switch_io_slaves_6_write_response_channel_BVALID), + .io_slaves_6_read_address_channel_ARREADY(bus_switch_io_slaves_6_read_address_channel_ARREADY), + .io_slaves_6_read_data_channel_RVALID(bus_switch_io_slaves_6_read_data_channel_RVALID), + .io_slaves_6_read_data_channel_RDATA(bus_switch_io_slaves_6_read_data_channel_RDATA), + .io_slaves_7_write_address_channel_AWREADY(bus_switch_io_slaves_7_write_address_channel_AWREADY), + .io_slaves_7_write_data_channel_WREADY(bus_switch_io_slaves_7_write_data_channel_WREADY), + .io_slaves_7_write_response_channel_BVALID(bus_switch_io_slaves_7_write_response_channel_BVALID), + .io_slaves_7_read_address_channel_ARREADY(bus_switch_io_slaves_7_read_address_channel_ARREADY), + .io_slaves_7_read_data_channel_RVALID(bus_switch_io_slaves_7_read_data_channel_RVALID), + .io_slaves_7_read_data_channel_RDATA(bus_switch_io_slaves_7_read_data_channel_RDATA), + .io_master_write_address_channel_AWVALID(bus_switch_io_master_write_address_channel_AWVALID), + .io_master_write_address_channel_AWREADY(bus_switch_io_master_write_address_channel_AWREADY), + .io_master_write_address_channel_AWADDR(bus_switch_io_master_write_address_channel_AWADDR), + .io_master_write_data_channel_WVALID(bus_switch_io_master_write_data_channel_WVALID), + .io_master_write_data_channel_WREADY(bus_switch_io_master_write_data_channel_WREADY), + .io_master_write_data_channel_WDATA(bus_switch_io_master_write_data_channel_WDATA), + .io_master_write_data_channel_WSTRB(bus_switch_io_master_write_data_channel_WSTRB), + .io_master_write_response_channel_BVALID(bus_switch_io_master_write_response_channel_BVALID), + .io_master_write_response_channel_BREADY(bus_switch_io_master_write_response_channel_BREADY), + .io_master_read_address_channel_ARVALID(bus_switch_io_master_read_address_channel_ARVALID), + .io_master_read_address_channel_ARREADY(bus_switch_io_master_read_address_channel_ARREADY), + .io_master_read_address_channel_ARADDR(bus_switch_io_master_read_address_channel_ARADDR), + .io_master_read_data_channel_RVALID(bus_switch_io_master_read_data_channel_RVALID), + .io_master_read_data_channel_RREADY(bus_switch_io_master_read_data_channel_RREADY), + .io_master_read_data_channel_RDATA(bus_switch_io_master_read_data_channel_RDATA) + ); + InstructionROM instruction_rom ( // @[src/main/scala/board/z710/z710/Top.scala 50:31] + .clock(instruction_rom_clock), + .io_address(instruction_rom_io_address), + .io_data(instruction_rom_io_data) + ); + ROMLoader rom_loader ( // @[src/main/scala/board/z710/z710/Top.scala 51:26] + .clock(rom_loader_clock), + .reset(rom_loader_reset), + .io_channels_write_address_channel_AWVALID(rom_loader_io_channels_write_address_channel_AWVALID), + .io_channels_write_address_channel_AWREADY(rom_loader_io_channels_write_address_channel_AWREADY), + .io_channels_write_address_channel_AWADDR(rom_loader_io_channels_write_address_channel_AWADDR), + .io_channels_write_data_channel_WVALID(rom_loader_io_channels_write_data_channel_WVALID), + .io_channels_write_data_channel_WREADY(rom_loader_io_channels_write_data_channel_WREADY), + .io_channels_write_data_channel_WDATA(rom_loader_io_channels_write_data_channel_WDATA), + .io_channels_write_data_channel_WSTRB(rom_loader_io_channels_write_data_channel_WSTRB), + .io_channels_write_response_channel_BVALID(rom_loader_io_channels_write_response_channel_BVALID), + .io_channels_write_response_channel_BREADY(rom_loader_io_channels_write_response_channel_BREADY), + .io_channels_read_address_channel_ARVALID(rom_loader_io_channels_read_address_channel_ARVALID), + .io_channels_read_address_channel_ARREADY(rom_loader_io_channels_read_address_channel_ARREADY), + .io_channels_read_address_channel_ARADDR(rom_loader_io_channels_read_address_channel_ARADDR), + .io_channels_read_data_channel_RVALID(rom_loader_io_channels_read_data_channel_RVALID), + .io_channels_read_data_channel_RREADY(rom_loader_io_channels_read_data_channel_RREADY), + .io_channels_read_data_channel_RDATA(rom_loader_io_channels_read_data_channel_RDATA), + .io_rom_address(rom_loader_io_rom_address), + .io_rom_data(rom_loader_io_rom_data), + .io_load_start(rom_loader_io_load_start), + .io_load_finished(rom_loader_io_load_finished) + ); + assign io_led = led_count >= 32'h2faf080; // @[src/main/scala/board/z710/z710/Top.scala 106:24] + assign io_tx = uart_io_txd; // @[src/main/scala/board/z710/z710/Top.scala 40:9] + assign uart_clock = clock; + assign uart_reset = reset; + assign uart_io_channels_write_address_channel_AWVALID = bus_switch_io_slaves_2_write_address_channel_AWVALID; // @[src/main/scala/board/z710/z710/Top.scala 87:27] + assign uart_io_channels_write_address_channel_AWADDR = bus_switch_io_slaves_2_write_address_channel_AWADDR[7:0]; // @[src/main/scala/board/z710/z710/Top.scala 87:27] + assign uart_io_channels_write_data_channel_WVALID = bus_switch_io_slaves_2_write_data_channel_WVALID; // @[src/main/scala/board/z710/z710/Top.scala 87:27] + assign uart_io_channels_write_data_channel_WDATA = bus_switch_io_slaves_2_write_data_channel_WDATA; // @[src/main/scala/board/z710/z710/Top.scala 87:27] + assign uart_io_channels_write_response_channel_BREADY = bus_switch_io_slaves_2_write_response_channel_BREADY; // @[src/main/scala/board/z710/z710/Top.scala 87:27] + assign uart_io_channels_read_address_channel_ARVALID = bus_switch_io_slaves_2_read_address_channel_ARVALID; // @[src/main/scala/board/z710/z710/Top.scala 87:27] + assign uart_io_channels_read_address_channel_ARADDR = bus_switch_io_slaves_2_read_address_channel_ARADDR[7:0]; // @[src/main/scala/board/z710/z710/Top.scala 87:27] + assign uart_io_channels_read_data_channel_RREADY = bus_switch_io_slaves_2_read_data_channel_RREADY; // @[src/main/scala/board/z710/z710/Top.scala 87:27] + assign uart_io_rxd = io_rx; // @[src/main/scala/board/z710/z710/Top.scala 41:15] + assign cpu_clock = clock; + assign cpu_reset = reset; + assign cpu_io_axi4_channels_write_address_channel_AWREADY = bus_switch_io_master_write_address_channel_AWREADY; // @[src/main/scala/board/z710/z710/Top.scala 55:24] + assign cpu_io_axi4_channels_write_data_channel_WREADY = bus_switch_io_master_write_data_channel_WREADY; // @[src/main/scala/board/z710/z710/Top.scala 55:24] + assign cpu_io_axi4_channels_write_response_channel_BVALID = bus_switch_io_master_write_response_channel_BVALID; // @[src/main/scala/board/z710/z710/Top.scala 55:24] + assign cpu_io_axi4_channels_read_address_channel_ARREADY = bus_switch_io_master_read_address_channel_ARREADY; // @[src/main/scala/board/z710/z710/Top.scala 55:24] + assign cpu_io_axi4_channels_read_data_channel_RVALID = bus_switch_io_master_read_data_channel_RVALID; // @[src/main/scala/board/z710/z710/Top.scala 55:24] + assign cpu_io_axi4_channels_read_data_channel_RDATA = bus_switch_io_master_read_data_channel_RDATA; // @[src/main/scala/board/z710/z710/Top.scala 55:24] + assign cpu_io_interrupt_flag = {{30'd0}, _cpu_io_interrupt_flag_T}; // @[src/main/scala/board/z710/z710/Top.scala 90:25] + assign cpu_io_stall_flag_bus = 2'h0 == boot_state | (2'h1 == boot_state | _GEN_1); // @[src/main/scala/board/z710/z710/Top.scala 68:22 64:25] + assign cpu_io_instruction_valid = 2'h0 == boot_state ? 1'h0 : _GEN_25; // @[src/main/scala/board/z710/z710/Top.scala 68:22 65:28] + assign mem_clock = clock; + assign mem_reset = reset; + assign mem_io_channels_write_address_channel_AWVALID = 2'h0 == boot_state ? + rom_loader_io_channels_write_address_channel_AWVALID : _GEN_4; // @[src/main/scala/board/z710/z710/Top.scala 68:22 72:30] + assign mem_io_channels_write_address_channel_AWADDR = 2'h0 == boot_state ? + rom_loader_io_channels_write_address_channel_AWADDR : _GEN_6; // @[src/main/scala/board/z710/z710/Top.scala 68:22 72:30] + assign mem_io_channels_write_data_channel_WVALID = 2'h0 == boot_state ? + rom_loader_io_channels_write_data_channel_WVALID : _GEN_8; // @[src/main/scala/board/z710/z710/Top.scala 68:22 72:30] + assign mem_io_channels_write_data_channel_WDATA = 2'h0 == boot_state ? rom_loader_io_channels_write_data_channel_WDATA + : _GEN_10; // @[src/main/scala/board/z710/z710/Top.scala 68:22 72:30] + assign mem_io_channels_write_data_channel_WSTRB = 2'h0 == boot_state ? rom_loader_io_channels_write_data_channel_WSTRB + : _GEN_11; // @[src/main/scala/board/z710/z710/Top.scala 68:22 72:30] + assign mem_io_channels_write_response_channel_BREADY = 2'h0 == boot_state ? + rom_loader_io_channels_write_response_channel_BREADY : _GEN_13; // @[src/main/scala/board/z710/z710/Top.scala 68:22 72:30] + assign mem_io_channels_read_address_channel_ARVALID = 2'h0 == boot_state ? + rom_loader_io_channels_read_address_channel_ARVALID : _GEN_15; // @[src/main/scala/board/z710/z710/Top.scala 68:22 72:30] + assign mem_io_channels_read_address_channel_ARADDR = 2'h0 == boot_state ? + rom_loader_io_channels_read_address_channel_ARADDR : _GEN_17; // @[src/main/scala/board/z710/z710/Top.scala 68:22 72:30] + assign mem_io_channels_read_data_channel_RREADY = 2'h0 == boot_state ? rom_loader_io_channels_read_data_channel_RREADY + : _GEN_20; // @[src/main/scala/board/z710/z710/Top.scala 68:22 72:30] + assign timer_clock = clock; + assign timer_reset = reset; + assign timer_io_channels_write_address_channel_AWVALID = bus_switch_io_slaves_4_write_address_channel_AWVALID; // @[src/main/scala/board/z710/z710/Top.scala 88:27] + assign timer_io_channels_write_address_channel_AWADDR = bus_switch_io_slaves_4_write_address_channel_AWADDR[7:0]; // @[src/main/scala/board/z710/z710/Top.scala 88:27] + assign timer_io_channels_write_data_channel_WVALID = bus_switch_io_slaves_4_write_data_channel_WVALID; // @[src/main/scala/board/z710/z710/Top.scala 88:27] + assign timer_io_channels_write_data_channel_WDATA = bus_switch_io_slaves_4_write_data_channel_WDATA; // @[src/main/scala/board/z710/z710/Top.scala 88:27] + assign timer_io_channels_write_response_channel_BREADY = bus_switch_io_slaves_4_write_response_channel_BREADY; // @[src/main/scala/board/z710/z710/Top.scala 88:27] + assign timer_io_channels_read_address_channel_ARVALID = bus_switch_io_slaves_4_read_address_channel_ARVALID; // @[src/main/scala/board/z710/z710/Top.scala 88:27] + assign timer_io_channels_read_address_channel_ARADDR = bus_switch_io_slaves_4_read_address_channel_ARADDR[7:0]; // @[src/main/scala/board/z710/z710/Top.scala 88:27] + assign timer_io_channels_read_data_channel_RREADY = bus_switch_io_slaves_4_read_data_channel_RREADY; // @[src/main/scala/board/z710/z710/Top.scala 88:27] + assign dummy_clock = clock; + assign dummy_reset = reset; + assign dummy_io_channels_write_address_channel_AWVALID = rom_loader_io_channels_write_address_channel_AWVALID; // @[src/main/scala/board/z710/z710/Top.scala 67:26] + assign dummy_io_channels_write_address_channel_AWADDR = rom_loader_io_channels_write_address_channel_AWADDR[3:0]; // @[src/main/scala/board/z710/z710/Top.scala 67:26] + assign dummy_io_channels_write_data_channel_WVALID = rom_loader_io_channels_write_data_channel_WVALID; // @[src/main/scala/board/z710/z710/Top.scala 67:26] + assign dummy_io_channels_write_data_channel_WDATA = rom_loader_io_channels_write_data_channel_WDATA; // @[src/main/scala/board/z710/z710/Top.scala 67:26] + assign dummy_io_channels_write_data_channel_WSTRB = rom_loader_io_channels_write_data_channel_WSTRB; // @[src/main/scala/board/z710/z710/Top.scala 67:26] + assign dummy_io_channels_write_response_channel_BREADY = rom_loader_io_channels_write_response_channel_BREADY; // @[src/main/scala/board/z710/z710/Top.scala 67:26] + assign dummy_io_channels_read_address_channel_ARVALID = rom_loader_io_channels_read_address_channel_ARVALID; // @[src/main/scala/board/z710/z710/Top.scala 67:26] + assign dummy_io_channels_read_address_channel_ARADDR = rom_loader_io_channels_read_address_channel_ARADDR[3:0]; // @[src/main/scala/board/z710/z710/Top.scala 67:26] + assign dummy_io_channels_read_data_channel_RREADY = rom_loader_io_channels_read_data_channel_RREADY; // @[src/main/scala/board/z710/z710/Top.scala 67:26] + assign bus_switch_clock = clock; + assign bus_switch_reset = reset; + assign bus_switch_io_address = cpu_io_bus_address; // @[src/main/scala/board/z710/z710/Top.scala 56:25] + assign bus_switch_io_slaves_0_write_address_channel_AWREADY = mem_io_channels_write_address_channel_AWREADY; // @[src/main/scala/board/z710/z710/Top.scala 66:27] + assign bus_switch_io_slaves_0_write_data_channel_WREADY = mem_io_channels_write_data_channel_WREADY; // @[src/main/scala/board/z710/z710/Top.scala 66:27] + assign bus_switch_io_slaves_0_write_response_channel_BVALID = mem_io_channels_write_response_channel_BVALID; // @[src/main/scala/board/z710/z710/Top.scala 66:27] + assign bus_switch_io_slaves_0_read_address_channel_ARREADY = mem_io_channels_read_address_channel_ARREADY; // @[src/main/scala/board/z710/z710/Top.scala 66:27] + assign bus_switch_io_slaves_0_read_data_channel_RVALID = mem_io_channels_read_data_channel_RVALID; // @[src/main/scala/board/z710/z710/Top.scala 66:27] + assign bus_switch_io_slaves_0_read_data_channel_RDATA = mem_io_channels_read_data_channel_RDATA; // @[src/main/scala/board/z710/z710/Top.scala 66:27] + assign bus_switch_io_slaves_1_write_address_channel_AWREADY = dummy_io_channels_write_address_channel_AWREADY; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_1_write_data_channel_WREADY = dummy_io_channels_write_data_channel_WREADY; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_1_write_response_channel_BVALID = dummy_io_channels_write_response_channel_BVALID; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_1_read_address_channel_ARREADY = dummy_io_channels_read_address_channel_ARREADY; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_1_read_data_channel_RVALID = dummy_io_channels_read_data_channel_RVALID; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_1_read_data_channel_RDATA = dummy_io_channels_read_data_channel_RDATA; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_2_write_address_channel_AWREADY = uart_io_channels_write_address_channel_AWREADY; // @[src/main/scala/board/z710/z710/Top.scala 87:27] + assign bus_switch_io_slaves_2_write_data_channel_WREADY = uart_io_channels_write_data_channel_WREADY; // @[src/main/scala/board/z710/z710/Top.scala 87:27] + assign bus_switch_io_slaves_2_write_response_channel_BVALID = uart_io_channels_write_response_channel_BVALID; // @[src/main/scala/board/z710/z710/Top.scala 87:27] + assign bus_switch_io_slaves_2_read_address_channel_ARREADY = uart_io_channels_read_address_channel_ARREADY; // @[src/main/scala/board/z710/z710/Top.scala 87:27] + assign bus_switch_io_slaves_2_read_data_channel_RVALID = uart_io_channels_read_data_channel_RVALID; // @[src/main/scala/board/z710/z710/Top.scala 87:27] + assign bus_switch_io_slaves_2_read_data_channel_RDATA = uart_io_channels_read_data_channel_RDATA; // @[src/main/scala/board/z710/z710/Top.scala 87:27] + assign bus_switch_io_slaves_3_write_address_channel_AWREADY = dummy_io_channels_write_address_channel_AWREADY; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_3_write_data_channel_WREADY = dummy_io_channels_write_data_channel_WREADY; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_3_write_response_channel_BVALID = dummy_io_channels_write_response_channel_BVALID; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_3_read_address_channel_ARREADY = dummy_io_channels_read_address_channel_ARREADY; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_3_read_data_channel_RVALID = dummy_io_channels_read_data_channel_RVALID; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_3_read_data_channel_RDATA = dummy_io_channels_read_data_channel_RDATA; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_4_write_address_channel_AWREADY = timer_io_channels_write_address_channel_AWREADY; // @[src/main/scala/board/z710/z710/Top.scala 88:27] + assign bus_switch_io_slaves_4_write_data_channel_WREADY = timer_io_channels_write_data_channel_WREADY; // @[src/main/scala/board/z710/z710/Top.scala 88:27] + assign bus_switch_io_slaves_4_write_response_channel_BVALID = timer_io_channels_write_response_channel_BVALID; // @[src/main/scala/board/z710/z710/Top.scala 88:27] + assign bus_switch_io_slaves_4_read_address_channel_ARREADY = timer_io_channels_read_address_channel_ARREADY; // @[src/main/scala/board/z710/z710/Top.scala 88:27] + assign bus_switch_io_slaves_4_read_data_channel_RVALID = timer_io_channels_read_data_channel_RVALID; // @[src/main/scala/board/z710/z710/Top.scala 88:27] + assign bus_switch_io_slaves_4_read_data_channel_RDATA = timer_io_channels_read_data_channel_RDATA; // @[src/main/scala/board/z710/z710/Top.scala 88:27] + assign bus_switch_io_slaves_5_write_address_channel_AWREADY = dummy_io_channels_write_address_channel_AWREADY; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_5_write_data_channel_WREADY = dummy_io_channels_write_data_channel_WREADY; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_5_write_response_channel_BVALID = dummy_io_channels_write_response_channel_BVALID; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_5_read_address_channel_ARREADY = dummy_io_channels_read_address_channel_ARREADY; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_5_read_data_channel_RVALID = dummy_io_channels_read_data_channel_RVALID; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_5_read_data_channel_RDATA = dummy_io_channels_read_data_channel_RDATA; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_6_write_address_channel_AWREADY = dummy_io_channels_write_address_channel_AWREADY; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_6_write_data_channel_WREADY = dummy_io_channels_write_data_channel_WREADY; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_6_write_response_channel_BVALID = dummy_io_channels_write_response_channel_BVALID; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_6_read_address_channel_ARREADY = dummy_io_channels_read_address_channel_ARREADY; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_6_read_data_channel_RVALID = dummy_io_channels_read_data_channel_RVALID; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_6_read_data_channel_RDATA = dummy_io_channels_read_data_channel_RDATA; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_7_write_address_channel_AWREADY = dummy_io_channels_write_address_channel_AWREADY; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_7_write_data_channel_WREADY = dummy_io_channels_write_data_channel_WREADY; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_7_write_response_channel_BVALID = dummy_io_channels_write_response_channel_BVALID; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_7_read_address_channel_ARREADY = dummy_io_channels_read_address_channel_ARREADY; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_7_read_data_channel_RVALID = dummy_io_channels_read_data_channel_RVALID; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_slaves_7_read_data_channel_RDATA = dummy_io_channels_read_data_channel_RDATA; // @[src/main/scala/board/z710/z710/Top.scala 58:29] + assign bus_switch_io_master_write_address_channel_AWVALID = cpu_io_axi4_channels_write_address_channel_AWVALID; // @[src/main/scala/board/z710/z710/Top.scala 55:24] + assign bus_switch_io_master_write_address_channel_AWADDR = cpu_io_axi4_channels_write_address_channel_AWADDR; // @[src/main/scala/board/z710/z710/Top.scala 55:24] + assign bus_switch_io_master_write_data_channel_WVALID = cpu_io_axi4_channels_write_data_channel_WVALID; // @[src/main/scala/board/z710/z710/Top.scala 55:24] + assign bus_switch_io_master_write_data_channel_WDATA = cpu_io_axi4_channels_write_data_channel_WDATA; // @[src/main/scala/board/z710/z710/Top.scala 55:24] + assign bus_switch_io_master_write_data_channel_WSTRB = cpu_io_axi4_channels_write_data_channel_WSTRB; // @[src/main/scala/board/z710/z710/Top.scala 55:24] + assign bus_switch_io_master_write_response_channel_BREADY = cpu_io_axi4_channels_write_response_channel_BREADY; // @[src/main/scala/board/z710/z710/Top.scala 55:24] + assign bus_switch_io_master_read_address_channel_ARVALID = cpu_io_axi4_channels_read_address_channel_ARVALID; // @[src/main/scala/board/z710/z710/Top.scala 55:24] + assign bus_switch_io_master_read_address_channel_ARADDR = cpu_io_axi4_channels_read_address_channel_ARADDR; // @[src/main/scala/board/z710/z710/Top.scala 55:24] + assign bus_switch_io_master_read_data_channel_RREADY = cpu_io_axi4_channels_read_data_channel_RREADY; // @[src/main/scala/board/z710/z710/Top.scala 55:24] + assign instruction_rom_clock = clock; + assign instruction_rom_io_address = rom_loader_io_rom_address; // @[src/main/scala/board/z710/z710/Top.scala 63:30] + assign rom_loader_clock = clock; + assign rom_loader_reset = reset; + assign rom_loader_io_channels_write_address_channel_AWREADY = 2'h0 == boot_state ? + mem_io_channels_write_address_channel_AWREADY : _GEN_5; // @[src/main/scala/board/z710/z710/Top.scala 68:22 72:30] + assign rom_loader_io_channels_write_data_channel_WREADY = 2'h0 == boot_state ? + mem_io_channels_write_data_channel_WREADY : _GEN_9; // @[src/main/scala/board/z710/z710/Top.scala 68:22 72:30] + assign rom_loader_io_channels_write_response_channel_BVALID = 2'h0 == boot_state ? + mem_io_channels_write_response_channel_BVALID : _GEN_12; // @[src/main/scala/board/z710/z710/Top.scala 68:22 72:30] + assign rom_loader_io_channels_read_address_channel_ARREADY = 2'h0 == boot_state ? + mem_io_channels_read_address_channel_ARREADY : _GEN_16; // @[src/main/scala/board/z710/z710/Top.scala 68:22 72:30] + assign rom_loader_io_channels_read_data_channel_RVALID = 2'h0 == boot_state ? mem_io_channels_read_data_channel_RVALID + : _GEN_19; // @[src/main/scala/board/z710/z710/Top.scala 68:22 72:30] + assign rom_loader_io_channels_read_data_channel_RDATA = 2'h0 == boot_state ? mem_io_channels_read_data_channel_RDATA + : _GEN_21; // @[src/main/scala/board/z710/z710/Top.scala 68:22 72:30] + assign rom_loader_io_rom_data = instruction_rom_io_data; // @[src/main/scala/board/z710/z710/Top.scala 62:26] + assign rom_loader_io_load_start = 2'h0 == boot_state; // @[src/main/scala/board/z710/z710/Top.scala 68:22] + always @(posedge clock) begin + if (reset) begin // @[src/main/scala/board/z710/z710/Top.scala 37:27] + boot_state <= 2'h0; // @[src/main/scala/board/z710/z710/Top.scala 37:27] + end else if (2'h0 == boot_state) begin // @[src/main/scala/board/z710/z710/Top.scala 68:22] + boot_state <= 2'h1; // @[src/main/scala/board/z710/z710/Top.scala 71:18] + end else if (2'h1 == boot_state) begin // @[src/main/scala/board/z710/z710/Top.scala 68:22] + if (rom_loader_io_load_finished) begin // @[src/main/scala/board/z710/z710/Top.scala 77:41] + boot_state <= 2'h3; // @[src/main/scala/board/z710/z710/Top.scala 78:20] + end + end + if (reset) begin // @[src/main/scala/board/z710/z710/Top.scala 99:26] + led_count <= 32'h0; // @[src/main/scala/board/z710/z710/Top.scala 99:26] + end else if (led_count >= 32'h5f5e100) begin // @[src/main/scala/board/z710/z710/Top.scala 100:34] + led_count <= 32'h0; // @[src/main/scala/board/z710/z710/Top.scala 101:15] + end else begin + led_count <= _led_count_T_1; // @[src/main/scala/board/z710/z710/Top.scala 103:15] + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + boot_state = _RAND_0[1:0]; + _RAND_1 = {1{`RANDOM}}; + led_count = _RAND_1[31:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule diff --git a/mini-yatcpu/verilog/z710/Top_reset.v b/mini-yatcpu/verilog/z710/Top_reset.v new file mode 100644 index 0000000..4349e47 --- /dev/null +++ b/mini-yatcpu/verilog/z710/Top_reset.v @@ -0,0 +1,32 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2023/12/01 16:32:40 +// Design Name: +// Module Name: Top_reset +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module Top_reset( + input reset + ); + initial begin + reset = 1; + #25 reset = 0; + end + + +endmodule diff --git a/mini-yatcpu/verilog/z710/clock_control.v b/mini-yatcpu/verilog/z710/clock_control.v new file mode 100644 index 0000000..f4e882d --- /dev/null +++ b/mini-yatcpu/verilog/z710/clock_control.v @@ -0,0 +1,29 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2023/11/29 15:52:55 +// Design Name: +// Module Name: clock_control +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module clock_control( + input clk_in, + input enable_clk, + output clk_out + ); + assign clk_out = clk_in & enable_clk; +endmodule diff --git a/mini-yatcpu/verilog/z710/design_1.bd b/mini-yatcpu/verilog/z710/design_1.bd new file mode 100644 index 0000000..39f979a --- /dev/null +++ b/mini-yatcpu/verilog/z710/design_1.bd @@ -0,0 +1,459 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0xD2682A7282870375", + "device": "xc7z010clg400-1", + "name": "design_1", + "rev_ctrl_bd_flag": "RevCtrlBdOff", + "synth_flow_mode": "Hierarchical", + "tool_version": "2020.1", + "validated": "true" + }, + "design_tree": { + "processing_system7_0": "", + "clock_control_0": "", + "xlconstant_0": "", + "Top_0": "" + }, + "interface_ports": { + "DDR": { + "mode": "Master", + "vlnv": "xilinx.com:interface:ddrx_rtl:1.0", + "parameters": { + "CAN_DEBUG": { + "value": "false", + "value_src": "default" + }, + "TIMEPERIOD_PS": { + "value": "1250", + "value_src": "default" + }, + "MEMORY_TYPE": { + "value": "COMPONENTS", + "value_src": "default" + }, + "DATA_WIDTH": { + "value": "8", + "value_src": "default" + }, + "CS_ENABLED": { + "value": "true", + "value_src": "default" + }, + "DATA_MASK_ENABLED": { + "value": "true", + "value_src": "default" + }, + "SLOT": { + "value": "Single", + "value_src": "default" + }, + "MEM_ADDR_MAP": { + "value": "ROW_COLUMN_BANK", + "value_src": "default" + }, + "BURST_LENGTH": { + "value": "8", + "value_src": "default" + }, + "AXI_ARBITRATION_SCHEME": { + "value": "TDM", + "value_src": "default" + }, + "CAS_LATENCY": { + "value": "11", + "value_src": "default" + }, + "CAS_WRITE_LATENCY": { + "value": "11", + "value_src": "default" + } + } + }, + "FIXED_IO": { + "mode": "Master", + "vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0", + "parameters": { + "CAN_DEBUG": { + "value": "false", + "value_src": "default" + } + } + } + }, + "ports": { + "io_clock": { + "type": "clk", + "direction": "I", + "parameters": { + "CLK_DOMAIN": { + "value": "design_1_clock", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.000", + "value_src": "default" + } + } + }, + "io_alive_led": { + "direction": "O" + }, + "io_reset": { + "direction": "I", + "parameters": { + "POLARITY": { + "value": "", + "value_src": "weak" + } + } + }, + "enable_clk": { + "type": "clk", + "direction": "I", + "parameters": { + "CLK_DOMAIN": { + "value": "design_1_enable_clk_0", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.000", + "value_src": "default" + } + } + } + }, + "components": { + "processing_system7_0": { + "vlnv": "xilinx.com:ip:processing_system7:5.5", + "xci_name": "design_1_processing_system7_0_0", + "parameters": { + "PCW_ACT_APU_PERIPHERAL_FREQMHZ": { + "value": "666.666687" + }, + "PCW_ACT_CAN_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_DCI_PERIPHERAL_FREQMHZ": { + "value": "10.158730" + }, + "PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_ENET1_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": { + "value": "50.000000" + }, + "PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_QSPI_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_SDIO_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_SMC_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_SPI_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_UART_PERIPHERAL_FREQMHZ": { + "value": "100.000000" + }, + "PCW_ACT_WDT_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_CLK0_FREQ": { + "value": "50000000" + }, + "PCW_CLK1_FREQ": { + "value": "10000000" + }, + "PCW_CLK2_FREQ": { + "value": "10000000" + }, + "PCW_CLK3_FREQ": { + "value": "10000000" + }, + "PCW_DDR_RAM_HIGHADDR": { + "value": "0x1FFFFFFF" + }, + "PCW_EN_EMIO_UART0": { + "value": "1" + }, + "PCW_EN_UART0": { + "value": "1" + }, + "PCW_EN_UART1": { + "value": "1" + }, + "PCW_FPGA_FCLK0_ENABLE": { + "value": "1" + }, + "PCW_MIO_48_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_48_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_48_SLEW": { + "value": "slow" + }, + "PCW_MIO_49_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_49_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_49_SLEW": { + "value": "slow" + }, + "PCW_MIO_TREE_PERIPHERALS": { + "value": "unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 1#UART 1#unassigned#unassigned#unassigned#unassigned" + }, + "PCW_MIO_TREE_SIGNALS": { + "value": "unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#tx#rx#unassigned#unassigned#unassigned#unassigned" + }, + "PCW_UART0_GRP_FULL_ENABLE": { + "value": "0" + }, + "PCW_UART0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_UART0_UART0_IO": { + "value": "EMIO" + }, + "PCW_UART1_GRP_FULL_ENABLE": { + "value": "0" + }, + "PCW_UART1_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_UART1_UART1_IO": { + "value": "MIO 48 .. 49" + }, + "PCW_UART_PERIPHERAL_FREQMHZ": { + "value": "100" + }, + "PCW_UART_PERIPHERAL_VALID": { + "value": "1" + }, + "PCW_UIPARAM_ACT_DDR_FREQ_MHZ": { + "value": "533.333374" + }, + "PCW_USE_M_AXI_GP0": { + "value": "0" + } + } + }, + "clock_control_0": { + "vlnv": "xilinx.com:module_ref:clock_control:1.0", + "xci_name": "design_1_clock_control_0_0", + "reference_info": { + "ref_type": "hdl", + "ref_name": "clock_control", + "boundary_crc": "0x0" + }, + "ports": { + "clk_in": { + "direction": "I", + "parameters": { + "CLK_DOMAIN": { + "value": "design_1_clock", + "value_src": "default_prop" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "user_prop" + }, + "PHASE": { + "value": "0.000", + "value_src": "default_prop" + } + } + }, + "enable_clk": { + "type": "clk", + "direction": "I", + "parameters": { + "CLK_DOMAIN": { + "value": "design_1_enable_clk_0", + "value_src": "default_prop" + } + } + }, + "clk_out": { + "direction": "O", + "parameters": { + "CLK_DOMAIN": { + "value": "", + "value_src": "weak" + }, + "FREQ_HZ": { + "value": "", + "value_src": "weak" + }, + "PHASE": { + "value": "", + "value_src": "weak" + } + } + } + } + }, + "xlconstant_0": { + "vlnv": "xilinx.com:ip:xlconstant:1.1", + "xci_name": "design_1_xlconstant_0_0" + }, + "Top_0": { + "vlnv": "xilinx.com:module_ref:Top:1.0", + "xci_name": "design_1_Top_0_0", + "reference_info": { + "ref_type": "hdl", + "ref_name": "Top", + "boundary_crc": "0x0" + }, + "ports": { + "clock": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_RESET": { + "value": "reset", + "value_src": "constant" + } + } + }, + "reset": { + "type": "rst", + "direction": "I" + }, + "io_led": { + "direction": "O" + }, + "io_tx": { + "direction": "O" + }, + "io_rx": { + "direction": "I" + } + } + } + }, + "interface_nets": { + "processing_system7_0_DDR": { + "interface_ports": [ + "DDR", + "processing_system7_0/DDR" + ] + }, + "processing_system7_0_FIXED_IO": { + "interface_ports": [ + "FIXED_IO", + "processing_system7_0/FIXED_IO" + ] + } + }, + "nets": { + "Top_0_io_tx": { + "ports": [ + "Top_0/io_tx", + "processing_system7_0/UART0_RX" + ] + }, + "Top_0_io_led": { + "ports": [ + "Top_0/io_led", + "io_alive_led" + ] + }, + "io_reset_1": { + "ports": [ + "io_reset", + "Top_0/reset" + ] + }, + "io_clock_1": { + "ports": [ + "io_clock", + "clock_control_0/clk_in" + ] + }, + "enable_clk_0_1": { + "ports": [ + "enable_clk", + "clock_control_0/enable_clk" + ] + }, + "clock_control_0_clk_out": { + "ports": [ + "clock_control_0/clk_out", + "Top_0/clock" + ] + }, + "xlconstant_0_dout": { + "ports": [ + "xlconstant_0/dout", + "Top_0/io_rx" + ] + } + } + } +} \ No newline at end of file diff --git a/mini-yatcpu/verilog/z710/design_1_wrapper.v b/mini-yatcpu/verilog/z710/design_1_wrapper.v new file mode 100644 index 0000000..e148ca7 --- /dev/null +++ b/mini-yatcpu/verilog/z710/design_1_wrapper.v @@ -0,0 +1,116 @@ +//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020 +//Date : Sun Dec 10 14:11:15 2023 +//Host : Tokisakix running 64-bit major release (build 9200) +//Command : generate_target design_1_wrapper.bd +//Design : design_1_wrapper +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module design_1_wrapper + (DDR_addr, + DDR_ba, + DDR_cas_n, + DDR_ck_n, + DDR_ck_p, + DDR_cke, + DDR_cs_n, + DDR_dm, + DDR_dq, + DDR_dqs_n, + DDR_dqs_p, + DDR_odt, + DDR_ras_n, + DDR_reset_n, + DDR_we_n, + FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp, + FIXED_IO_mio, + FIXED_IO_ps_clk, + FIXED_IO_ps_porb, + FIXED_IO_ps_srstb, + enable_clk, + io_alive_led, + io_clock, + io_reset); + inout [14:0]DDR_addr; + inout [2:0]DDR_ba; + inout DDR_cas_n; + inout DDR_ck_n; + inout DDR_ck_p; + inout DDR_cke; + inout DDR_cs_n; + inout [3:0]DDR_dm; + inout [31:0]DDR_dq; + inout [3:0]DDR_dqs_n; + inout [3:0]DDR_dqs_p; + inout DDR_odt; + inout DDR_ras_n; + inout DDR_reset_n; + inout DDR_we_n; + inout FIXED_IO_ddr_vrn; + inout FIXED_IO_ddr_vrp; + inout [53:0]FIXED_IO_mio; + inout FIXED_IO_ps_clk; + inout FIXED_IO_ps_porb; + inout FIXED_IO_ps_srstb; + input enable_clk; + output io_alive_led; + input io_clock; + input io_reset; + + wire [14:0]DDR_addr; + wire [2:0]DDR_ba; + wire DDR_cas_n; + wire DDR_ck_n; + wire DDR_ck_p; + wire DDR_cke; + wire DDR_cs_n; + wire [3:0]DDR_dm; + wire [31:0]DDR_dq; + wire [3:0]DDR_dqs_n; + wire [3:0]DDR_dqs_p; + wire DDR_odt; + wire DDR_ras_n; + wire DDR_reset_n; + wire DDR_we_n; + wire FIXED_IO_ddr_vrn; + wire FIXED_IO_ddr_vrp; + wire [53:0]FIXED_IO_mio; + wire FIXED_IO_ps_clk; + wire FIXED_IO_ps_porb; + wire FIXED_IO_ps_srstb; + wire enable_clk; + wire io_alive_led; + wire io_clock; + wire io_reset; + + design_1 design_1_i + (.DDR_addr(DDR_addr), + .DDR_ba(DDR_ba), + .DDR_cas_n(DDR_cas_n), + .DDR_ck_n(DDR_ck_n), + .DDR_ck_p(DDR_ck_p), + .DDR_cke(DDR_cke), + .DDR_cs_n(DDR_cs_n), + .DDR_dm(DDR_dm), + .DDR_dq(DDR_dq), + .DDR_dqs_n(DDR_dqs_n), + .DDR_dqs_p(DDR_dqs_p), + .DDR_odt(DDR_odt), + .DDR_ras_n(DDR_ras_n), + .DDR_reset_n(DDR_reset_n), + .DDR_we_n(DDR_we_n), + .FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn), + .FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp), + .FIXED_IO_mio(FIXED_IO_mio), + .FIXED_IO_ps_clk(FIXED_IO_ps_clk), + .FIXED_IO_ps_porb(FIXED_IO_ps_porb), + .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb), + .enable_clk(enable_clk), + .io_alive_led(io_alive_led), + .io_clock(io_clock), + .io_reset(io_reset)); +endmodule diff --git a/mini-yatcpu/verilog/z710/pass_through.v b/mini-yatcpu/verilog/z710/pass_through.v new file mode 100644 index 0000000..daf212e --- /dev/null +++ b/mini-yatcpu/verilog/z710/pass_through.v @@ -0,0 +1,28 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2023/11/29 16:38:00 +// Design Name: +// Module Name: pass_through +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module pass_through( + input in, + output out + ); + assign out = in; +endmodule diff --git a/mini-yatcpu/verilog/z710/test.v b/mini-yatcpu/verilog/z710/test.v new file mode 100644 index 0000000..b250a66 --- /dev/null +++ b/mini-yatcpu/verilog/z710/test.v @@ -0,0 +1,35 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2021/12/17 16:31:05 +// Design Name: +// Module Name: test +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module test(); +reg clock; +reg reset; +initial begin +clock = 0; +forever #1 clock = ~clock; +end +initial begin +reset = 1; +#2 reset = 0; +end +Top top(clock, reset); +endmodule \ No newline at end of file diff --git a/mini-yatcpu/verilog/z710/top_test.v b/mini-yatcpu/verilog/z710/top_test.v new file mode 100644 index 0000000..a2398e8 --- /dev/null +++ b/mini-yatcpu/verilog/z710/top_test.v @@ -0,0 +1,47 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2023/12/01 15:46:54 +// Design Name: +// Module Name: top_test +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module top_test( + + ); + + reg clock; + reg reset; + reg constant_zero = 1'b0; + + wire io_led, io_tx; + + localparam CLK_PERIOD = 20; + initial begin + clock = 1'b0; + forever #( CLK_PERIOD / 2 ) clock = ~clock; + end + + + initial begin + reset = 1; // need a down edge to init all components + #21 reset = 0; // NOTE!!: must happen together with clock down edge! + end + + Top mytop(clock, reset, io_led, io_tx, constant_zero); + +endmodule diff --git a/mini-yatcpu/verilog/z710/uart_control.v b/mini-yatcpu/verilog/z710/uart_control.v new file mode 100644 index 0000000..a73b6d2 --- /dev/null +++ b/mini-yatcpu/verilog/z710/uart_control.v @@ -0,0 +1,30 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2023/11/30 00:51:08 +// Design Name: +// Module Name: uart_control +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module uart_control( + input enable_uart, + input tx_in, + output tx_out + ); + assign tx_out = (enable_uart) ? tx_in : 1'h1; + +endmodule diff --git a/mini-yatcpu/vivado/basys3/basys3.xdc b/mini-yatcpu/vivado/basys3/basys3.xdc new file mode 100644 index 0000000..9864546 --- /dev/null +++ b/mini-yatcpu/vivado/basys3/basys3.xdc @@ -0,0 +1,307 @@ +# Copyright 2021 Howard Lau +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +## Clock signal +set_property PACKAGE_PIN W5 [get_ports clock] + set_property IOSTANDARD LVCMOS33 [get_ports clock] + create_clock -add -name sys_clk_pin -period 20.00 -waveform {0 5} [get_ports clock] + +## Switches +set_property PACKAGE_PIN V17 [get_ports {io_switch[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[0]}] +set_property PACKAGE_PIN V16 [get_ports {io_switch[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[1]}] +set_property PACKAGE_PIN W16 [get_ports {io_switch[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[2]}] +set_property PACKAGE_PIN W17 [get_ports {io_switch[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[3]}] +set_property PACKAGE_PIN W15 [get_ports {io_switch[4]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[4]}] +set_property PACKAGE_PIN V15 [get_ports {io_switch[5]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[5]}] +set_property PACKAGE_PIN W14 [get_ports {io_switch[6]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[6]}] +set_property PACKAGE_PIN W13 [get_ports {io_switch[7]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[7]}] +set_property PACKAGE_PIN V2 [get_ports {io_switch[8]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[8]}] +set_property PACKAGE_PIN T3 [get_ports {io_switch[9]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[9]}] +set_property PACKAGE_PIN T2 [get_ports {io_switch[10]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[10]}] +set_property PACKAGE_PIN R3 [get_ports {io_switch[11]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[11]}] +set_property PACKAGE_PIN W2 [get_ports {io_switch[12]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[12]}] +set_property PACKAGE_PIN U1 [get_ports {io_switch[13]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[13]}] +set_property PACKAGE_PIN T1 [get_ports {io_switch[14]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[14]}] +set_property PACKAGE_PIN R2 [get_ports {io_switch[15]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_switch[15]}] + + +## LEDs +set_property PACKAGE_PIN U16 [get_ports {io_led[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_led[0]}] +set_property PACKAGE_PIN E19 [get_ports {io_led[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_led[1]}] +set_property PACKAGE_PIN U19 [get_ports {io_led[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_led[2]}] +set_property PACKAGE_PIN V19 [get_ports {io_led[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_led[3]}] +set_property PACKAGE_PIN W18 [get_ports {io_led[4]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_led[4]}] +set_property PACKAGE_PIN U15 [get_ports {io_led[5]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_led[5]}] +set_property PACKAGE_PIN U14 [get_ports {io_led[6]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_led[6]}] +set_property PACKAGE_PIN V14 [get_ports {io_led[7]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_led[7]}] +set_property PACKAGE_PIN V13 [get_ports {io_led[8]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_led[8]}] +set_property PACKAGE_PIN V3 [get_ports {io_led[9]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_led[9]}] +set_property PACKAGE_PIN W3 [get_ports {io_led[10]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_led[10]}] +set_property PACKAGE_PIN U3 [get_ports {io_led[11]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_led[11]}] +set_property PACKAGE_PIN P3 [get_ports {io_led[12]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_led[12]}] +set_property PACKAGE_PIN N3 [get_ports {io_led[13]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_led[13]}] +set_property PACKAGE_PIN P1 [get_ports {io_led[14]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_led[14]}] +set_property PACKAGE_PIN L1 [get_ports {io_led[15]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_led[15]}] + + +##7 segment display +set_property PACKAGE_PIN U7 [get_ports io_segs[0]] + set_property IOSTANDARD LVCMOS33 [get_ports io_segs[0]] +set_property PACKAGE_PIN V5 [get_ports io_segs[1]] + set_property IOSTANDARD LVCMOS33 [get_ports io_segs[1]] +set_property PACKAGE_PIN U5 [get_ports io_segs[2]] + set_property IOSTANDARD LVCMOS33 [get_ports io_segs[2]] +set_property PACKAGE_PIN V8 [get_ports io_segs[3]] + set_property IOSTANDARD LVCMOS33 [get_ports io_segs[3]] +set_property PACKAGE_PIN U8 [get_ports io_segs[4]] + set_property IOSTANDARD LVCMOS33 [get_ports io_segs[4]] +set_property PACKAGE_PIN W6 [get_ports io_segs[5]] + set_property IOSTANDARD LVCMOS33 [get_ports io_segs[5]] +set_property PACKAGE_PIN W7 [get_ports io_segs[6]] + set_property IOSTANDARD LVCMOS33 [get_ports io_segs[6]] +set_property PACKAGE_PIN V7 [get_ports io_segs[7]] + set_property IOSTANDARD LVCMOS33 [get_ports io_segs[7]] + +set_property PACKAGE_PIN U2 [get_ports {io_digit_mask[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_digit_mask[0]}] +set_property PACKAGE_PIN U4 [get_ports {io_digit_mask[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_digit_mask[1]}] +set_property PACKAGE_PIN V4 [get_ports {io_digit_mask[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_digit_mask[2]}] +set_property PACKAGE_PIN W4 [get_ports {io_digit_mask[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_digit_mask[3]}] + + +##Buttons +set_property PACKAGE_PIN U18 [get_ports reset] + set_property IOSTANDARD LVCMOS33 [get_ports reset] +#set_property PACKAGE_PIN T18 [get_ports io_freqIncrease] + #set_property IOSTANDARD LVCMOS33 [get_ports io_freqIncrease] +#set_property PACKAGE_PIN W19 [get_ports io_widthIncrease] + #set_property IOSTANDARD LVCMOS33 [get_ports io_widthIncrease] +#set_property PACKAGE_PIN T17 [get_ports io_widthDecrease] + #set_property IOSTANDARD LVCMOS33 [get_ports io_widthDecrease] +#set_property PACKAGE_PIN U17 [get_ports io_freqDecrease] + #set_property IOSTANDARD LVCMOS33 [get_ports io_freqDecrease] + + + +##Pmod Header JA +##Sch name = JA1 +#set_property PACKAGE_PIN J1 [get_ports {JA[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}] +##Sch name = JA2 +#set_property PACKAGE_PIN L2 [get_ports {JA[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}] +##Sch name = JA3 +#set_property PACKAGE_PIN J2 [get_ports {JA[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}] +##Sch name = JA4 +#set_property PACKAGE_PIN G2 [get_ports {JA[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}] +##Sch name = JA7 +#set_property PACKAGE_PIN H1 [get_ports {JA[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}] +##Sch name = JA8 +#set_property PACKAGE_PIN K2 [get_ports {JA[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}] +##Sch name = JA9 +#set_property PACKAGE_PIN H2 [get_ports {JA[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}] +##Sch name = JA10 +#set_property PACKAGE_PIN G3 [get_ports {JA[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}] + + + +##Pmod Header JB +##Sch name = JB1 +#set_property PACKAGE_PIN A14 [get_ports {JB[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}] +##Sch name = JB2 +#set_property PACKAGE_PIN A16 [get_ports {JB[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}] +##Sch name = JB3 +#set_property PACKAGE_PIN B15 [get_ports {JB[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}] +##Sch name = JB4 +#set_property PACKAGE_PIN B16 [get_ports {JB[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}] +##Sch name = JB7 +#set_property PACKAGE_PIN A15 [get_ports {JB[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}] +##Sch name = JB8 +#set_property PACKAGE_PIN A17 [get_ports {JB[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}] +##Sch name = JB9 +#set_property PACKAGE_PIN C15 [get_ports {JB[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}] +##Sch name = JB10 +#set_property PACKAGE_PIN C16 [get_ports {JB[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}] + + + +##Pmod Header JC +##Sch name = JC1 +#set_property PACKAGE_PIN K17 [get_ports {JC[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}] +##Sch name = JC2 +#set_property PACKAGE_PIN M18 [get_ports {JC[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}] +##Sch name = JC3 +#set_property PACKAGE_PIN N17 [get_ports {JC[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}] +##Sch name = JC4 +#set_property PACKAGE_PIN P18 [get_ports {JC[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}] +##Sch name = JC7 +#set_property PACKAGE_PIN L17 [get_ports {JC[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}] +##Sch name = JC8 +#set_property PACKAGE_PIN M19 [get_ports {JC[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}] +##Sch name = JC9 +#set_property PACKAGE_PIN P17 [get_ports {JC[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}] +##Sch name = JC10 +#set_property PACKAGE_PIN R18 [get_ports {JC[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}] + + +##Pmod Header JXADC +##Sch name = XA1_P +#set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}] +##Sch name = XA2_P +#set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}] +##Sch name = XA3_P +#set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}] +##Sch name = XA4_P +#set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}] +##Sch name = XA1_N +#set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}] +##Sch name = XA2_N +#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}] +##Sch name = XA3_N +#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}] +##Sch name = XA4_N +#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}] + + + +##VGA Connector +set_property PACKAGE_PIN G19 [get_ports {io_rgb[8]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_rgb[8]}] +set_property PACKAGE_PIN H19 [get_ports {io_rgb[9]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_rgb[9]}] +set_property PACKAGE_PIN J19 [get_ports {io_rgb[10]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_rgb[10]}] +set_property PACKAGE_PIN N19 [get_ports {io_rgb[11]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_rgb[11]}] +set_property PACKAGE_PIN N18 [get_ports {io_rgb[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_rgb[0]}] +set_property PACKAGE_PIN L18 [get_ports {io_rgb[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_rgb[1]}] +set_property PACKAGE_PIN K18 [get_ports {io_rgb[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_rgb[2]}] +set_property PACKAGE_PIN J18 [get_ports {io_rgb[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_rgb[3]}] +set_property PACKAGE_PIN J17 [get_ports {io_rgb[4]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_rgb[4]}] +set_property PACKAGE_PIN H17 [get_ports {io_rgb[5]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_rgb[5]}] +set_property PACKAGE_PIN G17 [get_ports {io_rgb[6]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_rgb[6]}] +set_property PACKAGE_PIN D17 [get_ports {io_rgb[7]}] + set_property IOSTANDARD LVCMOS33 [get_ports {io_rgb[7]}] +set_property PACKAGE_PIN P19 [get_ports io_hsync] + set_property IOSTANDARD LVCMOS33 [get_ports io_hsync] +set_property PACKAGE_PIN R19 [get_ports io_vsync] + set_property IOSTANDARD LVCMOS33 [get_ports io_vsync] + + +##USB-RS232 Interface +set_property PACKAGE_PIN B18 [get_ports io_rx] + set_property IOSTANDARD LVCMOS33 [get_ports io_rx] +set_property PACKAGE_PIN A18 [get_ports io_tx] + set_property IOSTANDARD LVCMOS33 [get_ports io_tx] + + +##USB HID (PS/2) +#set_property PACKAGE_PIN C17 [get_ports PS2Clk] + #set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk] + #set_property PULLUP true [get_ports PS2Clk] +#set_property PACKAGE_PIN B17 [get_ports PS2Data] + #set_property IOSTANDARD LVCMOS33 [get_ports PS2Data] + #set_property PULLUP true [get_ports PS2Data] + + +##Quad SPI Flash +##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the +##STARTUPE2 primitive. +#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}] +#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}] +#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}] +#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}] +#set_property PACKAGE_PIN K19 [get_ports QspiCSn] + #set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn] + + +## Configuration options, can be used for all designs +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property CFGBVS VCCO [current_design] diff --git a/mini-yatcpu/vivado/basys3/generate_and_program.tcl b/mini-yatcpu/vivado/basys3/generate_and_program.tcl new file mode 100644 index 0000000..71df1af --- /dev/null +++ b/mini-yatcpu/vivado/basys3/generate_and_program.tcl @@ -0,0 +1,17 @@ +# Copyright 2021 Howard Lau +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Only tested on Vivado 2020.1 on Windows 10 +source generate_bitstream.tcl +source program_device.tcl \ No newline at end of file diff --git a/mini-yatcpu/vivado/basys3/generate_bitstream.tcl b/mini-yatcpu/vivado/basys3/generate_bitstream.tcl new file mode 100644 index 0000000..e1a26fb --- /dev/null +++ b/mini-yatcpu/vivado/basys3/generate_bitstream.tcl @@ -0,0 +1,55 @@ +# Copyright 2021 Howard Lau +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +source open_project.tcl + +while 1 { + if { [catch {launch_runs synth_1 -jobs 4 } ] } { + regexp {ERROR: \[Common (\d+-\d+)]} $errorInfo -> code + if { [string equal $code "12-978"] } { + puts "Already generated and up-to-date" + break + } elseif { [string equal $code "17-69"] } { + puts "Out of date, reset runs" + reset_runs synth_1 + continue + } else { + puts "UNKNOWN ERROR!!! $errorInfo" + exit + } + } + break +} + +wait_on_run synth_1 + +while 1 { + if { [catch {launch_runs impl_1 -jobs 4 -to_step write_bitstream } ] } { + regexp {ERROR: \[Vivado (\d+-\d+)]} $errorInfo -> code + if { [string equal $code "12-978"] } { + puts "Already generated and up-to-date" + break + } elseif { [string equal $code "12-1088"] } { + puts "Out of date, reset runs" + reset_runs impl_1 + continue + } else { + puts "UNKNOWN ERROR!!! $errorInfo" + exit + } + } + break +} + +wait_on_run impl_1 diff --git a/mini-yatcpu/vivado/basys3/open_project.tcl b/mini-yatcpu/vivado/basys3/open_project.tcl new file mode 100644 index 0000000..b20931a --- /dev/null +++ b/mini-yatcpu/vivado/basys3/open_project.tcl @@ -0,0 +1,39 @@ +# Copyright 2021 Howard Lau +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Only tested on Vivado 2020.1 on Windows 10 + +# set variables +set project_dir riscv-basys3 +set project_name riscv-basys3 +set part xc7a35tcpg236-1 +set sources {../../verilog/basys3/Top.v} +set test_sources {../../verilog/basys3/test.v} + +# open the project. will create one if it doesn't exist +if {[file exist $project_dir]} { + # check that it's a directory + if {! [file isdirectory $project_dir]} { + puts "$project_dir exists, but it's a file" + } + open_project $project_dir/$project_name.xpr -part $part +} else { + create_project $project_name $project_dir -part $part +} + +add_files -norecurse $sources +update_compile_order -fileset sources_1 +add_files -fileset constrs_1 -norecurse basys3.xdc +add_files -fileset sim_1 -norecurse $test_sources +update_compile_order -fileset sim_1 diff --git a/mini-yatcpu/vivado/basys3/program_device.tcl b/mini-yatcpu/vivado/basys3/program_device.tcl new file mode 100644 index 0000000..12fe648 --- /dev/null +++ b/mini-yatcpu/vivado/basys3/program_device.tcl @@ -0,0 +1,24 @@ +# Copyright 2021 Howard Lau +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Only tested on Vivado 2020.1 on Windows 10 +open_hw_manager +connect_hw_server -allow_non_jtag +open_hw_target +current_hw_device [get_hw_devices xc7a35t_0] +refresh_hw_server [current_hw_server] +open_hw_target [lindex [get_hw_targets] 0] +set_property PROGRAM.FILE {./riscv-basys3/riscv-basys3.runs/impl_1/Top.bit} [get_hw_devices xc7a35t_0] +program_hw_devices [get_hw_devices xc7a35t_0] +close_hw_target diff --git a/mini-yatcpu/vivado/basys3/run.ps1 b/mini-yatcpu/vivado/basys3/run.ps1 new file mode 100644 index 0000000..178feab --- /dev/null +++ b/mini-yatcpu/vivado/basys3/run.ps1 @@ -0,0 +1,4 @@ +cd .. +sbt run +cd vivado +C:\Xilinx\Vivado\2020.1\bin\vivado -mode batch -source .\generate_and_program.tcl \ No newline at end of file diff --git a/mini-yatcpu/vivado/basys3/run_simulation.tcl b/mini-yatcpu/vivado/basys3/run_simulation.tcl new file mode 100644 index 0000000..7c1a23c --- /dev/null +++ b/mini-yatcpu/vivado/basys3/run_simulation.tcl @@ -0,0 +1,24 @@ +# Copyright 2021 Howard Lau +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +source open_project.tcl + +launch_simulation +restart +open_vcd +log_wave -recursive [get_object /test/top/cpu/*] +log_vcd [get_object /test/top/cpu/*] +run 1000ns +close_vcd +close_sim diff --git a/mini-yatcpu/vivado/pynq/generate_and_program.tcl b/mini-yatcpu/vivado/pynq/generate_and_program.tcl new file mode 100644 index 0000000..71df1af --- /dev/null +++ b/mini-yatcpu/vivado/pynq/generate_and_program.tcl @@ -0,0 +1,17 @@ +# Copyright 2021 Howard Lau +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Only tested on Vivado 2020.1 on Windows 10 +source generate_bitstream.tcl +source program_device.tcl \ No newline at end of file diff --git a/mini-yatcpu/vivado/pynq/generate_bitstream.tcl b/mini-yatcpu/vivado/pynq/generate_bitstream.tcl new file mode 100644 index 0000000..886475e --- /dev/null +++ b/mini-yatcpu/vivado/pynq/generate_bitstream.tcl @@ -0,0 +1,57 @@ +# Copyright 2021 Howard Lau +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +source open_project.tcl +set_param general.maxThreads 16 +update_module_reference design_1_Top_0_0 + +while 1 { + if { [catch {launch_runs synth_1 -jobs 16 } ] } { + regexp {ERROR: \[Common (\d+-\d+)]} $errorInfo -> code + if { [string equal $code "12-978"] } { + puts "Already generated and up-to-date" + break + } elseif { [string equal $code "17-69"] } { + puts "Out of date, reset runs" + reset_runs synth_1 + continue + } else { + puts "UNKNOWN ERROR!!! $errorInfo" + exit + } + } + break +} + +wait_on_run synth_1 + +while 1 { + if { [catch {launch_runs impl_1 -jobs 16 -to_step write_bitstream } ] } { + regexp {ERROR: \[Vivado (\d+-\d+)]} $errorInfo -> code + if { [string equal $code "12-978"] } { + puts "Already generated and up-to-date" + break + } elseif { [string equal $code "12-1088"] } { + puts "Out of date, reset runs" + reset_runs impl_1 + continue + } else { + puts "UNKNOWN ERROR!!! $errorInfo" + exit + } + } + break +} + +wait_on_run impl_1 diff --git a/mini-yatcpu/vivado/pynq/open_project.tcl b/mini-yatcpu/vivado/pynq/open_project.tcl new file mode 100644 index 0000000..19a2dc2 --- /dev/null +++ b/mini-yatcpu/vivado/pynq/open_project.tcl @@ -0,0 +1,33 @@ +# Copyright 2021 Howard Lau +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Only tested on Vivado 2020.1 on Windows 10 + +# set variables +set project_dir riscv-pynq +set project_name riscv-pynq +set part xc7z020clg400-1 +set sources {../../verilog/pynq/Top.v} +set test_sources {../../verilog/pynq/test.v} + +# open the project. will create one if it doesn't exist +if {[file exist $project_dir]} { + # check that it's a directory + if {! [file isdirectory $project_dir]} { + puts "$project_dir exists, but it's a file" + } + open_project $project_dir/$project_name.xpr -part $part +} else { + source riscv-pynq.tcl +} \ No newline at end of file diff --git a/mini-yatcpu/vivado/pynq/program_device.tcl b/mini-yatcpu/vivado/pynq/program_device.tcl new file mode 100644 index 0000000..fb6caab --- /dev/null +++ b/mini-yatcpu/vivado/pynq/program_device.tcl @@ -0,0 +1,22 @@ +# Copyright 2021 Howard Lau +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Only tested on Vivado 2020.1 on Windows 10 +open_hw_manager +connect_hw_server -allow_non_jtag +refresh_hw_server [current_hw_server] +open_hw_target [lindex [get_hw_targets] 0] +set_property PROGRAM.FILE {riscv-pynq/riscv-pynq.runs/impl_1/design_1_wrapper.bit} [get_hw_devices xc7z020_1] +program_hw_devices [get_hw_devices xc7z020_1] +close_hw_target diff --git a/mini-yatcpu/vivado/pynq/pynq.xdc b/mini-yatcpu/vivado/pynq/pynq.xdc new file mode 100644 index 0000000..94761f0 --- /dev/null +++ b/mini-yatcpu/vivado/pynq/pynq.xdc @@ -0,0 +1,202 @@ +## This file is a general .xdc for the PYNQ-Z1 board Rev. C +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Clock signal 125 MHz + +set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports clock] +create_clock -period 8.000 -name sys_clk_pin -waveform {0.000 4.000} -add [get_ports clock] + +##Switches + +set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { io_debug_step }]; #IO_L7N_T1_AD2N_35 Sch=sw[0] +#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L7P_T1_AD2P_35 Sch=sw[1] + +##RGB LEDs + +#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { led4_b }]; #IO_L22N_T3_AD7N_35 Sch=led4_b +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { led4_g }]; #IO_L16P_T2_35 Sch=led4_g +#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led4_r }]; #IO_L21P_T3_DQS_AD14P_35 Sch=led4_r +#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led5_b }]; #IO_0_35 Sch=led5_b +#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { led5_g }]; #IO_L22P_T3_AD7P_35 Sch=led5_g +#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led5_r }]; #IO_L23N_T3_35 Sch=led5_r + +##LEDs + +set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {io_led[0]}] +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {io_led[1]}] +set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports {io_led[2]}] +set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports {io_led[3]}] + +##Buttons + +set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS33} [get_ports reset] +set_property -dict { PACKAGE_PIN D20 IOSTANDARD LVCMOS33 } [get_ports { io_debug_clk }]; #IO_L4N_T0_35 Sch=btn[1] +#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=btn[2] +#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=btn[3] + +##Pmod Header JA + +#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { io_rx }]; #IO_L17P_T2_34 Sch=ja_p[1] +#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { io_tx }]; #IO_L17N_T2_34 Sch=ja_n[1] +# set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports io_rx] +# set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33} [get_ports io_tx] +#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L12P_T1_MRCC_34 Sch=ja_p[3] +#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L12N_T1_MRCC_34 Sch=ja_n[3] +#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22P_T3_34 Sch=ja_p[4] +#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22N_T3_34 Sch=ja_n[4] + +##Pmod Header JB + +#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L8P_T1_34 Sch=jb_p[1] +#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L8N_T1_34 Sch=jb_n[1] +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports io_rx] +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports io_tx] +#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L18P_T2_34 Sch=jb_p[3] +#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L18N_T2_34 Sch=jb_n[3] +#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L4P_T0_34 Sch=jb_p[4] +#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L4N_T0_34 Sch=jb_n[4] + +##Audio Out + +#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L20N_T3_34 Sch=aud_pwm +#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L20P_T3_34 Sch=aud_sd + +##Mic input + +#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_L6N_T0_VREF_35 Sch=m_clk +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L16N_T2_35 Sch=m_data + +##ChipKit Single Ended Analog Inputs +##NOTE: The ck_an_p pins can be used as single ended analog inputs with voltages from 0-3.3V (Chipkit Analog pins A0-A5). +## These signals should only be connected to the XADC core. When using these pins as digital I/O, use pins ck_io[14-19]. + +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[0] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=ck_an_n[0] +#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[0] }]; #IO_L3P_T0_DQS_AD1P_35 Sch=ck_an_p[0] +#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[1] }]; #IO_L5N_T0_AD9N_35 Sch=ck_an_n[1] +#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[1] }]; #IO_L5P_T0_AD9P_35 Sch=ck_an_p[1] +#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[2] }]; #IO_L20N_T3_AD6N_35 Sch=ck_an_n[2] +#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[2] }]; #IO_L20P_T3_AD6P_35 Sch=ck_an_p[2] +#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[3] }]; #IO_L24N_T3_AD15N_35 Sch=ck_an_n[3] +#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[3] }]; #IO_L24P_T3_AD15P_35 Sch=ck_an_p[3] +#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[4] }]; #IO_L17N_T2_AD5N_35 Sch=ck_an_n[4] +#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[4] }]; #IO_L17P_T2_AD5P_35 Sch=ck_an_p[4] +#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[5] }]; #IO_L18N_T2_AD13N_35 Sch=ck_an_n[5] +#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[5] }]; #IO_L18P_T2_AD13P_35 Sch=ck_an_p[5] + +##ChipKit Digital I/O Low + +#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io[0] }]; #IO_L5P_T0_34 Sch=ck_io[0] +#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { ck_io[1] }]; #IO_L2N_T0_34 Sch=ck_io[1] +#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { ck_io[2] }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=ck_io[2] +#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { ck_io[3] }]; #IO_L3N_T0_DQS_34 Sch=ck_io[3] +#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[4] }]; #IO_L10P_T1_34 Sch=ck_io[4] +#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[5] }]; #IO_L5N_T0_34 Sch=ck_io[5] +#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[6] }]; #IO_L19P_T3_34 Sch=ck_io[6] +#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[7] }]; #IO_L9N_T1_DQS_34 Sch=ck_io[7] +#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[8] }]; #IO_L21P_T3_DQS_34 Sch=ck_io[8] +#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { ck_io[9] }]; #IO_L21N_T3_DQS_34 Sch=ck_io[9] +#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[10] }]; #IO_L9P_T1_DQS_34 Sch=ck_io[10] +#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[11] }]; #IO_L19N_T3_VREF_34 Sch=ck_io[11] +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io[12] }]; #IO_L23N_T3_34 Sch=ck_io[12] +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[13] }]; #IO_L23P_T3_34 Sch=ck_io[13] + +##ChipKit Digital I/O On Outer Analog Header +##NOTE: These pins should be used when using the analog header signals A0-A5 as digital I/O (Chipkit digital pins 14-19) + +#set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS33 } [get_ports { ck_io[14] }]; #IO_L18N_T2_13 Sch=ck_a[0] +#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { ck_io[15] }]; #IO_L20P_T3_13 Sch=ck_a[1] +#set_property -dict { PACKAGE_PIN W11 IOSTANDARD LVCMOS33 } [get_ports { ck_io[16] }]; #IO_L18P_T2_13 Sch=ck_a[2] +#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { ck_io[17] }]; #IO_L21P_T3_DQS_13 Sch=ck_a[3] +#set_property -dict { PACKAGE_PIN T5 IOSTANDARD LVCMOS33 } [get_ports { ck_io[18] }]; #IO_L19P_T3_13 Sch=ck_a[4] +#set_property -dict { PACKAGE_PIN U10 IOSTANDARD LVCMOS33 } [get_ports { ck_io[19] }]; #IO_L12N_T1_MRCC_13 Sch=ck_a[5] + +##ChipKit Digital I/O On Inner Analog Header +##NOTE: These pins will need to be connected to the XADC core when used as differential analog inputs (Chipkit analog pins A6-A11) + +#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { ck_io[20] }]; #IO_L1N_T0_AD0N_35 Sch=ad_n[0] +#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { ck_io[21] }]; #IO_L1P_T0_AD0P_35 Sch=ad_p[0] +#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { ck_io[22] }]; #IO_L15N_T2_DQS_AD12N_35 Sch=ad_n[12] +#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { ck_io[23] }]; #IO_L15P_T2_DQS_AD12P_35 Sch=ad_p[12] +#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { ck_io[24] }]; #IO_L2N_T0_AD8N_35 Sch=ad_n[8] +#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { ck_io[25] }]; #IO_L2P_T0_AD8P_35 Sch=ad_p[8] + +##ChipKit Digital I/O High + +#set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports { ck_io[26] }]; #IO_L19N_T3_VREF_13 Sch=ck_io[26] +#set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports { ck_io[27] }]; #IO_L6N_T0_VREF_13 Sch=ck_io[27] +#set_property -dict { PACKAGE_PIN V6 IOSTANDARD LVCMOS33 } [get_ports { ck_io[28] }]; #IO_L22P_T3_13 Sch=ck_io[28] +#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { ck_io[29] }]; #IO_L11P_T1_SRCC_13 Sch=ck_io[29] +#set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { ck_io[30] }]; #IO_L11N_T1_SRCC_13 Sch=ck_io[30] +#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports { ck_io[31] }]; #IO_L17N_T2_13 Sch=ck_io[31] +#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { ck_io[32] }]; #IO_L15P_T2_DQS_13 Sch=ck_io[32] +#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { ck_io[33] }]; #IO_L21N_T3_DQS_13 Sch=ck_io[33] +#set_property -dict { PACKAGE_PIN W10 IOSTANDARD LVCMOS33 } [get_ports { ck_io[34] }]; #IO_L16P_T2_13 Sch=ck_io[34] +#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { ck_io[35] }]; #IO_L22N_T3_13 Sch=ck_io[35] +#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { ck_io[36] }]; #IO_L13N_T2_MRCC_13 Sch=ck_io[36] +#set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { ck_io[37] }]; #IO_L13P_T2_MRCC_13 Sch=ck_io[37] +#set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS33 } [get_ports { ck_io[38] }]; #IO_L15N_T2_DQS_13 Sch=ck_io[38] +#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { ck_io[39] }]; #IO_L14N_T2_SRCC_13 Sch=ck_io[39] +#set_property -dict { PACKAGE_PIN W9 IOSTANDARD LVCMOS33 } [get_ports { ck_io[40] }]; #IO_L16N_T2_13 Sch=ck_io[40] +#set_property -dict { PACKAGE_PIN Y9 IOSTANDARD LVCMOS33 } [get_ports { ck_io[41] }]; #IO_L14P_T2_SRCC_13 Sch=ck_io[41] +#set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 } [get_ports { ck_io[42] }]; #IO_L20N_T3_13 Sch=ck_ioa + +## ChipKit SPI + +#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L10N_T1_34 Sch=ck_miso +#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L2P_T0_34 Sch=ck_mosi +#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L19P_T3_35 Sch=ck_sck +#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L6P_T0_35 Sch=ck_ss + +## ChipKit I2C + +#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_34 Sch=ck_scl +#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_34 Sch=ck_sda + +##HDMI Rx + +#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L13N_T2_MRCC_35 Sch=hdmi_rx_cec +set_property -dict { PACKAGE_PIN P19 IOSTANDARD TMDS_33 } [get_ports { io_debug_hdmi_clk_n }]; #IO_L13N_T2_MRCC_34 Sch=hdmi_rx_clk_n +set_property -dict { PACKAGE_PIN N18 IOSTANDARD TMDS_33 } [get_ports { io_debug_hdmi_clk_p }]; #IO_L13P_T2_MRCC_34 Sch=hdmi_rx_clk_p +set_property -dict { PACKAGE_PIN W20 IOSTANDARD TMDS_33 } [get_ports { io_debug_hdmi_data_n[0] }]; #IO_L16N_T2_34 Sch=hdmi_rx_d_n[0] +set_property -dict { PACKAGE_PIN V20 IOSTANDARD TMDS_33 } [get_ports { io_debug_hdmi_data_p[0] }]; #IO_L16P_T2_34 Sch=hdmi_rx_d_p[0] +set_property -dict { PACKAGE_PIN U20 IOSTANDARD TMDS_33 } [get_ports { io_debug_hdmi_data_n[1] }]; #IO_L15N_T2_DQS_34 Sch=hdmi_rx_d_n[1] +set_property -dict { PACKAGE_PIN T20 IOSTANDARD TMDS_33 } [get_ports { io_debug_hdmi_data_p[1] }]; #IO_L15P_T2_DQS_34 Sch=hdmi_rx_d_p[1] +set_property -dict { PACKAGE_PIN P20 IOSTANDARD TMDS_33 } [get_ports { io_debug_hdmi_data_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=hdmi_rx_d_n[2] +set_property -dict { PACKAGE_PIN N20 IOSTANDARD TMDS_33 } [get_ports { io_debug_hdmi_data_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=hdmi_rx_d_p[2] +set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { io_debug_hdmi_hpdn }]; #IO_25_34 Sch=hdmi_rx_hpd +#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L11P_T1_SRCC_34 Sch=hdmi_rx_scl +#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L11N_T1_SRCC_34 Sch=hdmi_rx_sda + +##HDMI Tx + +#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L19N_T3_VREF_35 Sch=hdmi_tx_cec +set_property -dict {PACKAGE_PIN L17 IOSTANDARD TMDS_33} [get_ports io_hdmi_clk_n] +set_property -dict {PACKAGE_PIN L16 IOSTANDARD TMDS_33} [get_ports io_hdmi_clk_p] +set_property -dict {PACKAGE_PIN K18 IOSTANDARD TMDS_33} [get_ports {io_hdmi_data_n[0]}] +set_property -dict {PACKAGE_PIN K17 IOSTANDARD TMDS_33} [get_ports {io_hdmi_data_p[0]}] +set_property -dict {PACKAGE_PIN J19 IOSTANDARD TMDS_33} [get_ports {io_hdmi_data_n[1]}] +set_property -dict {PACKAGE_PIN K19 IOSTANDARD TMDS_33} [get_ports {io_hdmi_data_p[1]}] +set_property -dict {PACKAGE_PIN H18 IOSTANDARD TMDS_33} [get_ports {io_hdmi_data_n[2]}] +set_property -dict {PACKAGE_PIN J18 IOSTANDARD TMDS_33} [get_ports {io_hdmi_data_p[2]}] +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports io_hdmi_hpdn] +#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L8P_T1_AD10P_35 Sch=hdmi_tx_scl +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L8N_T1_AD10N_35 Sch=hdmi_tx_sda + +##Crypto SDA + +#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_25_35 Sch=crypto_sda + + + +connect_debug_port u_ila_0/probe0 [get_nets [list {cpu/cpu/clint/io_id_interrupt_handler_address[0]} {cpu/cpu/clint/io_id_interrupt_handler_address[1]} {cpu/cpu/clint/io_id_interrupt_handler_address[2]} {cpu/cpu/clint/io_id_interrupt_handler_address[3]} {cpu/cpu/clint/io_id_interrupt_handler_address[4]} {cpu/cpu/clint/io_id_interrupt_handler_address[5]} {cpu/cpu/clint/io_id_interrupt_handler_address[6]} {cpu/cpu/clint/io_id_interrupt_handler_address[7]} {cpu/cpu/clint/io_id_interrupt_handler_address[8]} {cpu/cpu/clint/io_id_interrupt_handler_address[9]} {cpu/cpu/clint/io_id_interrupt_handler_address[10]} {cpu/cpu/clint/io_id_interrupt_handler_address[11]} {cpu/cpu/clint/io_id_interrupt_handler_address[12]} {cpu/cpu/clint/io_id_interrupt_handler_address[13]} {cpu/cpu/clint/io_id_interrupt_handler_address[14]} {cpu/cpu/clint/io_id_interrupt_handler_address[15]} {cpu/cpu/clint/io_id_interrupt_handler_address[16]} {cpu/cpu/clint/io_id_interrupt_handler_address[17]} {cpu/cpu/clint/io_id_interrupt_handler_address[18]} {cpu/cpu/clint/io_id_interrupt_handler_address[19]} {cpu/cpu/clint/io_id_interrupt_handler_address[20]} {cpu/cpu/clint/io_id_interrupt_handler_address[21]} {cpu/cpu/clint/io_id_interrupt_handler_address[22]} {cpu/cpu/clint/io_id_interrupt_handler_address[23]} {cpu/cpu/clint/io_id_interrupt_handler_address[24]} {cpu/cpu/clint/io_id_interrupt_handler_address[25]} {cpu/cpu/clint/io_id_interrupt_handler_address[26]} {cpu/cpu/clint/io_id_interrupt_handler_address[27]} {cpu/cpu/clint/io_id_interrupt_handler_address[28]} {cpu/cpu/clint/io_id_interrupt_handler_address[29]} {cpu/cpu/clint/io_id_interrupt_handler_address[30]} {cpu/cpu/clint/io_id_interrupt_handler_address[31]}]] +connect_debug_port u_ila_0/probe1 [get_nets [list {cpu/cpu/csr_regs/io_clint_csr_mepc[0]} {cpu/cpu/csr_regs/io_clint_csr_mepc[1]} {cpu/cpu/csr_regs/io_clint_csr_mepc[2]} {cpu/cpu/csr_regs/io_clint_csr_mepc[3]} {cpu/cpu/csr_regs/io_clint_csr_mepc[4]} {cpu/cpu/csr_regs/io_clint_csr_mepc[5]} {cpu/cpu/csr_regs/io_clint_csr_mepc[6]} {cpu/cpu/csr_regs/io_clint_csr_mepc[7]} {cpu/cpu/csr_regs/io_clint_csr_mepc[8]} {cpu/cpu/csr_regs/io_clint_csr_mepc[9]} {cpu/cpu/csr_regs/io_clint_csr_mepc[10]} {cpu/cpu/csr_regs/io_clint_csr_mepc[11]} {cpu/cpu/csr_regs/io_clint_csr_mepc[12]} {cpu/cpu/csr_regs/io_clint_csr_mepc[13]} {cpu/cpu/csr_regs/io_clint_csr_mepc[14]} {cpu/cpu/csr_regs/io_clint_csr_mepc[15]} {cpu/cpu/csr_regs/io_clint_csr_mepc[16]} {cpu/cpu/csr_regs/io_clint_csr_mepc[17]} {cpu/cpu/csr_regs/io_clint_csr_mepc[18]} {cpu/cpu/csr_regs/io_clint_csr_mepc[19]} {cpu/cpu/csr_regs/io_clint_csr_mepc[20]} {cpu/cpu/csr_regs/io_clint_csr_mepc[21]} {cpu/cpu/csr_regs/io_clint_csr_mepc[22]} {cpu/cpu/csr_regs/io_clint_csr_mepc[23]} {cpu/cpu/csr_regs/io_clint_csr_mepc[24]} {cpu/cpu/csr_regs/io_clint_csr_mepc[25]} {cpu/cpu/csr_regs/io_clint_csr_mepc[26]} {cpu/cpu/csr_regs/io_clint_csr_mepc[27]} {cpu/cpu/csr_regs/io_clint_csr_mepc[28]} {cpu/cpu/csr_regs/io_clint_csr_mepc[29]} {cpu/cpu/csr_regs/io_clint_csr_mepc[30]} {cpu/cpu/csr_regs/io_clint_csr_mepc[31]}]] +connect_debug_port u_ila_0/probe2 [get_nets [list {cpu/cpu/csr_regs/io_clint_csr_mstatus[0]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[1]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[2]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[3]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[4]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[5]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[6]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[7]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[8]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[9]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[10]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[11]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[12]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[13]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[14]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[15]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[16]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[17]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[18]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[19]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[20]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[21]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[22]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[23]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[24]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[25]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[26]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[27]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[28]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[29]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[30]} {cpu/cpu/csr_regs/io_clint_csr_mstatus[31]}]] +connect_debug_port u_ila_0/probe3 [get_nets [list {cpu/cpu/csr_regs/io_clint_csr_mtvec[0]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[1]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[2]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[3]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[4]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[5]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[6]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[7]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[8]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[9]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[10]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[11]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[12]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[13]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[14]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[15]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[16]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[17]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[18]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[19]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[20]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[21]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[22]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[23]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[24]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[25]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[26]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[27]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[28]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[29]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[30]} {cpu/cpu/csr_regs/io_clint_csr_mtvec[31]}]] +connect_debug_port u_ila_0/probe4 [get_nets [list {cpu/cpu/inst_fetch/io_id_instruction_address[0]} {cpu/cpu/inst_fetch/io_id_instruction_address[1]} {cpu/cpu/inst_fetch/io_id_instruction_address[2]} {cpu/cpu/inst_fetch/io_id_instruction_address[3]} {cpu/cpu/inst_fetch/io_id_instruction_address[4]} {cpu/cpu/inst_fetch/io_id_instruction_address[5]} {cpu/cpu/inst_fetch/io_id_instruction_address[6]} {cpu/cpu/inst_fetch/io_id_instruction_address[7]} {cpu/cpu/inst_fetch/io_id_instruction_address[8]} {cpu/cpu/inst_fetch/io_id_instruction_address[9]} {cpu/cpu/inst_fetch/io_id_instruction_address[10]} {cpu/cpu/inst_fetch/io_id_instruction_address[11]} {cpu/cpu/inst_fetch/io_id_instruction_address[12]} {cpu/cpu/inst_fetch/io_id_instruction_address[13]} {cpu/cpu/inst_fetch/io_id_instruction_address[14]} {cpu/cpu/inst_fetch/io_id_instruction_address[15]} {cpu/cpu/inst_fetch/io_id_instruction_address[16]} {cpu/cpu/inst_fetch/io_id_instruction_address[17]} {cpu/cpu/inst_fetch/io_id_instruction_address[18]} {cpu/cpu/inst_fetch/io_id_instruction_address[19]} {cpu/cpu/inst_fetch/io_id_instruction_address[20]} {cpu/cpu/inst_fetch/io_id_instruction_address[21]} {cpu/cpu/inst_fetch/io_id_instruction_address[22]} {cpu/cpu/inst_fetch/io_id_instruction_address[23]} {cpu/cpu/inst_fetch/io_id_instruction_address[24]} {cpu/cpu/inst_fetch/io_id_instruction_address[25]} {cpu/cpu/inst_fetch/io_id_instruction_address[26]} {cpu/cpu/inst_fetch/io_id_instruction_address[27]} {cpu/cpu/inst_fetch/io_id_instruction_address[28]} {cpu/cpu/inst_fetch/io_id_instruction_address[29]} {cpu/cpu/inst_fetch/io_id_instruction_address[30]} {cpu/cpu/inst_fetch/io_id_instruction_address[31]}]] +connect_debug_port u_ila_0/probe5 [get_nets [list {cpu_io_interrupt_flag[0]} {cpu_io_interrupt_flag[1]} {cpu_io_interrupt_flag[2]} {cpu_io_interrupt_flag[3]} {cpu_io_interrupt_flag[4]} {cpu_io_interrupt_flag[5]} {cpu_io_interrupt_flag[6]} {cpu_io_interrupt_flag[7]} {cpu_io_interrupt_flag[8]} {cpu_io_interrupt_flag[9]} {cpu_io_interrupt_flag[10]} {cpu_io_interrupt_flag[11]} {cpu_io_interrupt_flag[12]} {cpu_io_interrupt_flag[13]} {cpu_io_interrupt_flag[14]} {cpu_io_interrupt_flag[15]} {cpu_io_interrupt_flag[16]} {cpu_io_interrupt_flag[17]} {cpu_io_interrupt_flag[18]} {cpu_io_interrupt_flag[19]} {cpu_io_interrupt_flag[20]} {cpu_io_interrupt_flag[21]} {cpu_io_interrupt_flag[22]} {cpu_io_interrupt_flag[23]} {cpu_io_interrupt_flag[24]} {cpu_io_interrupt_flag[25]} {cpu_io_interrupt_flag[26]} {cpu_io_interrupt_flag[27]} {cpu_io_interrupt_flag[28]} {cpu_io_interrupt_flag[29]} {cpu_io_interrupt_flag[30]} {cpu_io_interrupt_flag[31]}]] +connect_debug_port u_ila_0/probe6 [get_nets [list cpu/cpu/clint/io_exception_signal]] +connect_debug_port u_ila_0/probe7 [get_nets [list cpu/cpu/clint/io_id_interrupt_assert]] +connect_debug_port u_ila_0/probe8 [get_nets [list uart_io_signal_interrupt]] + diff --git a/mini-yatcpu/vivado/pynq/riscv-pynq.tcl b/mini-yatcpu/vivado/pynq/riscv-pynq.tcl new file mode 100644 index 0000000..9f033d7 --- /dev/null +++ b/mini-yatcpu/vivado/pynq/riscv-pynq.tcl @@ -0,0 +1,1602 @@ +#***************************************************************************************** +# Vivado (TM) v2020.1 (64-bit) +# +# riscv-pynq.tcl: Tcl script for re-creating project 'riscv-pynq' +# +# Generated by Vivado on Thu Jun 09 10:55:13 +0800 2022 +# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 +# +# This file contains the Vivado Tcl commands for re-creating the project to the state* +# when this script was generated. In order to re-create the project, please source this +# file in the Vivado Tcl Shell. +# +# * Note that the runs in the created project will be configured the same way as the +# original project, however they will not be launched automatically. To regenerate the +# run results please launch the synthesis/implementation runs as needed. +# +#***************************************************************************************** +# NOTE: In order to use this script for source control purposes, please make sure that the +# following files are added to the source control system:- +# +# 1. This project restoration tcl script (riscv-pynq.tcl) that was generated. +# +# 2. The following source(s) files that were local or imported into the original project. +# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) +# +# "verilog/pynq/design_1_wrapper.v" +# +# 3. The following remote source files that were added to the original project:- +# +# "verilog/pynq/TMDS_PLLVR.v" +# "verilog/pynq/Top.v" +# "vivado/pynq/pynq.xdc" +# "verilog/pynq/test.v" +# +#***************************************************************************************** + +# Set the reference directory for source file relative paths (by default the value is script directory path) +set origin_dir "../.." + +# Use origin directory path location variable, if specified in the tcl shell +if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc +} + +# Set the project name +set _xil_proj_name_ "riscv-pynq" + +# Use project name variable, if specified in the tcl shell +if { [info exists ::user_project_name] } { + set _xil_proj_name_ $::user_project_name +} + +variable script_file +set script_file "riscv-pynq.tcl" + +# Help information for this script +proc print_help {} { + variable script_file + puts "\nDescription:" + puts "Recreate a Vivado project from this script. The created project will be" + puts "functionally equivalent to the original project for which this script was" + puts "generated. The script contains commands for creating a project, filesets," + puts "runs, adding/importing sources and setting properties on various objects.\n" + puts "Syntax:" + puts "$script_file" + puts "$script_file -tclargs \[--origin_dir \]" + puts "$script_file -tclargs \[--project_name \]" + puts "$script_file -tclargs \[--help\]\n" + puts "Usage:" + puts "Name Description" + puts "-------------------------------------------------------------------------" + puts "\[--origin_dir \] Determine source file paths wrt this path. Default" + puts " origin_dir path value is \".\", otherwise, the value" + puts " that was set with the \"-paths_relative_to\" switch" + puts " when this script was generated.\n" + puts "\[--project_name \] Create project with the specified name. Default" + puts " name is the name of the project from where this" + puts " script was generated.\n" + puts "\[--help\] Print help information for this script" + puts "-------------------------------------------------------------------------\n" + exit 0 +} + +if { $::argc > 0 } { + for {set i 0} {$i < $::argc} {incr i} { + set option [string trim [lindex $::argv $i]] + switch -regexp -- $option { + "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } + "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] } + "--help" { print_help } + default { + if { [regexp {^-} $option] } { + puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n" + return 1 + } + } + } + } +} + +# Set the directory path for the original project from where this script was exported +set orig_proj_dir "[file normalize "$origin_dir/vivado/pynq/riscv-pynq"]" + +# Create project +create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z020clg400-1 + +# Set the directory path for the new project +set proj_dir [get_property directory [current_project]] + +# Set project properties +set obj [current_project] +set_property -name "default_lib" -value "xil_defaultlib" -objects $obj +set_property -name "enable_vhdl_2008" -value "1" -objects $obj +set_property -name "ip_cache_permissions" -value "read write" -objects $obj +set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj +set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj +set_property -name "part" -value "xc7z020clg400-1" -objects $obj +set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj +set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj +set_property -name "simulator_language" -value "Mixed" -objects $obj +set_property -name "webtalk.activehdl_export_sim" -value "1" -objects $obj +set_property -name "webtalk.ies_export_sim" -value "1" -objects $obj +set_property -name "webtalk.modelsim_export_sim" -value "1" -objects $obj +set_property -name "webtalk.questa_export_sim" -value "1" -objects $obj +set_property -name "webtalk.riviera_export_sim" -value "1" -objects $obj +set_property -name "webtalk.vcs_export_sim" -value "1" -objects $obj +set_property -name "webtalk.xcelium_export_sim" -value "1" -objects $obj +set_property -name "webtalk.xsim_export_sim" -value "1" -objects $obj +set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj + +# Create 'sources_1' fileset (if not found) +if {[string equal [get_filesets -quiet sources_1] ""]} { + create_fileset -srcset sources_1 +} + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/verilog/pynq/TMDS_PLLVR.v"] \ + [file normalize "${origin_dir}/verilog/pynq/Top.v"] \ +] +add_files -norecurse -fileset $obj $files + +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/verilog/pynq/design_1_wrapper.v" ]\ +] +set imported_files [import_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset properties +set obj [get_filesets sources_1] +set_property -name "top" -value "design_1_wrapper" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj + +# Create 'constrs_1' fileset (if not found) +if {[string equal [get_filesets -quiet constrs_1] ""]} { + create_fileset -constrset constrs_1 +} + +# Set 'constrs_1' fileset object +set obj [get_filesets constrs_1] + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/vivado/pynq/pynq.xdc"]" +set file_added [add_files -norecurse -fileset $obj [list $file]] +set file "$origin_dir/vivado/pynq/pynq.xdc" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj + +# Set 'constrs_1' fileset properties +set obj [get_filesets constrs_1] +set_property -name "target_part" -value "xc7z020clg400-1" -objects $obj + +# Create 'sim_1' fileset (if not found) +if {[string equal [get_filesets -quiet sim_1] ""]} { + create_fileset -simset sim_1 +} + +# Set 'sim_1' fileset object +set obj [get_filesets sim_1] +set files [list \ + [file normalize "${origin_dir}/verilog/pynq/test.v"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sim_1' fileset file properties for remote files +# None + +# Set 'sim_1' fileset file properties for local files +# None + +# Set 'sim_1' fileset properties +set obj [get_filesets sim_1] +set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj +set_property -name "top" -value "test" -objects $obj +set_property -name "top_lib" -value "xil_defaultlib" -objects $obj + +# Set 'utils_1' fileset object +set obj [get_filesets utils_1] +# Empty (no sources present) + +# Set 'utils_1' fileset properties +set obj [get_filesets utils_1] + + +# Adding sources referenced in BDs, if not already added +if { [get_files TMDS_PLLVR.v] == "" } { + import_files -quiet -fileset sources_1 ${origin_dir}/verilog/pynq/TMDS_PLLVR.v +} +if { [get_files Top.v] == "" } { + import_files -quiet -fileset sources_1 ${origin_dir}/verilog/pynq/Top.v +} + + +# Proc to create BD design_1 +proc cr_bd_design_1 { parentCell } { +# The design that will be created by this Tcl proc contains the following +# module references: +# Top + + + + # CHANGE DESIGN NAME HERE + set design_name design_1 + + common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + set bCheckIPsPassed 1 + ################################################################## + # CHECK IPs + ################################################################## + set bCheckIPs 1 + if { $bCheckIPs == 1 } { + set list_check_ips "\ + xilinx.com:ip:processing_system7:5.5\ + xilinx.com:ip:proc_sys_reset:5.0\ + " + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + + } + + ################################################################## + # CHECK Modules + ################################################################## + set bCheckModules 1 + if { $bCheckModules == 1 } { + set list_check_mods "\ + Top\ + " + + set list_mods_missing "" + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + + if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 + } + + variable script_folder + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] + + set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] + + + # Create ports + set io_hdmi_clk_n [ create_bd_port -dir O -type clk io_hdmi_clk_n ] + set io_hdmi_clk_p [ create_bd_port -dir O -type clk io_hdmi_clk_p ] + set io_hdmi_data_n [ create_bd_port -dir O -from 2 -to 0 io_hdmi_data_n ] + set io_hdmi_data_p [ create_bd_port -dir O -from 2 -to 0 io_hdmi_data_p ] + set io_hdmi_hpdn [ create_bd_port -dir O io_hdmi_hpdn ] + set io_led [ create_bd_port -dir O -from 3 -to 0 io_led ] + set io_rx [ create_bd_port -dir I io_rx ] + set io_tx [ create_bd_port -dir O io_tx ] + set reset [ create_bd_port -dir I -type rst reset ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ + ] $reset + + # Create instance: Top_0, and set properties + set block_name Top + set block_cell_name Top_0 + if { [catch {set Top_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $Top_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ + ] [get_bd_pins /Top_0/reset] + + # Create instance: axi_mem_intercon, and set properties + set axi_mem_intercon [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_intercon ] + set_property -dict [ list \ + CONFIG.NUM_MI {1} \ + ] $axi_mem_intercon + + # Create instance: processing_system7_0, and set properties + set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] + set_property -dict [ list \ + CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {650.000000} \ + CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \ + CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095} \ + CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.096154} \ + CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \ + CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {125.000000} \ + CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \ + CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {108.333336} \ + CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {108.333336} \ + CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {108.333336} \ + CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {108.333336} \ + CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {108.333336} \ + CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {108.333336} \ + CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} \ + CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} \ + CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {108.333336} \ + CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \ + CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {650} \ + CONFIG.PCW_ARMPLL_CTRL_FBDIV {26} \ + CONFIG.PCW_CAN0_BASEADDR {0xE0008000} \ + CONFIG.PCW_CAN0_CAN0_IO {} \ + CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF} \ + CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \ + CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1} \ + CONFIG.PCW_CAN1_BASEADDR {0xE0009000} \ + CONFIG.PCW_CAN1_CAN1_IO {} \ + CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} \ + CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \ + CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1} \ + CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_CAN_PERIPHERAL_VALID {0} \ + CONFIG.PCW_CLK0_FREQ {125000000} \ + CONFIG.PCW_CLK1_FREQ {10000000} \ + CONFIG.PCW_CLK2_FREQ {10000000} \ + CONFIG.PCW_CLK3_FREQ {10000000} \ + CONFIG.PCW_CORE0_FIQ_INTR {0} \ + CONFIG.PCW_CORE0_IRQ_INTR {0} \ + CONFIG.PCW_CORE1_FIQ_INTR {0} \ + CONFIG.PCW_CORE1_IRQ_INTR {0} \ + CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \ + CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1300.000} \ + CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \ + CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {52} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {2} \ + CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \ + CONFIG.PCW_DDRPLL_CTRL_FBDIV {21} \ + CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1050.000} \ + CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \ + CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \ + CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \ + CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \ + CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \ + CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \ + CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \ + CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \ + CONFIG.PCW_DDR_PRIORITY_READPORT_0 {} \ + CONFIG.PCW_DDR_PRIORITY_READPORT_2 {} \ + CONFIG.PCW_DDR_PRIORITY_WRITEPORT_0 {} \ + CONFIG.PCW_DDR_PRIORITY_WRITEPORT_2 {} \ + CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \ + CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \ + CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \ + CONFIG.PCW_DM_WIDTH {4} \ + CONFIG.PCW_DQS_WIDTH {4} \ + CONFIG.PCW_DQ_WIDTH {32} \ + CONFIG.PCW_ENET0_BASEADDR {0xE000B000} \ + CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \ + CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ + CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \ + CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF} \ + CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \ + CONFIG.PCW_ENET0_RESET_ENABLE {1} \ + CONFIG.PCW_ENET0_RESET_IO {MIO 9} \ + CONFIG.PCW_ENET1_BASEADDR {0xE000C000} \ + CONFIG.PCW_ENET1_ENET1_IO {} \ + CONFIG.PCW_ENET1_HIGHADDR {0xE000CFFF} \ + CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \ + CONFIG.PCW_ENET1_RESET_ENABLE {0} \ + CONFIG.PCW_ENET1_RESET_IO {} \ + CONFIG.PCW_FTM_CTI_IN1 {} \ + CONFIG.PCW_FTM_CTI_IN3 {} \ + CONFIG.PCW_FTM_CTI_OUT1 {} \ + CONFIG.PCW_FTM_CTI_OUT3 {} \ + CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \ + CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF} \ + CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ + CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ + CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_I2C0_BASEADDR {0xE0004000} \ + CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \ + CONFIG.PCW_I2C0_GRP_INT_IO {} \ + CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_I2C0_RESET_ENABLE {0} \ + CONFIG.PCW_I2C0_RESET_IO {} \ + CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF} \ + CONFIG.PCW_I2C1_I2C1_IO {} \ + CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \ + CONFIG.PCW_I2C_RESET_ENABLE {1} \ + CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \ + CONFIG.PCW_I2C_RESET_SELECT {} \ + CONFIG.PCW_NAND_NAND_IO {} \ + CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_CS0_IO {} \ + CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_SRAM_CS0_IO {} \ + CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_SRAM_INT_IO {} \ + CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1} \ + CONFIG.PCW_NOR_SRAM_CS0_T_PC {1} \ + CONFIG.PCW_NOR_SRAM_CS0_T_RC {11} \ + CONFIG.PCW_NOR_SRAM_CS0_T_TR {1} \ + CONFIG.PCW_NOR_SRAM_CS0_T_WC {11} \ + CONFIG.PCW_NOR_SRAM_CS0_T_WP {1} \ + CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {0} \ + CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1} \ + CONFIG.PCW_NOR_SRAM_CS1_T_PC {1} \ + CONFIG.PCW_NOR_SRAM_CS1_T_RC {11} \ + CONFIG.PCW_NOR_SRAM_CS1_T_TR {1} \ + CONFIG.PCW_NOR_SRAM_CS1_T_WC {11} \ + CONFIG.PCW_NOR_SRAM_CS1_T_WP {1} \ + CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0} \ + CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \ + CONFIG.PCW_P2F_CAN0_INTR {0} \ + CONFIG.PCW_P2F_CAN1_INTR {0} \ + CONFIG.PCW_P2F_CTI_INTR {0} \ + CONFIG.PCW_P2F_DMAC0_INTR {0} \ + CONFIG.PCW_P2F_DMAC1_INTR {0} \ + CONFIG.PCW_P2F_DMAC2_INTR {0} \ + CONFIG.PCW_P2F_DMAC3_INTR {0} \ + CONFIG.PCW_P2F_DMAC4_INTR {0} \ + CONFIG.PCW_P2F_DMAC5_INTR {0} \ + CONFIG.PCW_P2F_DMAC6_INTR {0} \ + CONFIG.PCW_P2F_DMAC7_INTR {0} \ + CONFIG.PCW_P2F_DMAC_ABORT_INTR {0} \ + CONFIG.PCW_P2F_ENET0_INTR {0} \ + CONFIG.PCW_P2F_ENET1_INTR {0} \ + CONFIG.PCW_P2F_GPIO_INTR {0} \ + CONFIG.PCW_P2F_I2C0_INTR {0} \ + CONFIG.PCW_P2F_I2C1_INTR {0} \ + CONFIG.PCW_P2F_QSPI_INTR {0} \ + CONFIG.PCW_P2F_SDIO0_INTR {0} \ + CONFIG.PCW_P2F_SDIO1_INTR {0} \ + CONFIG.PCW_P2F_SMC_INTR {0} \ + CONFIG.PCW_P2F_SPI0_INTR {0} \ + CONFIG.PCW_P2F_SPI1_INTR {0} \ + CONFIG.PCW_P2F_UART0_INTR {0} \ + CONFIG.PCW_P2F_UART1_INTR {0} \ + CONFIG.PCW_P2F_USB0_INTR {0} \ + CONFIG.PCW_P2F_USB1_INTR {0} \ + CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.223} \ + CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.212} \ + CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.085} \ + CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.092} \ + CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {0.040} \ + CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {0.058} \ + CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \ + CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \ + CONFIG.PCW_PACKAGE_NAME {clg400} \ + CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \ + CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \ + CONFIG.PCW_PERIPHERAL_BOARD_PRESET {None} \ + CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_PJTAG_PJTAG_IO {} \ + CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \ + CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \ + CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \ + CONFIG.PCW_QSPI_GRP_SS1_IO {} \ + CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \ + CONFIG.PCW_SD0_GRP_WP_IO {} \ + CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \ + CONFIG.PCW_SD1_GRP_POW_IO {} \ + CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_SD1_SD1_IO {} \ + CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \ + CONFIG.PCW_SPI0_GRP_SS1_IO {} \ + CONFIG.PCW_SPI0_HIGHADDR {0xE0006FFF} \ + CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_SPI0_SPI0_IO {} \ + CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \ + CONFIG.PCW_SPI1_GRP_SS1_IO {} \ + CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF} \ + CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_SPI1_SPI1_IO {} \ + CONFIG.PCW_TRACE_GRP_2BIT_ENABLE {0} \ + CONFIG.PCW_TRACE_GRP_2BIT_IO {} \ + CONFIG.PCW_TRACE_GRP_4BIT_ENABLE {0} \ + CONFIG.PCW_TRACE_GRP_4BIT_IO {} \ + CONFIG.PCW_TRACE_INTERNAL_WIDTH {2} \ + CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_TRACE_PIPELINE_WIDTH {8} \ + CONFIG.PCW_TRACE_TRACE_IO {} \ + CONFIG.PCW_TTC1_BASEADDR {0xE0105000} \ + CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \ + CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ {133.333333} \ + CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \ + CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ {133.333333} \ + CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \ + CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ {133.333333} \ + CONFIG.PCW_TTC1_HIGHADDR {0xE0105fff} \ + CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_TTC1_TTC1_IO {} \ + CONFIG.PCW_UART0_HIGHADDR {0xE0000FFF} \ + CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \ + CONFIG.PCW_UART1_BASEADDR {0xE0001000} \ + CONFIG.PCW_UART1_BAUD_RATE {115200} \ + CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \ + CONFIG.PCW_UART1_GRP_FULL_IO {} \ + CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \ + CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_UART_PERIPHERAL_VALID {1} \ + CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {525.000000} \ + CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \ + CONFIG.PCW_UIPARAM_DDR_AL {0} \ + CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \ + CONFIG.PCW_UIPARAM_DDR_BL {8} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.223} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.212} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.085} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.092} \ + CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \ + CONFIG.PCW_UIPARAM_DDR_CL {7} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {25.8} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.4535} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {25.8} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.4535} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.4535} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.4535} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \ + CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \ + CONFIG.PCW_UIPARAM_DDR_CWL {6} \ + CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \ + CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {15.6} \ + CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {105.056} \ + CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {18.8} \ + CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {66.904} \ + CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0} \ + CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {89.1715} \ + CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0} \ + CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.63} \ + CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.040} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.058} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \ + CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {16.5} \ + CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {98.503} \ + CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {18} \ + CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {68.5855} \ + CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0} \ + CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {90.295} \ + CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0} \ + CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {103.977} \ + CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \ + CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \ + CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \ + CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {525} \ + CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \ + CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3} \ + CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \ + CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \ + CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \ + CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \ + CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \ + CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \ + CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \ + CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \ + CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \ + CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \ + CONFIG.PCW_UIPARAM_DDR_T_RP {7} \ + CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \ + CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NA} \ + CONFIG.PCW_USB0_BASEADDR {0xE0102000} \ + CONFIG.PCW_USB0_HIGHADDR {0xE0102fff} \ + CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \ + CONFIG.PCW_USB0_RESET_ENABLE {1} \ + CONFIG.PCW_USB0_RESET_IO {MIO 46} \ + CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \ + CONFIG.PCW_USB1_BASEADDR {0xE0103000} \ + CONFIG.PCW_USB1_HIGHADDR {0xE0103fff} \ + CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ {60} \ + CONFIG.PCW_USB1_RESET_ENABLE {0} \ + CONFIG.PCW_USB1_RESET_IO {} \ + CONFIG.PCW_USB_RESET_ENABLE {1} \ + CONFIG.PCW_USB_RESET_POLARITY {Active Low} \ + CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \ + CONFIG.PCW_USE_AXI_FABRIC_IDLE {0} \ + CONFIG.PCW_USE_AXI_NONSECURE {1} \ + CONFIG.PCW_USE_CORESIGHT {0} \ + CONFIG.PCW_USE_CROSS_TRIGGER {0} \ + CONFIG.PCW_USE_CR_FABRIC {1} \ + CONFIG.PCW_USE_DDR_BYPASS {0} \ + CONFIG.PCW_USE_DEBUG {0} \ + CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {0} \ + CONFIG.PCW_USE_DMA0 {0} \ + CONFIG.PCW_USE_DMA1 {0} \ + CONFIG.PCW_USE_DMA2 {0} \ + CONFIG.PCW_USE_DMA3 {0} \ + CONFIG.PCW_USE_EXPANDED_IOP {0} \ + CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS {0} \ + CONFIG.PCW_USE_FABRIC_INTERRUPT {0} \ + CONFIG.PCW_USE_HIGH_OCM {0} \ + CONFIG.PCW_USE_M_AXI_GP0 {0} \ + CONFIG.PCW_USE_M_AXI_GP1 {0} \ + CONFIG.PCW_USE_PROC_EVENT_BUS {0} \ + CONFIG.PCW_USE_PS_SLCR_REGISTERS {0} \ + CONFIG.PCW_USE_S_AXI_ACP {0} \ + CONFIG.PCW_USE_S_AXI_GP0 {0} \ + CONFIG.PCW_USE_S_AXI_GP1 {0} \ + CONFIG.PCW_USE_S_AXI_HP0 {1} \ + CONFIG.PCW_USE_S_AXI_HP1 {0} \ + CONFIG.PCW_USE_S_AXI_HP2 {0} \ + CONFIG.PCW_USE_S_AXI_HP3 {0} \ + CONFIG.PCW_USE_TRACE {0} \ + CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR {0} \ + CONFIG.PCW_VALUE_SILVERSION {3} \ + CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X} \ + CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \ + CONFIG.PCW_WDT_WDT_IO {