mirror of
https://github.com/handsomezhuzhu/2025-yatcpu.git
synced 2026-02-20 20:10:14 +00:00
498 lines
16 KiB
JSON
498 lines
16 KiB
JSON
[
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|AXI4LiteSlave",
|
|
"duplicate":"~Top|Top/uart:Uart/slave:AXI4LiteSlave",
|
|
"index":0.0
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/if2id:IF2ID/instruction:PipelineRegister",
|
|
"index":0.11842105263157894
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_1",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/if2id:IF2ID/instruction_address:PipelineRegister_1",
|
|
"index":0.13157894736842105
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_2",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/if2id:IF2ID/interrupt_flag:PipelineRegister_2",
|
|
"index":0.14473684210526316
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_3",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/instruction:PipelineRegister",
|
|
"index":0.18421052631578946
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_4",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/instruction_address:PipelineRegister_1",
|
|
"index":0.19736842105263158
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_5",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/regs_write_enable:PipelineRegister_5",
|
|
"index":0.21052631578947367
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_6",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/regs_write_address:PipelineRegister_6",
|
|
"index":0.2236842105263158
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_7",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/regs_write_source:PipelineRegister_7",
|
|
"index":0.23684210526315788
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_8",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/reg1_data:PipelineRegister_2",
|
|
"index":0.25
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_9",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/reg2_data:PipelineRegister_2",
|
|
"index":0.2631578947368421
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_10",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/immediate:PipelineRegister_2",
|
|
"index":0.27631578947368424
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_11",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/aluop1_source:PipelineRegister_5",
|
|
"index":0.2894736842105263
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_12",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/aluop2_source:PipelineRegister_5",
|
|
"index":0.3026315789473684
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_13",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/csr_write_enable:PipelineRegister_5",
|
|
"index":0.3157894736842105
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_15",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/memory_read_enable:PipelineRegister_5",
|
|
"index":0.34210526315789475
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_16",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/memory_write_enable:PipelineRegister_5",
|
|
"index":0.35526315789473684
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_17",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/id2ex:ID2EX/csr_read_data:PipelineRegister_2",
|
|
"index":0.3684210526315789
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_18",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/regs_write_enable:PipelineRegister_5",
|
|
"index":0.4342105263157895
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_19",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/regs_write_source:PipelineRegister_7",
|
|
"index":0.4473684210526316
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_20",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/regs_write_address:PipelineRegister_6",
|
|
"index":0.4605263157894737
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_21",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/instruction_address:PipelineRegister_2",
|
|
"index":0.47368421052631576
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_22",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/instruction:PipelineRegister_2",
|
|
"index":0.4868421052631579
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_23",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/reg1_data:PipelineRegister_2",
|
|
"index":0.5
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_24",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/reg2_data:PipelineRegister_2",
|
|
"index":0.5131578947368421
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_25",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/alu_result:PipelineRegister_2",
|
|
"index":0.5263157894736842
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_26",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/memory_read_enable:PipelineRegister_5",
|
|
"index":0.5394736842105263
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_27",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/memory_write_enable:PipelineRegister_5",
|
|
"index":0.5526315789473685
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_28",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/ex2mem:EX2MEM/csr_read_data:PipelineRegister_2",
|
|
"index":0.5657894736842105
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_29",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/alu_result:PipelineRegister_2",
|
|
"index":0.6052631578947368
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_30",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/memory_read_data:PipelineRegister_2",
|
|
"index":0.618421052631579
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_31",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/regs_write_enable:PipelineRegister_5",
|
|
"index":0.631578947368421
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_32",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/regs_write_source:PipelineRegister_7",
|
|
"index":0.6447368421052632
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_33",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/regs_write_address:PipelineRegister_6",
|
|
"index":0.6578947368421053
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_34",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/instruction_address:PipelineRegister_2",
|
|
"index":0.6710526315789473
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|PipelineRegister_35",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/mem2wb:MEM2WB/csr_read_data:PipelineRegister_2",
|
|
"index":0.6842105263157895
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|AXI4LiteMaster",
|
|
"duplicate":"~Top|Top/cpu:CPU_1/cpu:CPU/axi4_master:AXI4LiteMaster",
|
|
"index":0.7631578947368421
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|AXI4LiteSlave_1",
|
|
"duplicate":"~Top|Top/mem:Memory/slave:AXI4LiteSlave_1",
|
|
"index":0.8289473684210527
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|AXI4LiteSlave_2",
|
|
"duplicate":"~Top|Top/timer:Timer/slave:AXI4LiteSlave",
|
|
"index":0.8552631578947368
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|AXI4LiteSlave_3",
|
|
"duplicate":"~Top|Top/dummy:DummySlave/slave:AXI4LiteSlave_1",
|
|
"index":0.881578947368421
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|AXI4LiteMaster_1",
|
|
"duplicate":"~Top|Top/bus_switch:BusSwitch/dummy:DummyMaster/master:AXI4LiteMaster",
|
|
"index":0.9210526315789473
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DedupedResult",
|
|
"original":"~Top|AXI4LiteMaster_2",
|
|
"duplicate":"~Top|Top/rom_loader:ROMLoader/master:AXI4LiteMaster",
|
|
"index":0.9736842105263158
|
|
},
|
|
{
|
|
"class":"firrtl.EmitCircuitAnnotation",
|
|
"emitter":"firrtl.VerilogEmitter"
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
|
|
"target":"Top.AXI4LiteMaster.state",
|
|
"enumTypeName":"bus.AXI4LiteStates"
|
|
},
|
|
{
|
|
"class":"firrtl.annotations.MemorySynthInit$"
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
|
|
"target":"Top.AXI4LiteSlave_1.state",
|
|
"enumTypeName":"bus.AXI4LiteStates"
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
|
|
"target":"Top.AXI4LiteSlave.state",
|
|
"enumTypeName":"bus.AXI4LiteStates"
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation",
|
|
"typeName":"riscv.core.fivestage.MEMAccessState",
|
|
"definition":{
|
|
"if_address_translate":1,
|
|
"if_access":4,
|
|
"idle":0,
|
|
"mem_address_translate":2,
|
|
"mem_access":3
|
|
}
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
|
|
"target":"Top.CPU.mem_access_state",
|
|
"enumTypeName":"riscv.core.fivestage.MEMAccessState"
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation",
|
|
"typeName":"riscv.core.fivestage.BUSGranted",
|
|
"definition":{
|
|
"mmu_if_granted":4,
|
|
"if_granted":1,
|
|
"mmu_mem_granted":3,
|
|
"mem_granted":2,
|
|
"idle":0
|
|
}
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
|
|
"target":"Top.CPU.bus_granted",
|
|
"enumTypeName":"riscv.core.fivestage.BUSGranted"
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation",
|
|
"typeName":"riscv.core.fivestage.MMUStates",
|
|
"definition":{
|
|
"checkpte1":2,
|
|
"gotPhyicalAddress":6,
|
|
"setADbit":5,
|
|
"idle":0,
|
|
"checkpte0":4,
|
|
"level1":1,
|
|
"level0":3
|
|
}
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
|
|
"target":"Top.MMU.state",
|
|
"enumTypeName":"riscv.core.fivestage.MMUStates"
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation",
|
|
"typeName":"riscv.core.fivestage.MemoryAccessStates",
|
|
"definition":{
|
|
"Idle":0,
|
|
"Read":1,
|
|
"Write":2,
|
|
"ReadWrite":3
|
|
}
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
|
|
"target":"Top.MemoryAccess.mem_access_state",
|
|
"enumTypeName":"riscv.core.fivestage.MemoryAccessStates"
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
|
|
"target":"Top.ALUControl._io_alu_funct_T_33",
|
|
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
|
|
"target":"Top.ALUControl._io_alu_funct_T_31",
|
|
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
|
|
"target":"Top.ALUControl._io_alu_funct_T_29",
|
|
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
|
|
"target":"Top.ALUControl._io_alu_funct_T_27",
|
|
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
|
|
"target":"Top.ALUControl._io_alu_funct_T_25",
|
|
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
|
|
"target":"Top.ALUControl._io_alu_funct_T_23",
|
|
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
|
|
"target":"Top.ALUControl._io_alu_funct_T_21",
|
|
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
|
|
"target":"Top.ALUControl._io_alu_funct_T_17",
|
|
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
|
|
"target":"Top.ALUControl._io_alu_funct_T_15",
|
|
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
|
|
"target":"Top.ALUControl._io_alu_funct_T_13",
|
|
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
|
|
"target":"Top.ALUControl._io_alu_funct_T_11",
|
|
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
|
|
"target":"Top.ALUControl._io_alu_funct_T_9",
|
|
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
|
|
"target":"Top.ALUControl._io_alu_funct_T_7",
|
|
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
|
|
"target":"Top.ALUControl._io_alu_funct_T_5",
|
|
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
|
|
"target":"Top.ALUControl._io_alu_funct_T_3",
|
|
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
|
|
"target":"Top.ALUControl._io_alu_funct_T_1",
|
|
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
|
|
"target":"Top.ALUControl.io_alu_funct",
|
|
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation",
|
|
"typeName":"riscv.core.fivestage.ALUFunctions",
|
|
"definition":{
|
|
"sll":3,
|
|
"sra":9,
|
|
"or":6,
|
|
"xor":5,
|
|
"slt":4,
|
|
"sub":2,
|
|
"add":1,
|
|
"sltu":10,
|
|
"and":7,
|
|
"srl":8,
|
|
"zero":0
|
|
}
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
|
|
"target":"Top.ALU.io_func",
|
|
"enumTypeName":"riscv.core.fivestage.ALUFunctions"
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation",
|
|
"typeName":"riscv.core.fivestage.IFAccessStates",
|
|
"definition":{
|
|
"idle":0,
|
|
"read":1
|
|
}
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
|
|
"target":"Top.InstructionFetch.state",
|
|
"enumTypeName":"riscv.core.fivestage.IFAccessStates"
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation",
|
|
"typeName":"bus.AXI4LiteStates",
|
|
"definition":{
|
|
"ReadData":2,
|
|
"WriteAddr":3,
|
|
"WriteResp":5,
|
|
"Idle":0,
|
|
"WriteData":4,
|
|
"ReadAddr":1
|
|
}
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation",
|
|
"typeName":"board.z710.BootStates",
|
|
"definition":{
|
|
"Init":0,
|
|
"Loading":1,
|
|
"BusWait":2,
|
|
"Finished":3
|
|
}
|
|
},
|
|
{
|
|
"class":"chisel3.experimental.EnumAnnotations$EnumComponentAnnotation",
|
|
"target":"Top.Top.boot_state",
|
|
"enumTypeName":"board.z710.BootStates"
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
|
"targetDir":"verilog/z710"
|
|
},
|
|
{
|
|
"class":"firrtl.annotations.MemoryFileInlineAnnotation",
|
|
"target":"~Top|InstructionROM>mem",
|
|
"filename":"/workspaces/2023-fall-yatcpu-repo/mini-yatcpu/verilog/say_goodbye.asmbin.txt",
|
|
"hexOrBinary":"h"
|
|
}
|
|
] |