update clock_contrl.v for lab4 Z710

2026-02-20 20:10:14 +00:00 · 2024-11-19 01:29:05 +08:00
parent e4a4c6bf20
commit 5c930b046c
1 changed files with 1 additions and 1 deletions
--- a/lab4/verilog/z710/clock_control.v
+++ b/lab4/verilog/z710/clock_control.v
@@ -23,7 +23,7 @@
 module clock_control(
    input clock_in,
    input enable_clk,
-    output reg clock_out
+    output clock_out
    );
    assign clock_out = clock_in & enable_clk;
 endmodule