diff --git a/lab4/verilog/z710/clock_control.v b/lab4/verilog/z710/clock_control.v
index 873ee85..b836ba8 100644
--- a/lab4/verilog/z710/clock_control.v
+++ b/lab4/verilog/z710/clock_control.v
@@ -23,7 +23,7 @@
 module clock_control(
     input clock_in,
     input enable_clk,
-    output reg clock_out
+    output clock_out
     );
     assign clock_out = clock_in & enable_clk;
 endmodule