From 5c930b046c37bc00786207b003a16d7d9c4563e2 Mon Sep 17 00:00:00 2001
From: PurplePower <60787289+PurplePower@users.noreply.github.com>
Date: Tue, 19 Nov 2024 01:29:05 +0800
Subject: [PATCH] update clock_contrl.v for lab4 Z710

---
 lab4/verilog/z710/clock_control.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lab4/verilog/z710/clock_control.v b/lab4/verilog/z710/clock_control.v
index 873ee85..b836ba8 100644
--- a/lab4/verilog/z710/clock_control.v
+++ b/lab4/verilog/z710/clock_control.v
@@ -23,7 +23,7 @@
 module clock_control(
     input clock_in,
     input enable_clk,
-    output reg clock_out
+    output clock_out
     );
     assign clock_out = clock_in & enable_clk;
 endmodule