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实验报告检查
This commit is contained in:
362
lab4/朱梓涵24325356/bus/AXI4Lite.scala
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362
lab4/朱梓涵24325356/bus/AXI4Lite.scala
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@@ -0,0 +1,362 @@
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// Copyright 2021 Howard Lau
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package bus
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import chisel3._
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import chisel3.experimental.ChiselEnum
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import chisel3.util._
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import riscv.Parameters
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object AXI4Lite {
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val protWidth = 3
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val respWidth = 2
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}
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class AXI4LiteWriteAddressChannel(addrWidth: Int) extends Bundle {
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val AWVALID = Output(Bool())
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val AWREADY = Input(Bool())
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val AWADDR = Output(UInt(addrWidth.W))
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val AWPROT = Output(UInt(AXI4Lite.protWidth.W))
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}
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class AXI4LiteWriteDataChannel(dataWidth: Int) extends Bundle {
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val WVALID = Output(Bool())
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val WREADY = Input(Bool())
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val WDATA = Output(UInt(dataWidth.W))
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val WSTRB = Output(UInt((dataWidth / 8).W))
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}
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class AXI4LiteWriteResponseChannel extends Bundle {
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val BVALID = Input(Bool())
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val BREADY = Output(Bool())
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val BRESP = Input(UInt(AXI4Lite.respWidth.W))
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}
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class AXI4LiteReadAddressChannel(addrWidth: Int) extends Bundle {
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val ARVALID = Output(Bool())
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val ARREADY = Input(Bool())
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val ARADDR = Output(UInt(addrWidth.W))
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val ARPROT = Output(UInt(AXI4Lite.protWidth.W))
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}
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class AXI4LiteReadDataChannel(dataWidth: Int) extends Bundle {
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val RVALID = Input(Bool())
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val RREADY = Output(Bool())
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val RDATA = Input(UInt(dataWidth.W))
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val RRESP = Input(UInt(AXI4Lite.respWidth.W))
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}
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class AXI4LiteInterface(addrWidth: Int, dataWidth: Int) extends Bundle {
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val AWVALID = Output(Bool())
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val AWREADY = Input(Bool())
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val AWADDR = Output(UInt(addrWidth.W))
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val AWPROT = Output(UInt(AXI4Lite.protWidth.W))
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val WVALID = Output(Bool())
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val WREADY = Input(Bool())
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val WDATA = Output(UInt(dataWidth.W))
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val WSTRB = Output(UInt((dataWidth / 8).W))
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val BVALID = Input(Bool())
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val BREADY = Output(Bool())
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val BRESP = Input(UInt(AXI4Lite.respWidth.W))
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val ARVALID = Output(Bool())
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val ARREADY = Input(Bool())
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val ARADDR = Output(UInt(addrWidth.W))
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val ARPROT = Output(UInt(AXI4Lite.protWidth.W))
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val RVALID = Input(Bool())
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val RREADY = Output(Bool())
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val RDATA = Input(UInt(dataWidth.W))
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val RRESP = Input(UInt(AXI4Lite.respWidth.W))
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}
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class AXI4LiteChannels(addrWidth: Int, dataWidth: Int) extends Bundle {
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val write_address_channel = new AXI4LiteWriteAddressChannel(addrWidth)
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val write_data_channel = new AXI4LiteWriteDataChannel(dataWidth)
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val write_response_channel = new AXI4LiteWriteResponseChannel()
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val read_address_channel = new AXI4LiteReadAddressChannel(addrWidth)
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val read_data_channel = new AXI4LiteReadDataChannel(dataWidth)
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}
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class AXI4LiteSlaveBundle(addrWidth: Int, dataWidth: Int) extends Bundle {
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val read = Output(Bool()) // tell slave device to read
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val write = Output(Bool()) // tell slave device to write
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val read_data = Input(UInt(dataWidth.W)) // data read from slave device
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val read_valid = Input(Bool()) // indicates if read_data is valid
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val write_data = Output(UInt(dataWidth.W))
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val write_strobe = Output(Vec(Parameters.WordSize, Bool()))
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val address = Output(UInt(addrWidth.W))
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}
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class AXI4LiteMasterBundle(addrWidth: Int, dataWidth: Int) extends Bundle {
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val read = Input(Bool()) // request a read transaction
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val write = Input(Bool()) // request a write transaction
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val read_data = Output(UInt(dataWidth.W))
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val write_data = Input(UInt(dataWidth.W))
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val write_strobe = Input(Vec(Parameters.WordSize, Bool()))
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val address = Input(UInt(addrWidth.W))
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val busy = Output(Bool()) // if busy, master is not ready to accept new transactions
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val read_valid = Output(Bool()) // indicates read transaction done successfully and asserts for ONLY 1 cycle.
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val write_valid = Output(Bool()) // indicates write transaction done successfully and asserts for ONLY 1 cycle.
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}
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object AXI4LiteStates extends ChiselEnum {
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val Idle, ReadAddr, ReadDataWait, ReadData, WriteAddr, WriteData, WriteResp = Value
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}
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class AXI4LiteSlave(addrWidth: Int, dataWidth: Int) extends Module {
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val io = IO(new Bundle {
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val channels = Flipped(new AXI4LiteChannels(addrWidth, dataWidth))
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val bundle = new AXI4LiteSlaveBundle(addrWidth, dataWidth)
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})
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val state = RegInit(AXI4LiteStates.Idle)
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val addr = RegInit(0.U(dataWidth.W))
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io.bundle.address := addr
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val read = RegInit(false.B)
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io.bundle.read := read
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val write = RegInit(false.B)
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io.bundle.write := write
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val write_data = RegInit(0.U(dataWidth.W))
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io.bundle.write_data := write_data
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val write_strobe = RegInit(VecInit(Seq.fill(Parameters.WordSize)(false.B)))
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io.bundle.write_strobe := write_strobe
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val ARREADY = RegInit(false.B)
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io.channels.read_address_channel.ARREADY := ARREADY
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val RVALID = RegInit(false.B)
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io.channels.read_data_channel.RVALID := RVALID
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val RRESP = RegInit(0.U(AXI4Lite.respWidth))
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io.channels.read_data_channel.RRESP := RRESP
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val AWREADY = RegInit(false.B)
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io.channels.write_address_channel.AWREADY := AWREADY
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val WREADY = RegInit(false.B)
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io.channels.write_data_channel.WREADY := WREADY
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write_data := io.channels.write_data_channel.WDATA
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val BVALID = RegInit(false.B)
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io.channels.write_response_channel.BVALID := BVALID
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val BRESP = WireInit(0.U(AXI4Lite.respWidth))
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io.channels.write_response_channel.BRESP := BRESP
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//lab4(BUS)
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// 读数据寄存器，保证 RDATA 在 RVALID 为高时稳定
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val rdataReg = RegInit(0.U(dataWidth.W))
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io.channels.read_data_channel.RDATA := rdataReg
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switch(state) {
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is(AXI4LiteStates.Idle) {
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// 默认信号
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ARREADY := false.B
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RVALID := false.B
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AWREADY := false.B
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WREADY := false.B
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BVALID := false.B
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read := false.B
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write := false.B
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when(io.channels.read_address_channel.ARVALID) {
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addr := io.channels.read_address_channel.ARADDR
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ARREADY := true.B
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state := AXI4LiteStates.ReadAddr
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}.elsewhen(io.channels.write_address_channel.AWVALID) {
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addr := io.channels.write_address_channel.AWADDR
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AWREADY := true.B
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state := AXI4LiteStates.WriteAddr
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}
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}
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is(AXI4LiteStates.ReadAddr) {
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// 已经完成 ARVALID/ARREADY 握手，将地址送给从设备并发起一次读
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ARREADY := false.B
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read := true.B
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state := AXI4LiteStates.ReadData
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}
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is(AXI4LiteStates.ReadData) {
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// 保持对设备的读请求，等待设备返回 read_valid
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read := true.B
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when(io.bundle.read_valid && !RVALID) {
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// 设备已经准备好数据，将其锁存并让RVALID为1
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rdataReg := io.bundle.read_data
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RVALID := true.B
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}.elsewhen(RVALID && io.channels.read_data_channel.RREADY) {
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// 主机已经接收数据，完成一次读事务
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RVALID := false.B
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read := false.B
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state := AXI4LiteStates.Idle
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}
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}
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is(AXI4LiteStates.WriteAddr) {
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// 写地址握手结束，等待写数据
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AWREADY := false.B
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when(io.channels.write_data_channel.WVALID) {
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// 收到写数据，锁存写数据及写选通
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write_data := io.channels.write_data_channel.WDATA
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val wstrb = io.channels.write_data_channel.WSTRB
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when(wstrb === 0.U) {
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write_strobe := VecInit(Seq.fill(Parameters.WordSize)(true.B))
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}.otherwise {
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write_strobe := VecInit(wstrb.asBools)
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}
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WREADY := true.B
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write := true.B
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state := AXI4LiteStates.WriteData
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}
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}
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is(AXI4LiteStates.WriteData) {
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// 向设备发出一次写请求，WREADY 在一个周期后拉低
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WREADY := false.B
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write := false.B
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BVALID := true.B
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state := AXI4LiteStates.WriteResp
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}
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is(AXI4LiteStates.WriteResp) {
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// 等待主机对写响应握手
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when(io.channels.write_response_channel.BREADY) {
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BVALID := false.B
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state := AXI4LiteStates.Idle
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}
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}
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}
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}
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class AXI4LiteMaster(addrWidth: Int, dataWidth: Int) extends Module {
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val io = IO(new Bundle {
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val channels = new AXI4LiteChannels(addrWidth, dataWidth)
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val bundle = new AXI4LiteMasterBundle(addrWidth, dataWidth)
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})
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val state = RegInit(AXI4LiteStates.Idle)
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io.bundle.busy := state =/= AXI4LiteStates.Idle
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val addr = RegInit(0.U(dataWidth.W))
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val read_valid = RegInit(false.B)
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io.bundle.read_valid := read_valid
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val write_valid = RegInit(false.B)
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io.bundle.write_valid := write_valid
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val write_data = RegInit(0.U(dataWidth.W))
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val write_strobe = RegInit(VecInit(Seq.fill(Parameters.WordSize)(false.B)))
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val read_data = RegInit(0.U(dataWidth.W))
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io.channels.read_address_channel.ARADDR := 0.U
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val ARVALID = RegInit(false.B)
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io.channels.read_address_channel.ARVALID := ARVALID
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io.channels.read_address_channel.ARPROT := 0.U
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val RREADY = RegInit(false.B)
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io.channels.read_data_channel.RREADY := RREADY
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io.bundle.read_data := read_data
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val AWVALID = RegInit(false.B)
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io.channels.write_address_channel.AWADDR := 0.U
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io.channels.write_address_channel.AWVALID := AWVALID
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val WVALID = RegInit(false.B)
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io.channels.write_data_channel.WVALID := WVALID
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io.channels.write_data_channel.WDATA := write_data
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io.channels.write_address_channel.AWPROT := 0.U
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io.channels.write_data_channel.WSTRB := write_strobe.asUInt
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val BREADY = RegInit(false.B)
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io.channels.write_response_channel.BREADY := BREADY
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//lab4(BUS)
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// read_valid / write_valid 只拉高一个周期，在switch之前清零以便switch可以覆盖
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when(read_valid) { read_valid := false.B }
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when(write_valid) { write_valid := false.B }
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switch(state) {
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is(AXI4LiteStates.Idle) {
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ARVALID := false.B
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RREADY := false.B
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AWVALID := false.B
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WVALID := false.B
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BREADY := false.B
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when(io.bundle.read) {
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// 发起读事务
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addr := io.bundle.address
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state := AXI4LiteStates.ReadAddr
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ARVALID := true.B
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}.elsewhen(io.bundle.write) {
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// 发起写事务
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addr := io.bundle.address
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write_data := io.bundle.write_data
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write_strobe := io.bundle.write_strobe
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state := AXI4LiteStates.WriteAddr
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AWVALID := true.B
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}
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}
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is(AXI4LiteStates.ReadAddr) {
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// 发送读地址，直到从机准备好
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ARVALID := true.B
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io.channels.read_address_channel.ARADDR := addr
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when(io.channels.read_address_channel.ARREADY) {
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ARVALID := false.B
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RREADY := true.B
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state := AXI4LiteStates.ReadData
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}
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}
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is(AXI4LiteStates.ReadData) {
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// 保持 RREADY 高，等待从机 RVALID
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RREADY := true.B
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when(io.channels.read_data_channel.RVALID) {
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read_data := io.channels.read_data_channel.RDATA
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RREADY := false.B
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read_valid := true.B
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state := AXI4LiteStates.Idle
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}
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}
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is(AXI4LiteStates.WriteAddr) {
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// 发送写地址，直到从机准备好
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AWVALID := true.B
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io.channels.write_address_channel.AWADDR := addr
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when(io.channels.write_address_channel.AWREADY) {
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AWVALID := false.B
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WVALID := true.B
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state := AXI4LiteStates.WriteData
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}
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}
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is(AXI4LiteStates.WriteData) {
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// 发送写数据，直到从机接受
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WVALID := true.B
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io.channels.write_data_channel.WDATA := write_data
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io.channels.write_data_channel.WSTRB := write_strobe.asUInt
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when(io.channels.write_data_channel.WREADY) {
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WVALID := false.B
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BREADY := true.B
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state := AXI4LiteStates.WriteResp
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}
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}
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is(AXI4LiteStates.WriteResp) {
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// 等待从机写响应
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BREADY := true.B
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when(io.channels.write_response_channel.BVALID) {
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BREADY := false.B
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write_valid := true.B
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state := AXI4LiteStates.Idle
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}
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}
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}
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|
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}
|
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40
lab4/朱梓涵24325356/bus/BusArbiter.scala
Normal file
40
lab4/朱梓涵24325356/bus/BusArbiter.scala
Normal file
@@ -0,0 +1,40 @@
|
||||
// Copyright 2021 Howard Lau
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
package bus
|
||||
|
||||
import chisel3._
|
||||
import riscv.Parameters
|
||||
|
||||
class BusArbiter extends Module {
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||||
val io = IO(new Bundle {
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||||
val bus_request = Input(Vec(Parameters.MasterDeviceCount, Bool()))
|
||||
val bus_granted = Output(Vec(Parameters.MasterDeviceCount, Bool()))
|
||||
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||||
val ctrl_stall_flag = Output(Bool())
|
||||
})
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val granted = Wire(UInt())
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// Static Priority Arbitration
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||||
// Higher number = Higher priority
|
||||
granted := 0.U
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||||
for (i <- 0 until Parameters.MasterDeviceCount) {
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||||
when(io.bus_request(i.U)) {
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||||
granted := i.U
|
||||
}
|
||||
}
|
||||
for (i <- 0 until Parameters.MasterDeviceCount) {
|
||||
io.bus_granted(i.U) := i.U === granted
|
||||
}
|
||||
io.ctrl_stall_flag := !io.bus_granted(0.U)
|
||||
}
|
||||
33
lab4/朱梓涵24325356/bus/BusSwitch.scala
Normal file
33
lab4/朱梓涵24325356/bus/BusSwitch.scala
Normal file
@@ -0,0 +1,33 @@
|
||||
// Copyright 2021 Howard Lau
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
package bus
|
||||
|
||||
import chisel3._
|
||||
import peripheral.DummyMaster
|
||||
import riscv.Parameters
|
||||
|
||||
class BusSwitch extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val address = Input(UInt(Parameters.AddrWidth))
|
||||
val slaves = Vec(Parameters.SlaveDeviceCount, new AXI4LiteChannels(Parameters.AddrBits, Parameters.DataBits))
|
||||
val master = Flipped(new AXI4LiteChannels(Parameters.AddrBits, Parameters.DataBits))
|
||||
})
|
||||
val dummy = Module(new DummyMaster)
|
||||
val index = io.address(Parameters.AddrBits - 1, Parameters.AddrBits - Parameters.SlaveDeviceCountBits)
|
||||
for (i <- 0 until Parameters.SlaveDeviceCount) {
|
||||
io.slaves(i) <> dummy.io.channels
|
||||
}
|
||||
io.master <> io.slaves(index)
|
||||
}
|
||||
Reference in New Issue
Block a user