mirror of
https://github.com/handsomezhuzhu/2025-yatcpu.git
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41 lines
1.2 KiB
Scala
41 lines
1.2 KiB
Scala
// Copyright 2021 Howard Lau
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package bus
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import chisel3._
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import riscv.Parameters
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class BusArbiter extends Module {
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val io = IO(new Bundle {
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val bus_request = Input(Vec(Parameters.MasterDeviceCount, Bool()))
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val bus_granted = Output(Vec(Parameters.MasterDeviceCount, Bool()))
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val ctrl_stall_flag = Output(Bool())
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})
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val granted = Wire(UInt())
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// Static Priority Arbitration
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// Higher number = Higher priority
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granted := 0.U
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for (i <- 0 until Parameters.MasterDeviceCount) {
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when(io.bus_request(i.U)) {
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granted := i.U
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}
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}
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for (i <- 0 until Parameters.MasterDeviceCount) {
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io.bus_granted(i.U) := i.U === granted
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}
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io.ctrl_stall_flag := !io.bus_granted(0.U)
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}
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