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https://github.com/handsomezhuzhu/2025-yatcpu.git
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34 lines
1.2 KiB
Scala
34 lines
1.2 KiB
Scala
// Copyright 2021 Howard Lau
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package bus
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import chisel3._
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import peripheral.DummyMaster
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import riscv.Parameters
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class BusSwitch extends Module {
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val io = IO(new Bundle {
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val address = Input(UInt(Parameters.AddrWidth))
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val slaves = Vec(Parameters.SlaveDeviceCount, new AXI4LiteChannels(Parameters.AddrBits, Parameters.DataBits))
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val master = Flipped(new AXI4LiteChannels(Parameters.AddrBits, Parameters.DataBits))
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})
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val dummy = Module(new DummyMaster)
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val index = io.address(Parameters.AddrBits - 1, Parameters.AddrBits - Parameters.SlaveDeviceCountBits)
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for (i <- 0 until Parameters.SlaveDeviceCount) {
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io.slaves(i) <> dummy.io.channels
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}
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io.master <> io.slaves(index)
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}
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