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board updates and fixes

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- now VCD is written in all tests by default, turn it on/off in TestAnnotations.scala
- updated cmakelists.txt
- added board program scripts and sources for Zynq 7000 v1.3 2024/02 board, lab1 only currently
This commit is contained in:
PurplePower
2024-11-18 10:50:45 +08:00
parent 358100ec57
commit 3e3c8ba6c0
18 changed files with 1043 additions and 13 deletions
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29
lab1/vivado/z710v1.3/z710v1.3.xdc Normal file
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## This file is for SYSU computer organization courses.
## used for Zynq7010 fpga revision 1.3 2024/02
# clock, 50 MHz
set_property IOSTANDARD LVCMOS33 [get_ports io_clock];
set_property PACKAGE_PIN U18 [get_ports io_clock];
create_clock -period 20.000 -name io_clock -waveform {0.000 10.000} -add [get_ports io_clock];
# LEDs
set_property IOSTANDARD LVCMOS33 [get_ports io_led];
set_property PACKAGE_PIN J16 [get_ports io_led]; # PL_LED0
#set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports io_led_1];
#set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports io_led_2];
# switches
set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports clk_enalbe]; # PL_SW1
# buttons
set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS33} [get_ports io_reset]; # PL_KEY0
# UART ports
# rxd assigned to constant 1
set_property IOSTANDARD LVCMOS33 [get_ports UART0_TX_0]
set_property PACKAGE_PIN J15 [get_ports UART0_TX_0]
set_property IOSTANDARD LVCMOS33 [get_ports UART0_RX_0]
set_property PACKAGE_PIN T19 [get_ports UART0_RX_0]