mirror of
https://github.com/handsomezhuzhu/2025-yatcpu.git
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3e3c8ba6c0
- now VCD is written in all tests by default, turn it on/off in TestAnnotations.scala - updated cmakelists.txt - added board program scripts and sources for Zynq 7000 v1.3 2024/02 board, lab1 only currently
30 lines
1.0 KiB
Tcl
30 lines
1.0 KiB
Tcl
## This file is for SYSU computer organization courses.
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## used for Zynq7010 fpga revision 1.3 2024/02
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# clock, 50 MHz
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set_property IOSTANDARD LVCMOS33 [get_ports io_clock];
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set_property PACKAGE_PIN U18 [get_ports io_clock];
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create_clock -period 20.000 -name io_clock -waveform {0.000 10.000} -add [get_ports io_clock];
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# LEDs
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set_property IOSTANDARD LVCMOS33 [get_ports io_led];
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set_property PACKAGE_PIN J16 [get_ports io_led]; # PL_LED0
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#set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports io_led_1];
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#set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports io_led_2];
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# switches
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set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports clk_enalbe]; # PL_SW1
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# buttons
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set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS33} [get_ports io_reset]; # PL_KEY0
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# UART ports
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# rxd assigned to constant 1
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set_property IOSTANDARD LVCMOS33 [get_ports UART0_TX_0]
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set_property PACKAGE_PIN J15 [get_ports UART0_TX_0]
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set_property IOSTANDARD LVCMOS33 [get_ports UART0_RX_0]
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set_property PACKAGE_PIN T19 [get_ports UART0_RX_0]
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