diff --git a/lab1/csrc/CMakeLists.txt b/lab1/csrc/CMakeLists.txt
index ee07b00..1605a1f 100644
--- a/lab1/csrc/CMakeLists.txt
+++ b/lab1/csrc/CMakeLists.txt
@@ -5,7 +5,7 @@ project(yatcpu-programs C CXX ASM)
 # Setting variables
 set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -O0 --target=riscv32-unknown-elf -march=rv32i -mabi=ilp32")
 set(CMAKE_ASM_FLAGS "${CMAKE_ASM_FLAGS} -O0 --target=riscv32-unknown-elf -march=rv32i -mabi=ilp32")
-set(C_PROGRAMS tetris hello fibonacci quicksort paging tetris_mmu)
+set(C_PROGRAMS tetris hello fibonacci quicksort paging tetris_mmu say_goodbye)
 set(ASM_PROGRAMS mmio sb)
 set(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/link.lds)
 set(LINKER_FLAGS -T ${LINKER_SCRIPT}) 
diff --git a/lab1/src/main/scala/board/z710v1.3/Top.scala b/lab1/src/main/scala/board/z710v1.3/Top.scala
new file mode 100644
index 0000000..8744371
--- /dev/null
+++ b/lab1/src/main/scala/board/z710v1.3/Top.scala
@@ -0,0 +1,114 @@
+// Copyright 2022 Canbin Huang
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package board.z710v1_3
+
+import chisel3._
+import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
+import chisel3.util.Cat
+import peripheral._
+import riscv.Parameters
+import riscv.core.{CPU, ProgramCounter}
+
+class Top(binaryFilename: String = "say_goodbye.asmbin") extends Module {
+  val io = IO(new Bundle() {
+    val tx = Output(Bool())
+    val rx = Input(Bool())
+
+    val led = Output(Bool())  // z710 has few LEDs, use one for running indicator
+  })
+
+  
+  val clock_freq = 50_000_000
+
+  val mem = Module(new Memory(Parameters.MemorySizeInWords))
+  // val hdmi_display = Module(new HDMIDisplay)
+  // val display = Module(new CharacterDisplay)
+  // val timer = Module(new Timer)
+  val uart = Module(new Uart(frequency = clock_freq, baudRate = 115200)) // 31M or 32M is good, 33M more error
+  val dummy = Module(new Dummy)
+
+  // display.io.bundle <> dummy.io.bundle
+  mem.io.bundle <> dummy.io.bundle
+  mem.io.debug_read_address := 0.U
+  // timer.io.bundle <> dummy.io.bundle
+  uart.io.bundle <> dummy.io.bundle
+  io.tx := uart.io.txd
+  uart.io.rxd := io.rx
+
+  val instruction_rom = Module(new InstructionROM(binaryFilename))
+  val rom_loader = Module(new ROMLoader(instruction_rom.capacity))
+
+  rom_loader.io.rom_data := instruction_rom.io.data
+  rom_loader.io.load_address := Parameters.EntryAddress
+  instruction_rom.io.address := rom_loader.io.rom_address
+
+  val CPU_clkdiv = RegInit(UInt(2.W),0.U)
+  val CPU_tick = Wire(Bool())
+  val CPU_next = Wire(UInt(2.W))
+  CPU_next := Mux(CPU_clkdiv === 3.U, 0.U, CPU_clkdiv + 1.U)
+  CPU_tick := CPU_clkdiv === 0.U
+  CPU_clkdiv := CPU_next
+
+  withClock(CPU_tick.asClock) {
+    val cpu = Module(new CPU)
+    // cpu.io.interrupt_flag := Cat(uart.io.signal_interrupt, timer.io.signal_interrupt)
+    // cpu.io.csr_regs_debug_read_address := 0.U
+    // cpu.io.regs_debug_read_address := 0.U
+    cpu.io.debug_read_address := 0.U
+    // cpu.io.memory_bundle.read_data := 0.U
+    cpu.io.instruction_valid := rom_loader.io.load_finished
+    mem.io.instruction_address := cpu.io.instruction_address
+    cpu.io.instruction := mem.io.instruction
+
+    when(!rom_loader.io.load_finished) {
+      rom_loader.io.bundle <> mem.io.bundle
+      cpu.io.memory_bundle.read_data := 0.U
+    }.otherwise {
+      rom_loader.io.bundle.read_data := 0.U
+      when(cpu.io.deviceSelect === 2.U) {
+        cpu.io.memory_bundle <> uart.io.bundle
+      }.otherwise {
+        cpu.io.memory_bundle <> mem.io.bundle
+      }
+    }
+
+    when(!rom_loader.io.load_finished) {
+      rom_loader.io.bundle <> mem.io.bundle
+      cpu.io.memory_bundle.read_data := 0.U
+    }.otherwise {
+      rom_loader.io.bundle.read_data := 0.U
+      cpu.io.memory_bundle <> mem.io.bundle
+    }
+  }
+
+  // LED, blinks every second
+  val led_count = RegInit(0.U(32.W))
+  when (led_count >= clock_freq.U) {
+    led_count := 0.U
+  }.otherwise {
+    led_count := led_count + 1.U
+  }
+  io.led := (led_count >= (clock_freq.U >> 1))
+
+
+
+}
+
+object VerilogGenerator extends App {
+  (new ChiselStage).execute(
+    Array("-X", "verilog", "-td", "verilog/z710v1.3"), 
+    Seq(ChiselGeneratorAnnotation(() => new Top("say_goodbye.asmbin")))   // program to run on CPU
+  )
+}
diff --git a/lab1/src/test/scala/riscv/BoardTest.scala b/lab1/src/test/scala/riscv/BoardTest.scala
index 40bd459..cbccc73 100644
--- a/lab1/src/test/scala/riscv/BoardTest.scala
+++ b/lab1/src/test/scala/riscv/BoardTest.scala
@@ -7,13 +7,13 @@ import chisel3._
 import chisel3.util.{is, switch}
 import chiseltest._
 import org.scalatest.flatspec.AnyFlatSpec
-import board.z710.Top
+import board.{z710, z710v1_3, verilator}
 
 
-class SayGoodbyeTest extends AnyFlatSpec with ChiselScalatestTester {
-  behavior of "Board simulation"
+class Z710_SayGoodbyeTest extends AnyFlatSpec with ChiselScalatestTester {
+  behavior of "Z710 Board simulation"
   it should "say goodbye " in {
-    test(new Top("say_goodbye.asmbin")).withAnnotations(TestAnnotations.annos) { c => 
+    test(new z710.Top("say_goodbye.asmbin")).withAnnotations(TestAnnotations.annos) { c => 
       
       for (i <- 1 to 50000) {
         c.clock.step(5)
@@ -23,3 +23,17 @@ class SayGoodbyeTest extends AnyFlatSpec with ChiselScalatestTester {
   }
 }
 
+class Z710v13_SayGoodbyeTest extends AnyFlatSpec with ChiselScalatestTester {
+  behavior of "Z710v1.3 Board simulation"
+  it should "say goodbye " in {
+    test(new z710v1_3.Top("say_goodbye.asmbin")).withAnnotations(TestAnnotations.annos) { c => 
+      
+      for (i <- 1 to 50000) {
+        c.clock.step(5)
+        c.io.rx.poke((i % 2).U) // poke some useless value, since rx not yet used
+      }  
+    }
+  }
+}
+
+
diff --git a/lab1/src/test/scala/riscv/TestAnnotations.scala b/lab1/src/test/scala/riscv/TestAnnotations.scala
index 1dca602..369d83a 100644
--- a/lab1/src/test/scala/riscv/TestAnnotations.scala
+++ b/lab1/src/test/scala/riscv/TestAnnotations.scala
@@ -48,5 +48,6 @@ object WriteVcdEnabler {
 }
 
 object TestAnnotations {
-  val annos = VerilatorEnabler.annos ++ WriteVcdEnabler.annos
+  // val annos = VerilatorEnabler.annos ++ WriteVcdEnabler.annos
+  val annos = Seq(VerilatorBackendAnnotation, WriteVcdAnnotation) // enable VCD write by default
 }
diff --git a/lab1/verilog/z710v1.3/clock_control.v b/lab1/verilog/z710v1.3/clock_control.v
new file mode 100644
index 0000000..39a734a
--- /dev/null
+++ b/lab1/verilog/z710v1.3/clock_control.v
@@ -0,0 +1,33 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2023/11/29 15:52:55
+// Design Name: 
+// Module Name: clock_control
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module clock_control(
+    input clk_in,
+    input clk_enalbe,
+    output clk_out
+    );
+    
+    
+    // original clock
+   assign clk_out = clk_in & clk_enalbe;
+    
+endmodule
diff --git a/lab1/verilog/z710v1.3/top_test.v b/lab1/verilog/z710v1.3/top_test.v
new file mode 100644
index 0000000..ea6d7a8
--- /dev/null
+++ b/lab1/verilog/z710v1.3/top_test.v
@@ -0,0 +1,47 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2023/12/01 15:46:54
+// Design Name: 
+// Module Name: top_test
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module top_test(
+
+    );
+    
+    reg clock;
+    reg reset;
+    reg constant_zero = 1'b0;
+    
+    wire io_led, io_tx;
+    
+    localparam CLK_PERIOD = 10;
+    initial begin
+        clock = 1'b0;
+        forever #( CLK_PERIOD / 2 ) clock = ~clock;
+    end
+    
+    
+    initial begin
+        reset = 1;  // need a down edge to init all components
+        #(CLK_PERIOD)  reset = 0;  // NOTE!!: must happen together with clock down edge!
+    end
+    
+    Top mytop(clock, reset, io_tx, constant_zero, io_led );
+    
+endmodule
diff --git a/lab1/vivado/z710v1.3/README.md b/lab1/vivado/z710v1.3/README.md
new file mode 100644
index 0000000..e69de29
diff --git a/lab1/vivado/z710v1.3/generate_bitstream.tcl b/lab1/vivado/z710v1.3/generate_bitstream.tcl
new file mode 100644
index 0000000..9d3564d
--- /dev/null
+++ b/lab1/vivado/z710v1.3/generate_bitstream.tcl
@@ -0,0 +1,66 @@
+# Copyright 2021 Howard Lau
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+
+# setup variables
+set project_dir "./rv-z710v1.3-20"
+set project_name "rv-z710v1.3-20"
+
+open_project $project_dir/$project_name.xpr
+
+while 1 {
+    if { [catch {launch_runs synth_1 -jobs 4 } ] } {
+        regexp {ERROR: \[Common (\d+-\d+)]} $errorInfo -> code
+        if { [string equal $code "12-978"] } {
+            puts "Already generated and up-to-date"
+            break
+        } elseif { [string equal $code "17-69"] } {
+            puts "Out of date, reset runs"
+            reset_runs synth_1
+            continue
+        } else {
+            puts "UNKNOWN ERROR!!! $errorInfo"
+            exit
+        }
+    }
+    break
+}
+
+wait_on_run synth_1
+
+while 1 {
+    if { [catch {launch_runs impl_1 -jobs 4 -to_step write_bitstream } ] } {
+        regexp {ERROR: \[Vivado (\d+-\d+)]} $errorInfo -> code
+        if { [string equal $code "12-978"] } {
+            puts "Already generated and up-to-date"
+            break
+        } elseif { [string equal $code "12-1088"] } {
+            puts "Out of date, reset runs"
+            reset_runs impl_1
+            continue
+        } else {
+            puts "UNKNOWN ERROR!!! $errorInfo"
+            exit
+        }
+    }
+    break
+}
+
+wait_on_run impl_1
+
+
+# export hardware platform to Vitis
+set_property pfm_name {} [get_files -all $project_dir/$project_name.srcs/sources_1/bd/design_1/design_1.bd]
+write_hw_platform -fixed -include_bit -force -file $project_dir/design_1_wrapper.xsa
+
diff --git a/lab1/vivado/z710v1.3/program_device.tcl b/lab1/vivado/z710v1.3/program_device.tcl
new file mode 100644
index 0000000..e1badd3
--- /dev/null
+++ b/lab1/vivado/z710v1.3/program_device.tcl
@@ -0,0 +1,24 @@
+# Copyright 2021 Howard Lau
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+
+open_hw_manager
+connect_hw_server -allow_non_jtag
+open_hw_target
+current_hw_device [get_hw_devices xc7z010_1]
+refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7z010_1] 0]
+set_property PROGRAM.FILE {./rv-z710v1.3-20/rv-z710v1.3-20.runs/impl_1/design_1_wrapper.bit} [get_hw_devices xc7z010_1]
+program_hw_devices [get_hw_devices xc7z010_1]
+refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
+close_hw_target
diff --git a/lab1/vivado/z710v1.3/rv-z710v1.3-20.tcl b/lab1/vivado/z710v1.3/rv-z710v1.3-20.tcl
new file mode 100644
index 0000000..ec60a68
--- /dev/null
+++ b/lab1/vivado/z710v1.3/rv-z710v1.3-20.tcl
@@ -0,0 +1,698 @@
+#*****************************************************************************************
+# Vivado (TM) v2020.1 (64-bit)
+#
+# rv-z710v1.3-20.tcl: Tcl script for re-creating project 'rv-z710v1.3-20'
+#
+# Generated by Vivado on Mon Nov 18 09:57:15 +0800 2024
+# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
+#
+# This file contains the Vivado Tcl commands for re-creating the project to the state*
+# when this script was generated. In order to re-create the project, please source this
+# file in the Vivado Tcl Shell.
+#
+# * Note that the runs in the created project will be configured the same way as the
+#   original project, however they will not be launched automatically. To regenerate the
+#   run results please launch the synthesis/implementation runs as needed.
+#
+#*****************************************************************************************
+# NOTE: In order to use this script for source control purposes, please make sure that the
+#       following files are added to the source control system:-
+#
+# 1. This project restoration tcl script (rv-z710v1.3-20.tcl) that was generated.
+#
+# 2. The following source(s) files that were local or imported into the original project.
+#    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
+#
+#    "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/vivado/z710v1.3/rv-z710v1.3-20/rv-z710v1.3-20.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v"
+#
+# 3. The following remote source files that were added to the original project:-
+#
+#    "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/verilog/z710v1.3/Top.v"
+#    "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/verilog/z710v1.3/clock_control.v"
+#    "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/vivado/z710v1.3/z710v1.3.xdc"
+#
+#*****************************************************************************************
+
+# Set the reference directory for source file relative paths (by default the value is script directory path)
+set origin_dir "."
+
+# Use origin directory path location variable, if specified in the tcl shell
+if { [info exists ::origin_dir_loc] } {
+  set origin_dir $::origin_dir_loc
+}
+
+# Set the project name
+set _xil_proj_name_ "rv-z710v1.3-20"
+
+# Use project name variable, if specified in the tcl shell
+if { [info exists ::user_project_name] } {
+  set _xil_proj_name_ $::user_project_name
+}
+
+variable script_file
+set script_file "rv-z710v1.3-20.tcl"
+
+# Help information for this script
+proc print_help {} {
+  variable script_file
+  puts "\nDescription:"
+  puts "Recreate a Vivado project from this script. The created project will be"
+  puts "functionally equivalent to the original project for which this script was"
+  puts "generated. The script contains commands for creating a project, filesets,"
+  puts "runs, adding/importing sources and setting properties on various objects.\n"
+  puts "Syntax:"
+  puts "$script_file"
+  puts "$script_file -tclargs \[--origin_dir <path>\]"
+  puts "$script_file -tclargs \[--project_name <name>\]"
+  puts "$script_file -tclargs \[--help\]\n"
+  puts "Usage:"
+  puts "Name                   Description"
+  puts "-------------------------------------------------------------------------"
+  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
+  puts "                       origin_dir path value is \".\", otherwise, the value"
+  puts "                       that was set with the \"-paths_relative_to\" switch"
+  puts "                       when this script was generated.\n"
+  puts "\[--project_name <name>\] Create project with the specified name. Default"
+  puts "                       name is the name of the project from where this"
+  puts "                       script was generated.\n"
+  puts "\[--help\]               Print help information for this script"
+  puts "-------------------------------------------------------------------------\n"
+  exit 0
+}
+
+if { $::argc > 0 } {
+  for {set i 0} {$i < $::argc} {incr i} {
+    set option [string trim [lindex $::argv $i]]
+    switch -regexp -- $option {
+      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
+      "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
+      "--help"         { print_help }
+      default {
+        if { [regexp {^-} $option] } {
+          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
+          return 1
+        }
+      }
+    }
+  }
+}
+
+# Set the directory path for the original project from where this script was exported
+set orig_proj_dir "[file normalize "$origin_dir/rv-z710v1.3-20"]"
+
+# Create project
+create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z010clg400-1
+
+# Set the directory path for the new project
+set proj_dir [get_property directory [current_project]]
+
+# Set project properties
+set obj [current_project]
+set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
+set_property -name "enable_vhdl_2008" -value "1" -objects $obj
+set_property -name "ip_cache_permissions" -value "read write" -objects $obj
+set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
+set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
+set_property -name "part" -value "xc7z010clg400-1" -objects $obj
+set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
+set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
+set_property -name "simulator_language" -value "Mixed" -objects $obj
+
+# Create 'sources_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sources_1] ""]} {
+  create_fileset -srcset sources_1
+}
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+set files [list \
+ [file normalize "${origin_dir}/../../verilog/z710v1.3/Top.v"] \
+ [file normalize "${origin_dir}/../../verilog/z710v1.3/clock_control.v"] \
+]
+add_files -norecurse -fileset $obj $files
+
+# Import local files from the original project
+# set files [list \
+#  [file normalize "${origin_dir}/rv-z710v1.3-20/rv-z710v1.3-20.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v" ]\
+# ]
+set imported_files [import_files -fileset sources_1 $files]
+
+# Set 'sources_1' fileset file properties for remote files
+# None
+
+# Set 'sources_1' fileset file properties for local files
+# None
+
+# Set 'sources_1' fileset properties
+set obj [get_filesets sources_1]
+set_property -name "top" -value "design_1_wrapper" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+# Create 'constrs_1' fileset (if not found)
+if {[string equal [get_filesets -quiet constrs_1] ""]} {
+  create_fileset -constrset constrs_1
+}
+
+# Set 'constrs_1' fileset object
+set obj [get_filesets constrs_1]
+
+# Add/Import constrs file and set constrs file properties
+set file "[file normalize "$origin_dir/z710v1.3.xdc"]"
+set file_added [add_files -norecurse -fileset $obj [list $file]]
+set file "$origin_dir/z710v1.3.xdc"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
+set_property -name "file_type" -value "XDC" -objects $file_obj
+
+# Set 'constrs_1' fileset properties
+set obj [get_filesets constrs_1]
+set_property -name "target_part" -value "xc7z010clg400-1" -objects $obj
+
+# Create 'sim_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sim_1] ""]} {
+  create_fileset -simset sim_1
+}
+
+# Set 'sim_1' fileset object
+set obj [get_filesets sim_1]
+# Empty (no sources present)
+
+# Set 'sim_1' fileset properties
+set obj [get_filesets sim_1]
+set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
+set_property -name "top" -value "Top" -objects $obj
+set_property -name "top_file" -value "../../verilog/z710v1.3/Top.v" -objects $obj
+set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
+
+# Set 'utils_1' fileset object
+set obj [get_filesets utils_1]
+# Empty (no sources present)
+
+# Set 'utils_1' fileset properties
+set obj [get_filesets utils_1]
+
+
+# Adding sources referenced in BDs, if not already added
+if { [get_files Top.v] == "" } {
+  import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710v1.3/Top.v"
+}
+if { [get_files clock_control.v] == "" } {
+  import_files -quiet -fileset sources_1 "${origin_dir}/../..//verilog/z710v1.3/clock_control.v"
+}
+
+
+# Proc to create BD design_1
+proc cr_bd_design_1 { parentCell } {
+# The design that will be created by this Tcl proc contains the following 
+# module references:
+# Top, clock_control
+
+
+
+  # CHANGE DESIGN NAME HERE
+  set design_name design_1
+
+  common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+  create_bd_design $design_name
+
+  set bCheckIPsPassed 1
+  ##################################################################
+  # CHECK IPs
+  ##################################################################
+  set bCheckIPs 1
+  if { $bCheckIPs == 1 } {
+     set list_check_ips "\ 
+  xilinx.com:ip:util_vector_logic:2.0\
+  "
+
+   set list_ips_missing ""
+   common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+  }
+
+  ##################################################################
+  # CHECK Modules
+  ##################################################################
+  set bCheckModules 1
+  if { $bCheckModules == 1 } {
+     set list_check_mods "\ 
+  Top\
+  clock_control\
+  "
+
+   set list_mods_missing ""
+   common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
+
+   foreach mod_vlnv $list_check_mods {
+      if { [can_resolve_reference $mod_vlnv] == 0 } {
+         lappend list_mods_missing $mod_vlnv
+      }
+   }
+
+   if { $list_mods_missing ne "" } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
+      common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
+      set bCheckIPsPassed 0
+   }
+}
+
+  if { $bCheckIPsPassed != 1 } {
+    common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+    return 3
+  }
+
+  variable script_folder
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+
+  # Create ports
+  set UART0_RX_0 [ create_bd_port -dir I UART0_RX_0 ]
+  set UART0_TX_0 [ create_bd_port -dir O -type data UART0_TX_0 ]
+  set clk_enalbe [ create_bd_port -dir I -type ce clk_enalbe ]
+  set io_clock [ create_bd_port -dir I -type clk -freq_hz 50000000 io_clock ]
+  set io_led [ create_bd_port -dir O io_led ]
+  set io_reset [ create_bd_port -dir I -type rst io_reset ]
+  set_property -dict [ list \
+   CONFIG.POLARITY {ACTIVE_HIGH} \
+ ] $io_reset
+
+  # Create instance: Top_0, and set properties
+  set block_name Top
+  set block_cell_name Top_0
+  if { [catch {set Top_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $Top_0 eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+  
+  # Create instance: clock_control_0, and set properties
+  set block_name clock_control
+  set block_cell_name clock_control_0
+  if { [catch {set clock_control_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $clock_control_0 eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+  
+  # Create instance: util_vector_logic_0, and set properties
+  set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
+  set_property -dict [ list \
+   CONFIG.C_OPERATION {not} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_notgate.png} \
+ ] $util_vector_logic_0
+
+  # Create port connections
+  connect_bd_net -net Top_0_io_led [get_bd_ports io_led] [get_bd_pins Top_0/io_led]
+  connect_bd_net -net Top_0_io_tx [get_bd_ports UART0_TX_0] [get_bd_pins Top_0/io_tx]
+  connect_bd_net -net UART0_RX_0_1 [get_bd_ports UART0_RX_0] [get_bd_pins Top_0/io_rx]
+  connect_bd_net -net clk_enalbe_1 [get_bd_ports clk_enalbe] [get_bd_pins clock_control_0/clk_enalbe]
+  connect_bd_net -net clock_control_0_clk_out [get_bd_pins Top_0/clock] [get_bd_pins clock_control_0/clk_out]
+  connect_bd_net -net io_clock_1 [get_bd_ports io_clock] [get_bd_pins clock_control_0/clk_in]
+  connect_bd_net -net io_reset_1 [get_bd_ports io_reset] [get_bd_pins util_vector_logic_0/Op1]
+  connect_bd_net -net util_vector_logic_0_Res [get_bd_pins Top_0/reset] [get_bd_pins util_vector_logic_0/Res]
+
+  # Create address segments
+
+  # Perform GUI Layout
+  regenerate_bd_layout -layout_string {
+   "ActiveEmotionalView":"Default View",
+   "Default View_ScaleFactor":"1.0",
+   "Default View_TopLeft":"-343,-119",
+   "ExpandedHierarchyInLayout":"",
+   "guistr":"# # String gsaved with Nlview 7.0r6  2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:9.0 non-TLS
+#  -string -flagsOSRD
+preplace port io_reset -pg 1 -lvl 0 -x 0 -y 180 -defaultsOSRD
+preplace port io_clock -pg 1 -lvl 0 -x 0 -y 60 -defaultsOSRD
+preplace port clk_enalbe -pg 1 -lvl 0 -x 0 -y 80 -defaultsOSRD
+preplace port UART0_RX_0 -pg 1 -lvl 0 -x 0 -y 240 -defaultsOSRD
+preplace port UART0_TX_0 -pg 1 -lvl 3 -x 540 -y 170 -defaultsOSRD
+preplace port io_led -pg 1 -lvl 3 -x 540 -y 190 -defaultsOSRD
+preplace inst Top_0 -pg 1 -lvl 2 -x 420 -y 180 -defaultsOSRD
+preplace inst util_vector_logic_0 -pg 1 -lvl 1 -x 170 -y 180 -defaultsOSRD
+preplace inst clock_control_0 -pg 1 -lvl 1 -x 170 -y 70 -defaultsOSRD
+preplace netloc io_reset_1 1 0 1 NJ 180
+preplace netloc util_vector_logic_0_Res 1 1 1 NJ 180
+preplace netloc io_clock_1 1 0 1 NJ 60
+preplace netloc clk_enalbe_1 1 0 1 NJ 80
+preplace netloc clock_control_0_clk_out 1 1 1 320 70n
+preplace netloc UART0_RX_0_1 1 0 2 NJ 240 320J
+preplace netloc Top_0_io_tx 1 2 1 NJ 170
+preplace netloc Top_0_io_led 1 2 1 NJ 190
+levelinfo -pg 1 0 170 420 540
+pagesize -pg 1 -db -bbox -sgen -140 0 680 260
+"
+}
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+  close_bd_design $design_name 
+}
+# End of cr_bd_design_1()
+
+cr_bd_design_1 ""
+set_property REGISTERED_WITH_MANAGER "1" [get_files design_1.bd ] 
+set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files design_1.bd ] 
+
+# create HDL wrapper
+set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse design_1.bd] -top]
+add_files -norecurse -fileset sources_1 $wrapper_path
+
+# Create 'synth_1' run (if not found)
+if {[string equal [get_runs -quiet synth_1] ""]} {
+    create_run -name synth_1 -part xc7z010clg400-1 -flow {Vivado Synthesis 2020} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
+} else {
+  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
+  set_property flow "Vivado Synthesis 2020" [get_runs synth_1]
+}
+set obj [get_runs synth_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Synthesis Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'synth_1_synth_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
+  create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
+}
+set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
+if { $obj != "" } {
+
+}
+set obj [get_runs synth_1]
+set_property -name "part" -value "xc7z010clg400-1" -objects $obj
+set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
+
+# set the current synth run
+current_run -synthesis [get_runs synth_1]
+
+# Create 'impl_1' run (if not found)
+if {[string equal [get_runs -quiet impl_1] ""]} {
+    create_run -name impl_1 -part xc7z010clg400-1 -flow {Vivado Implementation 2020} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
+} else {
+  set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+  set_property flow "Vivado Implementation 2020" [get_runs impl_1]
+}
+set obj [get_runs impl_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Implementation Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'impl_1_init_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_opt_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_place_report_io_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_control_sets_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
+if { $obj != "" } {
+set_property -name "options.verbose" -value "1" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_methodology_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_power_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_route_status_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+set obj [get_runs impl_1]
+set_property -name "part" -value "xc7z010clg400-1" -objects $obj
+set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
+set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
+
+# set the current impl run
+current_run -implementation [get_runs impl_1]
+
+puts "INFO: Project created:${_xil_proj_name_}"
+# Create 'drc_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "drc_1" ] ] ""]} {
+create_dashboard_gadget -name {drc_1} -type drc
+}
+set obj [get_dashboard_gadgets [ list "drc_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
+
+# Create 'methodology_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "methodology_1" ] ] ""]} {
+create_dashboard_gadget -name {methodology_1} -type methodology
+}
+set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
+
+# Create 'power_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "power_1" ] ] ""]} {
+create_dashboard_gadget -name {power_1} -type power
+}
+set obj [get_dashboard_gadgets [ list "power_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
+
+# Create 'timing_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "timing_1" ] ] ""]} {
+create_dashboard_gadget -name {timing_1} -type timing
+}
+set obj [get_dashboard_gadgets [ list "timing_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
+
+# Create 'utilization_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_1" ] ] ""]} {
+create_dashboard_gadget -name {utilization_1} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
+set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
+set_property -name "run.step" -value "synth_design" -objects $obj
+set_property -name "run.type" -value "synthesis" -objects $obj
+
+# Create 'utilization_2' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_2" ] ] ""]} {
+create_dashboard_gadget -name {utilization_2} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
+set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
+
+move_dashboard_gadget -name {utilization_1} -row 0 -col 0
+move_dashboard_gadget -name {power_1} -row 1 -col 0
+move_dashboard_gadget -name {drc_1} -row 2 -col 0
+move_dashboard_gadget -name {timing_1} -row 0 -col 1
+move_dashboard_gadget -name {utilization_2} -row 1 -col 1
+move_dashboard_gadget -name {methodology_1} -row 2 -col 1
diff --git a/lab1/vivado/z710v1.3/z710v1.3.xdc b/lab1/vivado/z710v1.3/z710v1.3.xdc
new file mode 100644
index 0000000..80c889e
--- /dev/null
+++ b/lab1/vivado/z710v1.3/z710v1.3.xdc
@@ -0,0 +1,29 @@
+## This file is for SYSU computer organization courses.
+## used for Zynq7010 fpga revision 1.3 2024/02
+
+
+
+# clock, 50 MHz
+set_property IOSTANDARD LVCMOS33 [get_ports io_clock];
+set_property PACKAGE_PIN U18 [get_ports io_clock];
+create_clock -period 20.000 -name io_clock -waveform {0.000 10.000} -add [get_ports io_clock];
+
+# LEDs
+set_property IOSTANDARD LVCMOS33 [get_ports io_led];
+set_property PACKAGE_PIN J16 [get_ports io_led];   # PL_LED0
+#set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports io_led_1];
+#set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports io_led_2];
+
+# switches
+set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports clk_enalbe]; # PL_SW1
+
+# buttons
+set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS33} [get_ports io_reset];  # PL_KEY0
+
+
+# UART ports
+# rxd assigned to constant 1
+set_property IOSTANDARD LVCMOS33 [get_ports UART0_TX_0]
+set_property PACKAGE_PIN J15 [get_ports UART0_TX_0]
+set_property IOSTANDARD LVCMOS33 [get_ports UART0_RX_0]
+set_property PACKAGE_PIN T19 [get_ports UART0_RX_0]
diff --git a/lab2/csrc/CMakeLists.txt b/lab2/csrc/CMakeLists.txt
index 0cf3160..122513a 100644
--- a/lab2/csrc/CMakeLists.txt
+++ b/lab2/csrc/CMakeLists.txt
@@ -5,7 +5,7 @@ project(yatcpu-programs C CXX ASM)
 # Setting variables
 set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -O0 --target=riscv32-unknown-elf -march=rv32i -mabi=ilp32")
 set(CMAKE_ASM_FLAGS "${CMAKE_ASM_FLAGS} -O0 --target=riscv32-unknown-elf -march=rv32i -mabi=ilp32")
-set(C_PROGRAMS tetris hello fibonacci quicksort paging tetris_mmu simpletest)
+set(C_PROGRAMS tetris hello fibonacci quicksort paging tetris_mmu simpletest say_goodbye)
 set(ASM_PROGRAMS mmio sb)
 set(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/link.lds)
 set(LINKER_FLAGS -T ${LINKER_SCRIPT}) 
diff --git a/lab2/src/test/scala/riscv/TestAnnotations.scala b/lab2/src/test/scala/riscv/TestAnnotations.scala
index 7842a95..ac658da 100644
--- a/lab2/src/test/scala/riscv/TestAnnotations.scala
+++ b/lab2/src/test/scala/riscv/TestAnnotations.scala
@@ -48,5 +48,6 @@ object WriteVcdEnabler {
 }
 
 object TestAnnotations {
-  val annos = VerilatorEnabler.annos ++ WriteVcdEnabler.annos
+  // val annos = VerilatorEnabler.annos ++ WriteVcdEnabler.annos
+  val annos = Seq(VerilatorBackendAnnotation, WriteVcdAnnotation) // enable VCD write by default
 }
diff --git a/lab3/csrc/CMakeLists.txt b/lab3/csrc/CMakeLists.txt
index 5512cea..df74f8b 100644
--- a/lab3/csrc/CMakeLists.txt
+++ b/lab3/csrc/CMakeLists.txt
@@ -5,7 +5,7 @@ project(yatcpu-programs C CXX ASM)
 # Setting variables
 set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -O0 --target=riscv32-unknown-elf -march=rv32i -mabi=ilp32")
 set(CMAKE_ASM_FLAGS "${CMAKE_ASM_FLAGS} -O0 --target=riscv32-unknown-elf -march=rv32i -mabi=ilp32")
-set(C_PROGRAMS tetris hello fibonacci quicksort paging tetris_mmu)
+set(C_PROGRAMS tetris hello fibonacci quicksort paging tetris_mmu say_goodbye)
 set(ASM_PROGRAMS mmio sb hazard)
 set(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/link.lds)
 set(LINKER_FLAGS -T ${LINKER_SCRIPT}) 
diff --git a/lab3/src/test/scala/riscv/TestAnnotations.scala b/lab3/src/test/scala/riscv/TestAnnotations.scala
index 7842a95..ac658da 100644
--- a/lab3/src/test/scala/riscv/TestAnnotations.scala
+++ b/lab3/src/test/scala/riscv/TestAnnotations.scala
@@ -48,5 +48,6 @@ object WriteVcdEnabler {
 }
 
 object TestAnnotations {
-  val annos = VerilatorEnabler.annos ++ WriteVcdEnabler.annos
+  // val annos = VerilatorEnabler.annos ++ WriteVcdEnabler.annos
+  val annos = Seq(VerilatorBackendAnnotation, WriteVcdAnnotation) // enable VCD write by default
 }
diff --git a/lab4/csrc/CMakeLists.txt b/lab4/csrc/CMakeLists.txt
index ee07b00..1605a1f 100644
--- a/lab4/csrc/CMakeLists.txt
+++ b/lab4/csrc/CMakeLists.txt
@@ -5,7 +5,7 @@ project(yatcpu-programs C CXX ASM)
 # Setting variables
 set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -O0 --target=riscv32-unknown-elf -march=rv32i -mabi=ilp32")
 set(CMAKE_ASM_FLAGS "${CMAKE_ASM_FLAGS} -O0 --target=riscv32-unknown-elf -march=rv32i -mabi=ilp32")
-set(C_PROGRAMS tetris hello fibonacci quicksort paging tetris_mmu)
+set(C_PROGRAMS tetris hello fibonacci quicksort paging tetris_mmu say_goodbye)
 set(ASM_PROGRAMS mmio sb)
 set(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/link.lds)
 set(LINKER_FLAGS -T ${LINKER_SCRIPT}) 
diff --git a/lab4/src/test/scala/riscv/TestAnnotations.scala b/lab4/src/test/scala/riscv/TestAnnotations.scala
index 7842a95..ac658da 100644
--- a/lab4/src/test/scala/riscv/TestAnnotations.scala
+++ b/lab4/src/test/scala/riscv/TestAnnotations.scala
@@ -48,5 +48,6 @@ object WriteVcdEnabler {
 }
 
 object TestAnnotations {
-  val annos = VerilatorEnabler.annos ++ WriteVcdEnabler.annos
+  // val annos = VerilatorEnabler.annos ++ WriteVcdEnabler.annos
+  val annos = Seq(VerilatorBackendAnnotation, WriteVcdAnnotation) // enable VCD write by default
 }
diff --git a/mini-yatcpu/src/test/scala/riscv/TestAnnotations.scala b/mini-yatcpu/src/test/scala/riscv/TestAnnotations.scala
index 7842a95..ac658da 100644
--- a/mini-yatcpu/src/test/scala/riscv/TestAnnotations.scala
+++ b/mini-yatcpu/src/test/scala/riscv/TestAnnotations.scala
@@ -48,5 +48,6 @@ object WriteVcdEnabler {
 }
 
 object TestAnnotations {
-  val annos = VerilatorEnabler.annos ++ WriteVcdEnabler.annos
+  // val annos = VerilatorEnabler.annos ++ WriteVcdEnabler.annos
+  val annos = Seq(VerilatorBackendAnnotation, WriteVcdAnnotation) // enable VCD write by default
 }