PurplePower 844cb062c2 Deleted useless verilog files

2023-12-26 01:18:54 +08:00

..

clock_control.v

added vivado-vitis uart workflow to lab3

2023-12-25 23:40:26 +08:00

top_test.v

add lab3 file

2023-12-12 22:24:33 +08:00