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https://github.com/handsomezhuzhu/2025-yatcpu.git
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47 lines
1009 B
Verilog
47 lines
1009 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2023/11/29 15:52:55
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// Design Name:
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// Module Name: clock_control
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module clock_control(
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input clk_in,
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input enable_clk,
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output clk_out
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);
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// if clock is divided
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localparam clk_div = 2; // clock is diveded by half of divisor
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reg [3:0] cnt = 4'd0;
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reg out = 1'b0;
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always @(posedge clk_in) begin
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cnt <= cnt + 4'd1;
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if (cnt >= (clk_div - 1)) begin
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out <= ~out;
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cnt <= 0;
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end
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end
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assign clk_out = out & enable_clk;
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// original clock
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// assign clk_out = clk_in & enable_clk;
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endmodule
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