mirror of
https://github.com/handsomezhuzhu/2025-yatcpu.git
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3e3c8ba6c0
- now VCD is written in all tests by default, turn it on/off in TestAnnotations.scala - updated cmakelists.txt - added board program scripts and sources for Zynq 7000 v1.3 2024/02 board, lab1 only currently
34 lines
652 B
Verilog
34 lines
652 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2023/11/29 15:52:55
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// Design Name:
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// Module Name: clock_control
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module clock_control(
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input clk_in,
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input clk_enalbe,
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output clk_out
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);
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// original clock
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assign clk_out = clk_in & clk_enalbe;
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endmodule
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