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Author SHA1 Message Date
PurplePower
c16529a4c5 Update mkdocs.yml 2025-09-27 01:20:31 +08:00
PurplePower
2554622d8a Move mkdocs.yml to project root and update paths 
Relocated mkdocs.yml from docs/ to the project root and updated all navigation paths.
 2025-09-27 01:20:31 +08:00
PurplePower
b6d4ddb90e Update mkdocs.yml 2025-09-27 01:20:31 +08:00
PurplePower
d203d58fb2 Update ci.yml 2025-09-27 01:20:31 +08:00
PurplePower
b76a6b89a4 Create ci.yml 2025-09-27 01:20:31 +08:00
PurplePower
3ab6723374 updated report questions for lab1 and lab2 2025-09-27 01:11:11 +08:00
PurplePower
1f43ccfcba added clock step for waveform in ID test 2025-09-27 00:03:50 +08:00
PurplePower
aaa87c1fdf lab4 tutorial updated and imported some docs from orginal YatCPU docs 2025-08-25 22:03:10 +08:00
PurplePower
bd3a38a3c1 fixes for lab3, passed verilator sim and all tests with correct cf prints 2025-08-15 00:57:34 +08:00
PurplePower
47c801d5d7 updated anchors and autofiller 2025-08-14 21:57:07 +08:00
PurplePower
c6ff02a058 some updates 2025-08-14 18:19:52 +08:00
PurplePower
b9865cd612 Lab3 pipelined CPU renewed 
- added tutorial
- fix ID reg addr invalid in certain types of instructions
- renamed some variables for better understanding
 2025-08-14 16:55:53 +08:00
PurplePower
110132ff95 Merge branch 'dev' into docs 
# Conflicts:
#	.gitignore
 2025-07-23 20:42:38 +08:00
PurplePower
dc3c42bec8 Updated arch graph for lab 1 and 2 2025-07-23 20:40:36 +08:00
PurplePower
1d03eb788a Updated .gitignore 2025-07-20 17:03:14 +08:00
PurplePower
3890e3a314 Added auto answer filler and updated anchors for lab2 2025-07-20 15:55:04 +08:00
PurplePower
2caaf3d9f5 [not tested] lab2 codes updated: 
- added environment instruction tests
- removed useless classes in CLINT.scala
- rename and comments
 2025-07-19 21:21:21 +08:00
PurplePower
fb2a030f07 Migrated and updated lab1 and lab2 tutorials, etc 
- update to two tutorials
- added environment and cmd tutorial
- updated lab1 CPU arch graph
 2025-07-19 20:58:44 +08:00
PurplePower
18c1327051 longer run time for fibonacci test 2024-11-20 18:15:40 +08:00
PurplePower
283eb09fd3 temp fix for lab2 on z710v1.3 board 2024-11-19 02:56:45 +08:00
PurplePower
b4141db235 updates 2024-11-19 02:09:45 +08:00
PurplePower
2b8e3eb45f updates 2024-11-19 02:00:32 +08:00
PurplePower
ea09ee5925 updated readmes and better printing 2024-11-19 01:47:50 +08:00
PurplePower
5c930b046c update clock_contrl.v for lab4 Z710 2024-11-19 01:29:05 +08:00
PurplePower
e4a4c6bf20 update clock_control.v for lab4 Z710 2024-11-19 01:17:53 +08:00
PurplePower
3abdb32f47 updates lab4 Top.scala for Z710v1.3 2024-11-19 01:11:30 +08:00
PurplePower
0f87b85f9f update Top.scala for z710v1.3 in lab3 and lab4 2024-11-19 00:50:11 +08:00
PurplePower
a64186bddb update z7-10 project scripts for other labs 2024-11-19 00:44:37 +08:00
PurplePower
8a3fae13fd updates 2024-11-19 00:25:58 +08:00
PurplePower
542c34ed46 updates Z7-10 for lab3 and lab4 2024-11-18 23:45:05 +08:00
PurplePower
0f905afe36 fixes 2024-11-18 23:17:58 +08:00
PurplePower
93ac859c8f update the Top.scala for Z710 2024-11-18 22:35:36 +08:00
PurplePower
ddb70fa967 Fixing Z710 frequency TNS too large 
- now Z7-10 vivado project no longer copy files to local folder, so vivado can auto update it in generate_bitstream.tcl
- Z7-10 clock freq is divided by 5 from 125MHz to 25MHz in clock_control.v
- adds Zynq7000 v1.3 for lab2
 2024-11-18 22:30:07 +08:00
PurplePower
28380be03b fixex typo in clock_control.v 2024-11-18 17:37:50 +08:00
PurplePower
eba44fe287 fixed script again 2024-11-18 17:26:27 +08:00
PurplePower
67896ab727 update csrc for correct UART printing with lower clock frequency 2024-11-18 17:06:23 +08:00
PurplePower
ad0aaa823f fixed problems in Vivado 2020 of reset input from button 2024-11-18 17:02:42 +08:00
PurplePower
3e3c8ba6c0 board updates and fixes 
- now VCD is written in all tests by default, turn it on/off in TestAnnotations.scala
- updated cmakelists.txt
- added board program scripts and sources for Zynq 7000 v1.3 2024/02 board, lab1 only currently
 2024-11-18 10:50:45 +08:00
PurplePower
358100ec57 fixed missing import in decoder test; adds bloop and auto-generated vivado projects to gitignore 2024-11-14 11:04:11 +08:00
PurplePower
4c36205a7f fixed the wrong assignment of uart output in lab1 z710 Top module 2024-11-14 10:14:53 +08:00
PurplePower
948b2e64f8 Added more tests for decoder 2024-11-07 22:38:53 +08:00
PurplePower
6866ae32ad Merge branch 'main' into dev 2024-10-22 00:58:09 +08:00
Tokisakix
1e4bfaac1b Update README.md 2024-09-09 11:26:50 +08:00
PurplePower
55aff2d301 Update Top.scala 2024-01-24 15:11:56 +08:00
PurplePower
b9294c0bd1 added c source files back 2024-01-23 21:35:09 +08:00
PurplePower
b3738b8f63 Updated z710 README and vitis script 
- skipped a redundant `paltform generate` in vitis_prj_run.tcl
- updated z710 README.md to be more detailed
 2024-01-19 15:40:51 +08:00
PurplePower
0a8f2ecffc updated readme for z710 board burning 2024-01-13 11:54:24 +08:00
PurplePower
8b505af0bf Merge branch 'main' into dev 2024-01-13 11:51:16 +08:00
PurplePower
ef4a567f22 Updated readme in z710 board burning 2024-01-13 11:34:17 +08:00
TOKISAKIX\21168
6271b88ca5 update test 2024-01-11 10:01:31 +08:00