Commit Graph

5 Commits

Author SHA1 Message Date
PurplePower
ddb70fa967 Fixing Z710 frequency TNS too large
- now Z7-10 vivado project no longer copy files to local folder, so vivado can auto update it in generate_bitstream.tcl
- Z7-10 clock freq is divided by 5 from 125MHz to 25MHz in clock_control.v
- adds Zynq7000 v1.3 for lab2
2024-11-18 22:30:07 +08:00
PurplePower
512d0d2b4c Update generate_bitstream.tcl
fixed tiny bug
2023-12-25 20:06:23 +08:00
PurplePower
85c4621957 updated vidado-vitis uart workflow scripts
Generated Top.v can be burnt to Z7-10 board with these scripts with Vivado 2020.1, versions above should be OK.

- vivado project now generates with just a single script
- vitis project now runs with a single script
2023-12-25 17:10:17 +08:00
PurplePower
bcd11625a6 Fixed generate bitstream bug
copy not rename so vivado GUI still finds the .bit file
2023-12-25 11:53:20 +08:00
TOKISAKIX\21168
d7c8c1b030 finished lab1 2023-12-12 22:14:02 +08:00