19 Commits

Author	SHA1	Message	Date
PurplePower	1f43ccfcba	added clock step for waveform in ID test	2025-09-27 00:03:50 +08:00
PurplePower	b9865cd612	Lab3 pipelined CPU renewed ... - added tutorial - fix ID reg addr invalid in certain types of instructions - renamed some variables for better understanding	2025-08-14 16:55:53 +08:00
PurplePower	ea09ee5925	updated readmes and better printing	2024-11-19 01:47:50 +08:00
PurplePower	8a3fae13fd	updates	2024-11-19 00:25:58 +08:00
PurplePower	0f905afe36	fixes	2024-11-18 23:17:58 +08:00
PurplePower	93ac859c8f	update the Top.scala for Z710	2024-11-18 22:35:36 +08:00
PurplePower	67896ab727	update csrc for correct UART printing with lower clock frequency	2024-11-18 17:06:23 +08:00
PurplePower	3e3c8ba6c0	board updates and fixes ... - now VCD is written in all tests by default, turn it on/off in TestAnnotations.scala - updated cmakelists.txt - added board program scripts and sources for Zynq 7000 v1.3 2024/02 board, lab1 only currently	2024-11-18 10:50:45 +08:00
PurplePower	358100ec57	fixed missing import in decoder test; adds bloop and auto-generated vivado projects to gitignore	2024-11-14 11:04:11 +08:00
PurplePower	4c36205a7f	fixed the wrong assignment of uart output in lab1 z710 Top module	2024-11-14 10:14:53 +08:00
PurplePower	948b2e64f8	Added more tests for decoder	2024-11-07 22:38:53 +08:00
PurplePower	55aff2d301	Update Top.scala	2024-01-24 15:11:56 +08:00
PurplePower	0a8f2ecffc	updated readme for z710 board burning	2024-01-13 11:54:24 +08:00
PurplePower	2a6899729b	Fixed Z7-10 generator duplicate file directory	2023-12-23 00:52:34 +08:00
TOKISAKIX\21168	d7c8c1b030	finished lab1	2023-12-12 22:14:02 +08:00
TOKISAKIX\21168	72cb1aa15d	add lab1 file	2023-12-12 21:26:29 +08:00
TOKISAKIX\21168	2bce97ff4e	add file	2023-12-11 22:20:48 +08:00
TOKISAKIX\21168	e720a0dfc2	add csrc	2023-12-11 21:54:53 +08:00
TOKISAKIX\21168	910ee11168	init repo	2023-12-11 21:50:22 +08:00