- now Z7-10 vivado project no longer copy files to local folder, so vivado can auto update it in generate_bitstream.tcl
- Z7-10 clock freq is divided by 5 from 125MHz to 25MHz in clock_control.v
- adds Zynq7000 v1.3 for lab2
- now VCD is written in all tests by default, turn it on/off in TestAnnotations.scala
- updated cmakelists.txt
- added board program scripts and sources for Zynq 7000 v1.3 2024/02 board, lab1 only currently
Generated Top.v can be burnt to Z7-10 board with these scripts with Vivado 2020.1, versions above should be OK.
- vivado project now generates with just a single script
- vitis project now runs with a single script