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vivado-vitis uart workflow added for lab2
This commit is contained in:
PurplePower
@@ -48,6 +48,10 @@ xsct ./vitis_prj_run.tcl
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该段描述这些脚本如何获得，若您希望了解其中原理或做出贡献，可以阅读本节。
|
该段描述这些脚本如何获得，若您希望了解其中原理或做出贡献，可以阅读本节。
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### Lab1 auxiliary file related
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lab1 中的 `clock_control.v` 进行4分频，避免生成方案 Worst Negative Slack 超标：因为仍是单周期 CPU，单时钟时间过短导致电路来不及产生结果。
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### Use with Vivado 2020.1
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### Use with Vivado 2020.1
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#### Vivado 项目重建脚本
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#### Vivado 项目重建脚本
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99
lab2/vivado/z710/README.md
Normal file
99
lab2/vivado/z710/README.md
Normal file
@@ -0,0 +1,99 @@
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# 如何使用脚本使 CPU 烧录至 Zybo Z7-10 开发板并读取 UART 输出至电脑
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步骤如下：
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此处用 `vivado` 和 `xsct` 工具，并假设您已在 `vivado/z710` 目录下打开终端。（TODO）
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## 1. 生成 Vivado 项目
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确保您的 `verilog/z710` 下已生成 Top.v ，且其他组件的 verilog 文件都存在。
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执行命令以生成设计：
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```pwsh
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vivado -mode batch -source ./riscv-z710-v2020.tcl
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```
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完成后，您应见文件夹 `vivado/z710/riscv-z710-v2020`，且其中有 `riscv-z710-v2020.xpr`。
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## 2. 生成比特流并导出硬件平台
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完成上一步骤后，执行命令以生成比特流、导出硬件平台 .xsa 文件。
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```pwsh
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vivado -mode batch -source ./generate_bitstream.tcl
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```
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完成后，您应见 `vivado\z710\riscv-z710-v2020\design_1_wrapper.xsa` 文件。
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## 3. 构建 Vitis 项目并烧录至开发板
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完成上一步骤后，将开发板连接至电脑，并开启电源。随后执行命令将 CPU 烧录至开发板，并使 Zynq 处理器监听并返回 UART 输出：
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```pwsh
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xsct ./vitis_prj_run.tcl
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```
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若成功，您应看到开发板的 LD0 灯在打开其下方的 G15 开关（该开关控制输入CPU的时钟开关）时会闪烁，同时右侧 BTN16 上方的 LD12 已烧录指示灯亮起为绿色。
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打开任意的 COM 通信工具，连接至合适串口，即可收到 CPU 的输出 UART 信息，按 BTN0 （K18）会重置 CPU 以重新打印。
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## For Maintainers
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该段描述这些脚本如何获得，若您希望了解其中原理或做出贡献，可以阅读本节。
|
||||||
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### lab2 auxiliary file related
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CPU 输入频率4分频。
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### Use with Vivado 2020.1
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#### Vivado 项目重建脚本
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2020 版本的 Vivado 导出仍会引用 .bd 块设计文件（2022不会），即使勾选了用 TCL 重建块设计。从 Vivado 2022 版那里导出的脚本薅来一段代码让它不必引用 .bd 文件，从而单个文件就能重建项目。
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用 Vivado 2020 的 Write Project Tcl 导出脚本后，开头会提示需要的文件，包括了块设计的 `design_1_wrapper.v`，但里面其实已经有 TCL 连线。
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1. 在 `Set 'sources_1' fileset object` （Line 128）附近删除添加 `design_1_wrapper.v` 的一行
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2. 在注释`End of cr_bd_design_1()` 后，运行完 `cr_bd_design_ ""` 之后（Line 870），添加生成 wrapper Verilog 文件的指令，如下
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```tcl
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...
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# End of cr_bd_design_1()
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cr_bd_design_1 ""
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set_property REGISTERED_WITH_MANAGER "1" [get_files design_1.bd ]
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set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files design_1.bd ]
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# 加在这： call make_wrapper to create wrapper files
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set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse design_1.bd] -top]
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add_files -norecurse -fileset sources_1 $wrapper_path
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```
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修改后上述脚本就能重建项目。
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`open_project.tcl` 直接打开项目的 .xpr 项目文件，`generate_bitstream.tcl` 再生成比特流，并额外导出硬件平台。
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#### Vitis 项目重建脚本
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Vitis 仅在控制台的 Platform 控制台打印一些对硬件平台的操作指令，其他指令需要参照 XSCT（Xilinx Software Commandline Tool） 参考手册，以使用相关指令（纯苦工活）。一些流程在 Vitis IDE 里面的设置可以找到，比如 PS7 处理器的初始化流程（在脚本注释有写）。
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XSCT 会单独使用一个 cmd 窗口执行，因此如果中途因错误退出将来不及看到任何错误信息，因此需要在命令行打开 xsct（如 `E:\Xilinx\Vitis\2020.1\bin\xsct`），然后逐行执行（多行的 if 结构可一次性复制多行），并查看错误。
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注意 Vivado 和 Vitis 版本要一致，不要混用不同年份的版本。
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***
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### Use with Vivado 2022.1
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#### Vivado 项目重建脚本
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导（出）就完啦！
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||||||
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#### Vitis 项目重建脚本
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应该和 2020 的一样。
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@@ -1,17 +0,0 @@
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# Copyright 2021 Howard Lau
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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||||||
# You may obtain a copy of the License at
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||||||
#
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||||||
# http://www.apache.org/licenses/LICENSE-2.0
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||||||
#
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||||||
# Unless required by applicable law or agreed to in writing, software
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||||||
# distributed under the License is distributed on an "AS IS" BASIS,
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||||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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||||||
# See the License for the specific language governing permissions and
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||||||
# limitations under the License.
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||||||
# Only tested on Vivado 2020.1 on Windows 10
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source generate_bitstream.tcl
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source program_device.tcl
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@@ -54,8 +54,8 @@ while 1 {
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wait_on_run impl_1
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wait_on_run impl_1
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# copy the bitstream so vivado GUI still finds it
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file copy riscv-z710/riscv-z710.runs/impl_1/design_1_wrapper.bit riscv-z710/riscv-z710.runs/impl_1/Top.bit
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# this will export platform .xsz
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# export hardware platform to Vitis
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write_hw_platform -fixed -include_bit -force -file ./riscv-z710/Top.xsa
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set_property pfm_name {} [get_files -all $project_dir/$project_name.srcs/sources_1/bd/design_1/design_1.bd]
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write_hw_platform -fixed -include_bit -force -file $project_dir/design_1_wrapper.xsa
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@@ -1,33 +1,8 @@
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# Copyright 2021 Howard Lau
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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||||||
#
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||||||
# http://www.apache.org/licenses/LICENSE-2.0
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||||||
#
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||||||
# Unless required by applicable law or agreed to in writing, software
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||||||
# distributed under the License is distributed on an "AS IS" BASIS,
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|
||||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
# See the License for the specific language governing permissions and
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|
||||||
# limitations under the License.
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||||||
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||||||
# Only tested on Vivado 2020.1 on Windows 10
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# setup variables
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||||||
|
set project_dir "./riscv-z710-v2020"
|
||||||
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set project_name "riscv-z710-v2020"
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||||||
# set variables
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||||||
set project_dir riscv-z710
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||||||
set project_name riscv-z710
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||||||
set part xc7z010clg400-1
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||||||
set sources {../../verilog/z710/Top.v ../../verilog/z710/clock_control.v ../../verilog/z710/pass_through.v ../../verilog/z710/Top_reset.v ../../verilog/z710/uart_control.v}
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||||||
set test_sources {../../verilog/z710/test.v ../../verilog/z710/top_test.v}
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||||||
# open the project. will create one if it doesn't exist
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open_project $project_dir/$project_name.xpr
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if {[file exist $project_dir]} {
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||||||
# check that it's a directory
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||||||
if {! [file isdirectory $project_dir]} {
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||||||
puts "$project_dir exists, but it's a file"
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|
||||||
}
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||||||
open_project $project_dir/$project_name.xpr -part $part
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||||||
} else {
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||||||
source riscv-z710.tcl
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|
||||||
}
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||||||
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@@ -1,24 +0,0 @@
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# Copyright 2021 Howard Lau
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#
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|
||||||
# Licensed under the Apache License, Version 2.0 (the "License");
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|
||||||
# you may not use this file except in compliance with the License.
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|
||||||
# You may obtain a copy of the License at
|
|
||||||
#
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|
||||||
# http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
#
|
|
||||||
# Unless required by applicable law or agreed to in writing, software
|
|
||||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
# See the License for the specific language governing permissions and
|
|
||||||
# limitations under the License.
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|
||||||
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|
||||||
# Only tested on Vivado 2020.1 on Windows 10
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|
||||||
open_hw_manager
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connect_hw_server -allow_non_jtag
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open_hw_target
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current_hw_device [get_hw_devices xc7z010_1]
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refresh_hw_server [current_hw_server]
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open_hw_target [lindex [get_hw_targets] 0]
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|
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set_property PROGRAM.FILE {./riscv-z710/riscv-z710.runs/impl_1/Top.bit} [get_hw_devices xc7z010_1]
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program_hw_devices [get_hw_devices xc7z010_1]
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|
||||||
close_hw_target
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|
||||||
1170
lab2/vivado/z710/riscv-z710-v2020.tcl
Normal file
1170
lab2/vivado/z710/riscv-z710-v2020.tcl
Normal file
File diff suppressed because it is too large
Load Diff
Binary file not shown.
@@ -1,459 +0,0 @@
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{
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"design": {
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|
||||||
"design_info": {
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|
||||||
"boundary_crc": "0xD2682A7282870375",
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|
||||||
"device": "xc7z010clg400-1",
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|
||||||
"name": "design_1",
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|
||||||
"rev_ctrl_bd_flag": "RevCtrlBdOff",
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|
||||||
"synth_flow_mode": "Hierarchical",
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|
||||||
"tool_version": "2020.1",
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|
||||||
"validated": "true"
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|
||||||
},
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|
||||||
"design_tree": {
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|
||||||
"processing_system7_0": "",
|
|
||||||
"clock_control_0": "",
|
|
||||||
"xlconstant_0": "",
|
|
||||||
"Top_0": ""
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|
||||||
},
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|
||||||
"interface_ports": {
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|
||||||
"DDR": {
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|
||||||
"mode": "Master",
|
|
||||||
"vlnv": "xilinx.com:interface:ddrx_rtl:1.0",
|
|
||||||
"parameters": {
|
|
||||||
"CAN_DEBUG": {
|
|
||||||
"value": "false",
|
|
||||||
"value_src": "default"
|
|
||||||
},
|
|
||||||
"TIMEPERIOD_PS": {
|
|
||||||
"value": "1250",
|
|
||||||
"value_src": "default"
|
|
||||||
},
|
|
||||||
"MEMORY_TYPE": {
|
|
||||||
"value": "COMPONENTS",
|
|
||||||
"value_src": "default"
|
|
||||||
},
|
|
||||||
"DATA_WIDTH": {
|
|
||||||
"value": "8",
|
|
||||||
"value_src": "default"
|
|
||||||
},
|
|
||||||
"CS_ENABLED": {
|
|
||||||
"value": "true",
|
|
||||||
"value_src": "default"
|
|
||||||
},
|
|
||||||
"DATA_MASK_ENABLED": {
|
|
||||||
"value": "true",
|
|
||||||
"value_src": "default"
|
|
||||||
},
|
|
||||||
"SLOT": {
|
|
||||||
"value": "Single",
|
|
||||||
"value_src": "default"
|
|
||||||
},
|
|
||||||
"MEM_ADDR_MAP": {
|
|
||||||
"value": "ROW_COLUMN_BANK",
|
|
||||||
"value_src": "default"
|
|
||||||
},
|
|
||||||
"BURST_LENGTH": {
|
|
||||||
"value": "8",
|
|
||||||
"value_src": "default"
|
|
||||||
},
|
|
||||||
"AXI_ARBITRATION_SCHEME": {
|
|
||||||
"value": "TDM",
|
|
||||||
"value_src": "default"
|
|
||||||
},
|
|
||||||
"CAS_LATENCY": {
|
|
||||||
"value": "11",
|
|
||||||
"value_src": "default"
|
|
||||||
},
|
|
||||||
"CAS_WRITE_LATENCY": {
|
|
||||||
"value": "11",
|
|
||||||
"value_src": "default"
|
|
||||||
}
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"FIXED_IO": {
|
|
||||||
"mode": "Master",
|
|
||||||
"vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0",
|
|
||||||
"parameters": {
|
|
||||||
"CAN_DEBUG": {
|
|
||||||
"value": "false",
|
|
||||||
"value_src": "default"
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"ports": {
|
|
||||||
"io_clock": {
|
|
||||||
"type": "clk",
|
|
||||||
"direction": "I",
|
|
||||||
"parameters": {
|
|
||||||
"CLK_DOMAIN": {
|
|
||||||
"value": "design_1_clock",
|
|
||||||
"value_src": "default"
|
|
||||||
},
|
|
||||||
"FREQ_HZ": {
|
|
||||||
"value": "100000000"
|
|
||||||
},
|
|
||||||
"FREQ_TOLERANCE_HZ": {
|
|
||||||
"value": "0",
|
|
||||||
"value_src": "default"
|
|
||||||
},
|
|
||||||
"INSERT_VIP": {
|
|
||||||
"value": "0",
|
|
||||||
"value_src": "default"
|
|
||||||
},
|
|
||||||
"PHASE": {
|
|
||||||
"value": "0.000",
|
|
||||||
"value_src": "default"
|
|
||||||
}
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"io_alive_led": {
|
|
||||||
"direction": "O"
|
|
||||||
},
|
|
||||||
"io_reset": {
|
|
||||||
"direction": "I",
|
|
||||||
"parameters": {
|
|
||||||
"POLARITY": {
|
|
||||||
"value": "",
|
|
||||||
"value_src": "weak"
|
|
||||||
}
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"enable_clk": {
|
|
||||||
"type": "clk",
|
|
||||||
"direction": "I",
|
|
||||||
"parameters": {
|
|
||||||
"CLK_DOMAIN": {
|
|
||||||
"value": "design_1_enable_clk_0",
|
|
||||||
"value_src": "default"
|
|
||||||
},
|
|
||||||
"FREQ_HZ": {
|
|
||||||
"value": "100000000",
|
|
||||||
"value_src": "default"
|
|
||||||
},
|
|
||||||
"FREQ_TOLERANCE_HZ": {
|
|
||||||
"value": "0",
|
|
||||||
"value_src": "default"
|
|
||||||
},
|
|
||||||
"INSERT_VIP": {
|
|
||||||
"value": "0",
|
|
||||||
"value_src": "default"
|
|
||||||
},
|
|
||||||
"PHASE": {
|
|
||||||
"value": "0.000",
|
|
||||||
"value_src": "default"
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"components": {
|
|
||||||
"processing_system7_0": {
|
|
||||||
"vlnv": "xilinx.com:ip:processing_system7:5.5",
|
|
||||||
"xci_name": "design_1_processing_system7_0_0",
|
|
||||||
"parameters": {
|
|
||||||
"PCW_ACT_APU_PERIPHERAL_FREQMHZ": {
|
|
||||||
"value": "666.666687"
|
|
||||||
},
|
|
||||||
"PCW_ACT_CAN_PERIPHERAL_FREQMHZ": {
|
|
||||||
"value": "10.000000"
|
|
||||||
},
|
|
||||||
"PCW_ACT_DCI_PERIPHERAL_FREQMHZ": {
|
|
||||||
"value": "10.158730"
|
|
||||||
},
|
|
||||||
"PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": {
|
|
||||||
"value": "10.000000"
|
|
||||||
},
|
|
||||||
"PCW_ACT_ENET1_PERIPHERAL_FREQMHZ": {
|
|
||||||
"value": "10.000000"
|
|
||||||
},
|
|
||||||
"PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": {
|
|
||||||
"value": "50.000000"
|
|
||||||
},
|
|
||||||
"PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": {
|
|
||||||
"value": "10.000000"
|
|
||||||
},
|
|
||||||
"PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": {
|
|
||||||
"value": "10.000000"
|
|
||||||
},
|
|
||||||
"PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": {
|
|
||||||
"value": "10.000000"
|
|
||||||
},
|
|
||||||
"PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": {
|
|
||||||
"value": "200.000000"
|
|
||||||
},
|
|
||||||
"PCW_ACT_QSPI_PERIPHERAL_FREQMHZ": {
|
|
||||||
"value": "10.000000"
|
|
||||||
},
|
|
||||||
"PCW_ACT_SDIO_PERIPHERAL_FREQMHZ": {
|
|
||||||
"value": "10.000000"
|
|
||||||
},
|
|
||||||
"PCW_ACT_SMC_PERIPHERAL_FREQMHZ": {
|
|
||||||
"value": "10.000000"
|
|
||||||
},
|
|
||||||
"PCW_ACT_SPI_PERIPHERAL_FREQMHZ": {
|
|
||||||
"value": "10.000000"
|
|
||||||
},
|
|
||||||
"PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": {
|
|
||||||
"value": "200.000000"
|
|
||||||
},
|
|
||||||
"PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": {
|
|
||||||
"value": "111.111115"
|
|
||||||
},
|
|
||||||
"PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": {
|
|
||||||
"value": "111.111115"
|
|
||||||
},
|
|
||||||
"PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": {
|
|
||||||
"value": "111.111115"
|
|
||||||
},
|
|
||||||
"PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": {
|
|
||||||
"value": "111.111115"
|
|
||||||
},
|
|
||||||
"PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": {
|
|
||||||
"value": "111.111115"
|
|
||||||
},
|
|
||||||
"PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": {
|
|
||||||
"value": "111.111115"
|
|
||||||
},
|
|
||||||
"PCW_ACT_UART_PERIPHERAL_FREQMHZ": {
|
|
||||||
"value": "100.000000"
|
|
||||||
},
|
|
||||||
"PCW_ACT_WDT_PERIPHERAL_FREQMHZ": {
|
|
||||||
"value": "111.111115"
|
|
||||||
},
|
|
||||||
"PCW_CLK0_FREQ": {
|
|
||||||
"value": "50000000"
|
|
||||||
},
|
|
||||||
"PCW_CLK1_FREQ": {
|
|
||||||
"value": "10000000"
|
|
||||||
},
|
|
||||||
"PCW_CLK2_FREQ": {
|
|
||||||
"value": "10000000"
|
|
||||||
},
|
|
||||||
"PCW_CLK3_FREQ": {
|
|
||||||
"value": "10000000"
|
|
||||||
},
|
|
||||||
"PCW_DDR_RAM_HIGHADDR": {
|
|
||||||
"value": "0x1FFFFFFF"
|
|
||||||
},
|
|
||||||
"PCW_EN_EMIO_UART0": {
|
|
||||||
"value": "1"
|
|
||||||
},
|
|
||||||
"PCW_EN_UART0": {
|
|
||||||
"value": "1"
|
|
||||||
},
|
|
||||||
"PCW_EN_UART1": {
|
|
||||||
"value": "1"
|
|
||||||
},
|
|
||||||
"PCW_FPGA_FCLK0_ENABLE": {
|
|
||||||
"value": "1"
|
|
||||||
},
|
|
||||||
"PCW_MIO_48_IOTYPE": {
|
|
||||||
"value": "LVCMOS 3.3V"
|
|
||||||
},
|
|
||||||
"PCW_MIO_48_PULLUP": {
|
|
||||||
"value": "enabled"
|
|
||||||
},
|
|
||||||
"PCW_MIO_48_SLEW": {
|
|
||||||
"value": "slow"
|
|
||||||
},
|
|
||||||
"PCW_MIO_49_IOTYPE": {
|
|
||||||
"value": "LVCMOS 3.3V"
|
|
||||||
},
|
|
||||||
"PCW_MIO_49_PULLUP": {
|
|
||||||
"value": "enabled"
|
|
||||||
},
|
|
||||||
"PCW_MIO_49_SLEW": {
|
|
||||||
"value": "slow"
|
|
||||||
},
|
|
||||||
"PCW_MIO_TREE_PERIPHERALS": {
|
|
||||||
"value": "unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 1#UART 1#unassigned#unassigned#unassigned#unassigned"
|
|
||||||
},
|
|
||||||
"PCW_MIO_TREE_SIGNALS": {
|
|
||||||
"value": "unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#tx#rx#unassigned#unassigned#unassigned#unassigned"
|
|
||||||
},
|
|
||||||
"PCW_UART0_GRP_FULL_ENABLE": {
|
|
||||||
"value": "0"
|
|
||||||
},
|
|
||||||
"PCW_UART0_PERIPHERAL_ENABLE": {
|
|
||||||
"value": "1"
|
|
||||||
},
|
|
||||||
"PCW_UART0_UART0_IO": {
|
|
||||||
"value": "EMIO"
|
|
||||||
},
|
|
||||||
"PCW_UART1_GRP_FULL_ENABLE": {
|
|
||||||
"value": "0"
|
|
||||||
},
|
|
||||||
"PCW_UART1_PERIPHERAL_ENABLE": {
|
|
||||||
"value": "1"
|
|
||||||
},
|
|
||||||
"PCW_UART1_UART1_IO": {
|
|
||||||
"value": "MIO 48 .. 49"
|
|
||||||
},
|
|
||||||
"PCW_UART_PERIPHERAL_FREQMHZ": {
|
|
||||||
"value": "100"
|
|
||||||
},
|
|
||||||
"PCW_UART_PERIPHERAL_VALID": {
|
|
||||||
"value": "1"
|
|
||||||
},
|
|
||||||
"PCW_UIPARAM_ACT_DDR_FREQ_MHZ": {
|
|
||||||
"value": "533.333374"
|
|
||||||
},
|
|
||||||
"PCW_USE_M_AXI_GP0": {
|
|
||||||
"value": "0"
|
|
||||||
}
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"clock_control_0": {
|
|
||||||
"vlnv": "xilinx.com:module_ref:clock_control:1.0",
|
|
||||||
"xci_name": "design_1_clock_control_0_0",
|
|
||||||
"reference_info": {
|
|
||||||
"ref_type": "hdl",
|
|
||||||
"ref_name": "clock_control",
|
|
||||||
"boundary_crc": "0x0"
|
|
||||||
},
|
|
||||||
"ports": {
|
|
||||||
"clk_in": {
|
|
||||||
"direction": "I",
|
|
||||||
"parameters": {
|
|
||||||
"CLK_DOMAIN": {
|
|
||||||
"value": "design_1_clock",
|
|
||||||
"value_src": "default_prop"
|
|
||||||
},
|
|
||||||
"FREQ_HZ": {
|
|
||||||
"value": "100000000",
|
|
||||||
"value_src": "user_prop"
|
|
||||||
},
|
|
||||||
"PHASE": {
|
|
||||||
"value": "0.000",
|
|
||||||
"value_src": "default_prop"
|
|
||||||
}
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"enable_clk": {
|
|
||||||
"type": "clk",
|
|
||||||
"direction": "I",
|
|
||||||
"parameters": {
|
|
||||||
"CLK_DOMAIN": {
|
|
||||||
"value": "design_1_enable_clk_0",
|
|
||||||
"value_src": "default_prop"
|
|
||||||
}
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"clk_out": {
|
|
||||||
"direction": "O",
|
|
||||||
"parameters": {
|
|
||||||
"CLK_DOMAIN": {
|
|
||||||
"value": "",
|
|
||||||
"value_src": "weak"
|
|
||||||
},
|
|
||||||
"FREQ_HZ": {
|
|
||||||
"value": "",
|
|
||||||
"value_src": "weak"
|
|
||||||
},
|
|
||||||
"PHASE": {
|
|
||||||
"value": "",
|
|
||||||
"value_src": "weak"
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"xlconstant_0": {
|
|
||||||
"vlnv": "xilinx.com:ip:xlconstant:1.1",
|
|
||||||
"xci_name": "design_1_xlconstant_0_0"
|
|
||||||
},
|
|
||||||
"Top_0": {
|
|
||||||
"vlnv": "xilinx.com:module_ref:Top:1.0",
|
|
||||||
"xci_name": "design_1_Top_0_0",
|
|
||||||
"reference_info": {
|
|
||||||
"ref_type": "hdl",
|
|
||||||
"ref_name": "Top",
|
|
||||||
"boundary_crc": "0x0"
|
|
||||||
},
|
|
||||||
"ports": {
|
|
||||||
"clock": {
|
|
||||||
"type": "clk",
|
|
||||||
"direction": "I",
|
|
||||||
"parameters": {
|
|
||||||
"ASSOCIATED_RESET": {
|
|
||||||
"value": "reset",
|
|
||||||
"value_src": "constant"
|
|
||||||
}
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"reset": {
|
|
||||||
"type": "rst",
|
|
||||||
"direction": "I"
|
|
||||||
},
|
|
||||||
"io_tx": {
|
|
||||||
"direction": "O"
|
|
||||||
},
|
|
||||||
"io_rx": {
|
|
||||||
"direction": "I"
|
|
||||||
},
|
|
||||||
"io_led": {
|
|
||||||
"direction": "O"
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"interface_nets": {
|
|
||||||
"processing_system7_0_FIXED_IO": {
|
|
||||||
"interface_ports": [
|
|
||||||
"FIXED_IO",
|
|
||||||
"processing_system7_0/FIXED_IO"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
"processing_system7_0_DDR": {
|
|
||||||
"interface_ports": [
|
|
||||||
"DDR",
|
|
||||||
"processing_system7_0/DDR"
|
|
||||||
]
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"nets": {
|
|
||||||
"Top_0_io_tx": {
|
|
||||||
"ports": [
|
|
||||||
"Top_0/io_tx",
|
|
||||||
"processing_system7_0/UART0_RX"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
"Top_0_io_led": {
|
|
||||||
"ports": [
|
|
||||||
"Top_0/io_led",
|
|
||||||
"io_alive_led"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
"io_reset_1": {
|
|
||||||
"ports": [
|
|
||||||
"io_reset",
|
|
||||||
"Top_0/reset"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
"io_clock_1": {
|
|
||||||
"ports": [
|
|
||||||
"io_clock",
|
|
||||||
"clock_control_0/clk_in"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
"enable_clk_0_1": {
|
|
||||||
"ports": [
|
|
||||||
"enable_clk",
|
|
||||||
"clock_control_0/enable_clk"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
"clock_control_0_clk_out": {
|
|
||||||
"ports": [
|
|
||||||
"clock_control_0/clk_out",
|
|
||||||
"Top_0/clock"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
"xlconstant_0_dout": {
|
|
||||||
"ports": [
|
|
||||||
"xlconstant_0/dout",
|
|
||||||
"Top_0/io_rx"
|
|
||||||
]
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@@ -1,116 +0,0 @@
|
|||||||
//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
|
|
||||||
//--------------------------------------------------------------------------------
|
|
||||||
//Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
|
|
||||||
//Date : Tue Dec 12 00:14:50 2023
|
|
||||||
//Host : Tokisakix running 64-bit major release (build 9200)
|
|
||||||
//Command : generate_target design_1_wrapper.bd
|
|
||||||
//Design : design_1_wrapper
|
|
||||||
//Purpose : IP block netlist
|
|
||||||
//--------------------------------------------------------------------------------
|
|
||||||
`timescale 1 ps / 1 ps
|
|
||||||
|
|
||||||
module design_1_wrapper
|
|
||||||
(DDR_addr,
|
|
||||||
DDR_ba,
|
|
||||||
DDR_cas_n,
|
|
||||||
DDR_ck_n,
|
|
||||||
DDR_ck_p,
|
|
||||||
DDR_cke,
|
|
||||||
DDR_cs_n,
|
|
||||||
DDR_dm,
|
|
||||||
DDR_dq,
|
|
||||||
DDR_dqs_n,
|
|
||||||
DDR_dqs_p,
|
|
||||||
DDR_odt,
|
|
||||||
DDR_ras_n,
|
|
||||||
DDR_reset_n,
|
|
||||||
DDR_we_n,
|
|
||||||
FIXED_IO_ddr_vrn,
|
|
||||||
FIXED_IO_ddr_vrp,
|
|
||||||
FIXED_IO_mio,
|
|
||||||
FIXED_IO_ps_clk,
|
|
||||||
FIXED_IO_ps_porb,
|
|
||||||
FIXED_IO_ps_srstb,
|
|
||||||
enable_clk,
|
|
||||||
io_alive_led,
|
|
||||||
io_clock,
|
|
||||||
io_reset);
|
|
||||||
inout [14:0]DDR_addr;
|
|
||||||
inout [2:0]DDR_ba;
|
|
||||||
inout DDR_cas_n;
|
|
||||||
inout DDR_ck_n;
|
|
||||||
inout DDR_ck_p;
|
|
||||||
inout DDR_cke;
|
|
||||||
inout DDR_cs_n;
|
|
||||||
inout [3:0]DDR_dm;
|
|
||||||
inout [31:0]DDR_dq;
|
|
||||||
inout [3:0]DDR_dqs_n;
|
|
||||||
inout [3:0]DDR_dqs_p;
|
|
||||||
inout DDR_odt;
|
|
||||||
inout DDR_ras_n;
|
|
||||||
inout DDR_reset_n;
|
|
||||||
inout DDR_we_n;
|
|
||||||
inout FIXED_IO_ddr_vrn;
|
|
||||||
inout FIXED_IO_ddr_vrp;
|
|
||||||
inout [53:0]FIXED_IO_mio;
|
|
||||||
inout FIXED_IO_ps_clk;
|
|
||||||
inout FIXED_IO_ps_porb;
|
|
||||||
inout FIXED_IO_ps_srstb;
|
|
||||||
input enable_clk;
|
|
||||||
output io_alive_led;
|
|
||||||
input io_clock;
|
|
||||||
input io_reset;
|
|
||||||
|
|
||||||
wire [14:0]DDR_addr;
|
|
||||||
wire [2:0]DDR_ba;
|
|
||||||
wire DDR_cas_n;
|
|
||||||
wire DDR_ck_n;
|
|
||||||
wire DDR_ck_p;
|
|
||||||
wire DDR_cke;
|
|
||||||
wire DDR_cs_n;
|
|
||||||
wire [3:0]DDR_dm;
|
|
||||||
wire [31:0]DDR_dq;
|
|
||||||
wire [3:0]DDR_dqs_n;
|
|
||||||
wire [3:0]DDR_dqs_p;
|
|
||||||
wire DDR_odt;
|
|
||||||
wire DDR_ras_n;
|
|
||||||
wire DDR_reset_n;
|
|
||||||
wire DDR_we_n;
|
|
||||||
wire FIXED_IO_ddr_vrn;
|
|
||||||
wire FIXED_IO_ddr_vrp;
|
|
||||||
wire [53:0]FIXED_IO_mio;
|
|
||||||
wire FIXED_IO_ps_clk;
|
|
||||||
wire FIXED_IO_ps_porb;
|
|
||||||
wire FIXED_IO_ps_srstb;
|
|
||||||
wire enable_clk;
|
|
||||||
wire io_alive_led;
|
|
||||||
wire io_clock;
|
|
||||||
wire io_reset;
|
|
||||||
|
|
||||||
design_1 design_1_i
|
|
||||||
(.DDR_addr(DDR_addr),
|
|
||||||
.DDR_ba(DDR_ba),
|
|
||||||
.DDR_cas_n(DDR_cas_n),
|
|
||||||
.DDR_ck_n(DDR_ck_n),
|
|
||||||
.DDR_ck_p(DDR_ck_p),
|
|
||||||
.DDR_cke(DDR_cke),
|
|
||||||
.DDR_cs_n(DDR_cs_n),
|
|
||||||
.DDR_dm(DDR_dm),
|
|
||||||
.DDR_dq(DDR_dq),
|
|
||||||
.DDR_dqs_n(DDR_dqs_n),
|
|
||||||
.DDR_dqs_p(DDR_dqs_p),
|
|
||||||
.DDR_odt(DDR_odt),
|
|
||||||
.DDR_ras_n(DDR_ras_n),
|
|
||||||
.DDR_reset_n(DDR_reset_n),
|
|
||||||
.DDR_we_n(DDR_we_n),
|
|
||||||
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
|
|
||||||
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
|
|
||||||
.FIXED_IO_mio(FIXED_IO_mio),
|
|
||||||
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
|
|
||||||
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
|
|
||||||
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
|
|
||||||
.enable_clk(enable_clk),
|
|
||||||
.io_alive_led(io_alive_led),
|
|
||||||
.io_clock(io_clock),
|
|
||||||
.io_reset(io_reset));
|
|
||||||
endmodule
|
|
||||||
@@ -1,376 +0,0 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
|
||||||
<!-- Product Version: Vivado v2020.1 (64-bit) -->
|
|
||||||
<!-- -->
|
|
||||||
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
|
|
||||||
|
|
||||||
<Project Version="7" Minor="49" Path="C:/Users/21168/Desktop/2023-fall-yatcpu-repo/lab2/vivado/z710/riscv-z710/riscv-z710.xpr">
|
|
||||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
|
||||||
<Configuration>
|
|
||||||
<Option Name="Id" Val="668831b5ccb743abb1dad41da490586a"/>
|
|
||||||
<Option Name="Part" Val="xc7z010clg400-1"/>
|
|
||||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
|
||||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
|
||||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
|
||||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
|
||||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
|
||||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
|
||||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
|
||||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
|
||||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
|
||||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
|
||||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
|
||||||
<Option Name="SimulatorInstallDirIES" Val=""/>
|
|
||||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
|
||||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
|
||||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
|
||||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
|
||||||
<Option Name="BoardPart" Val=""/>
|
|
||||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
|
||||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
|
||||||
<Option Name="ProjectType" Val="Default"/>
|
|
||||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
|
||||||
<Option Name="IPDefaultOutputPath" Val="$PSRCDIR/sources_1"/>
|
|
||||||
<Option Name="IPCachePermission" Val="read"/>
|
|
||||||
<Option Name="IPCachePermission" Val="write"/>
|
|
||||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
|
||||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
|
||||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
|
||||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
|
||||||
<Option Name="EnableBDX" Val="FALSE"/>
|
|
||||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTXSimExportSim" Val="0"/>
|
|
||||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
|
||||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
|
||||||
<Option Name="WTIesExportSim" Val="0"/>
|
|
||||||
<Option Name="WTVcsExportSim" Val="0"/>
|
|
||||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
|
||||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
|
||||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
|
||||||
<Option Name="XSimRadix" Val="hex"/>
|
|
||||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
|
||||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
|
||||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
|
||||||
<Option Name="SimTypes" Val="rtl"/>
|
|
||||||
<Option Name="SimTypes" Val="bfm"/>
|
|
||||||
<Option Name="SimTypes" Val="tlm"/>
|
|
||||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
|
||||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
|
||||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
|
||||||
</Configuration>
|
|
||||||
<FileSets Version="1" Minor="31">
|
|
||||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
|
||||||
<Filter Type="Srcs"/>
|
|
||||||
<File Path="$PPRDIR/../../../../lab4/verilog/z710/clock_control.v">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PPRDIR/../../../verilog/z710/Top.v">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci">
|
|
||||||
<Proxy FileSetName="design_1_processing_system7_0_0"/>
|
|
||||||
</CompFileExtendedInfo>
|
|
||||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_clock_control_0_0/design_1_clock_control_0_0.xci">
|
|
||||||
<Proxy FileSetName="design_1_clock_control_0_0"/>
|
|
||||||
</CompFileExtendedInfo>
|
|
||||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_Top_0_0/design_1_Top_0_0.xci">
|
|
||||||
<Proxy FileSetName="design_1_Top_0_0"/>
|
|
||||||
</CompFileExtendedInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PSRCDIR/sources_1/bd/design_1/hdl/design_1_wrapper.v">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PPRDIR/../../../../lab4/verilog/z710/Top_reset.v">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="AutoDisabled" Val="1"/>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PPRDIR/../../../../lab4/verilog/z710/pass_through.v">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="AutoDisabled" Val="1"/>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PPRDIR/../../../../lab4/verilog/z710/uart_control.v">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="AutoDisabled" Val="1"/>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<Config>
|
|
||||||
<Option Name="DesignMode" Val="RTL"/>
|
|
||||||
<Option Name="TopModule" Val="design_1_wrapper"/>
|
|
||||||
</Config>
|
|
||||||
</FileSet>
|
|
||||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
|
||||||
<Filter Type="Constrs"/>
|
|
||||||
<File Path="$PPRDIR/../z710.xdc">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<Config>
|
|
||||||
<Option Name="ConstrsType" Val="XDC"/>
|
|
||||||
</Config>
|
|
||||||
</FileSet>
|
|
||||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
|
||||||
<Filter Type="Srcs"/>
|
|
||||||
<File Path="$PPRDIR/../../../../lab4/verilog/z710/test.v">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="AutoDisabled" Val="1"/>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PPRDIR/../../../../lab4/verilog/z710/top_test.v">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="AutoDisabled" Val="1"/>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<Config>
|
|
||||||
<Option Name="DesignMode" Val="RTL"/>
|
|
||||||
<Option Name="TopModule" Val="design_1_wrapper"/>
|
|
||||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
|
||||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
|
||||||
<Option Name="TransportPathDelay" Val="0"/>
|
|
||||||
<Option Name="TransportIntDelay" Val="0"/>
|
|
||||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
|
||||||
<Option Name="PamDesignTestbench" Val=""/>
|
|
||||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
|
||||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
|
||||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
|
||||||
<Option Name="SrcSet" Val="sources_1"/>
|
|
||||||
</Config>
|
|
||||||
</FileSet>
|
|
||||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
|
||||||
<Filter Type="Utils"/>
|
|
||||||
<Config>
|
|
||||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
|
||||||
</Config>
|
|
||||||
</FileSet>
|
|
||||||
<FileSet Name="design_1_processing_system7_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_processing_system7_0_0">
|
|
||||||
<Config>
|
|
||||||
<Option Name="TopModule" Val="design_1_processing_system7_0_0"/>
|
|
||||||
<Option Name="UseBlackboxStub" Val="1"/>
|
|
||||||
</Config>
|
|
||||||
</FileSet>
|
|
||||||
<FileSet Name="design_1_clock_control_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_clock_control_0_0">
|
|
||||||
<Config>
|
|
||||||
<Option Name="TopModule" Val="design_1_clock_control_0_0"/>
|
|
||||||
<Option Name="UseBlackboxStub" Val="1"/>
|
|
||||||
</Config>
|
|
||||||
</FileSet>
|
|
||||||
<FileSet Name="design_1_Top_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_Top_0_0">
|
|
||||||
<Config>
|
|
||||||
<Option Name="TopModule" Val="design_1_Top_0_0"/>
|
|
||||||
<Option Name="UseBlackboxStub" Val="1"/>
|
|
||||||
</Config>
|
|
||||||
</FileSet>
|
|
||||||
</FileSets>
|
|
||||||
<Simulators>
|
|
||||||
<Simulator Name="XSim">
|
|
||||||
<Option Name="Description" Val="Vivado Simulator"/>
|
|
||||||
<Option Name="CompiledLib" Val="0"/>
|
|
||||||
</Simulator>
|
|
||||||
<Simulator Name="ModelSim">
|
|
||||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
|
||||||
</Simulator>
|
|
||||||
<Simulator Name="Questa">
|
|
||||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
|
||||||
</Simulator>
|
|
||||||
<Simulator Name="Riviera">
|
|
||||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
|
||||||
</Simulator>
|
|
||||||
<Simulator Name="ActiveHDL">
|
|
||||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
|
||||||
</Simulator>
|
|
||||||
</Simulators>
|
|
||||||
<Runs Version="1" Minor="11">
|
|
||||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
|
|
||||||
<Step Id="synth_design"/>
|
|
||||||
</Strategy>
|
|
||||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
||||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
<Run Id="design_1_processing_system7_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_processing_system7_0_0" Part="xc7z010clg400-1" ConstrsSet="design_1_processing_system7_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_processing_system7_0_0_synth_1" IncludeInArchive="true">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
|
|
||||||
<Desc>Vivado Synthesis Defaults</Desc>
|
|
||||||
</StratHandle>
|
|
||||||
<Step Id="synth_design"/>
|
|
||||||
</Strategy>
|
|
||||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
||||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
<Run Id="design_1_clock_control_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_clock_control_0_0" Part="xc7z010clg400-1" ConstrsSet="design_1_clock_control_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_clock_control_0_0_synth_1" IncludeInArchive="true">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
|
|
||||||
<Desc>Vivado Synthesis Defaults</Desc>
|
|
||||||
</StratHandle>
|
|
||||||
<Step Id="synth_design"/>
|
|
||||||
</Strategy>
|
|
||||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
||||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
<Run Id="design_1_Top_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_Top_0_0" Part="xc7z010clg400-1" ConstrsSet="design_1_Top_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_Top_0_0_synth_1" IncludeInArchive="true">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
|
|
||||||
<Desc>Vivado Synthesis Defaults</Desc>
|
|
||||||
</StratHandle>
|
|
||||||
<Step Id="synth_design"/>
|
|
||||||
</Strategy>
|
|
||||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
||||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
|
||||||
<Step Id="init_design"/>
|
|
||||||
<Step Id="opt_design"/>
|
|
||||||
<Step Id="power_opt_design"/>
|
|
||||||
<Step Id="place_design"/>
|
|
||||||
<Step Id="post_place_power_opt_design"/>
|
|
||||||
<Step Id="phys_opt_design"/>
|
|
||||||
<Step Id="route_design"/>
|
|
||||||
<Step Id="post_route_phys_opt_design"/>
|
|
||||||
<Step Id="write_bitstream"/>
|
|
||||||
</Strategy>
|
|
||||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
|
||||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
<Run Id="design_1_processing_system7_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_processing_system7_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_processing_system7_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
|
|
||||||
<Desc>Default settings for Implementation.</Desc>
|
|
||||||
</StratHandle>
|
|
||||||
<Step Id="init_design"/>
|
|
||||||
<Step Id="opt_design"/>
|
|
||||||
<Step Id="power_opt_design"/>
|
|
||||||
<Step Id="place_design"/>
|
|
||||||
<Step Id="post_place_power_opt_design"/>
|
|
||||||
<Step Id="phys_opt_design"/>
|
|
||||||
<Step Id="route_design"/>
|
|
||||||
<Step Id="post_route_phys_opt_design"/>
|
|
||||||
<Step Id="write_bitstream"/>
|
|
||||||
</Strategy>
|
|
||||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
<Run Id="design_1_clock_control_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_clock_control_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_clock_control_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
|
|
||||||
<Desc>Default settings for Implementation.</Desc>
|
|
||||||
</StratHandle>
|
|
||||||
<Step Id="init_design"/>
|
|
||||||
<Step Id="opt_design"/>
|
|
||||||
<Step Id="power_opt_design"/>
|
|
||||||
<Step Id="place_design"/>
|
|
||||||
<Step Id="post_place_power_opt_design"/>
|
|
||||||
<Step Id="phys_opt_design"/>
|
|
||||||
<Step Id="route_design"/>
|
|
||||||
<Step Id="post_route_phys_opt_design"/>
|
|
||||||
<Step Id="write_bitstream"/>
|
|
||||||
</Strategy>
|
|
||||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
<Run Id="design_1_Top_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_Top_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_Top_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
|
|
||||||
<Desc>Default settings for Implementation.</Desc>
|
|
||||||
</StratHandle>
|
|
||||||
<Step Id="init_design"/>
|
|
||||||
<Step Id="opt_design"/>
|
|
||||||
<Step Id="power_opt_design"/>
|
|
||||||
<Step Id="place_design"/>
|
|
||||||
<Step Id="post_place_power_opt_design"/>
|
|
||||||
<Step Id="phys_opt_design"/>
|
|
||||||
<Step Id="route_design"/>
|
|
||||||
<Step Id="post_route_phys_opt_design"/>
|
|
||||||
<Step Id="write_bitstream"/>
|
|
||||||
</Strategy>
|
|
||||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
</Runs>
|
|
||||||
<Board/>
|
|
||||||
<DashboardSummary Version="1" Minor="0">
|
|
||||||
<Dashboards>
|
|
||||||
<Dashboard Name="default_dashboard">
|
|
||||||
<Gadgets>
|
|
||||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
|
||||||
</Gadget>
|
|
||||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
|
||||||
</Gadget>
|
|
||||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
|
||||||
</Gadget>
|
|
||||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
|
||||||
</Gadget>
|
|
||||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
|
||||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
|
||||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
|
||||||
</Gadget>
|
|
||||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
|
||||||
</Gadget>
|
|
||||||
</Gadgets>
|
|
||||||
</Dashboard>
|
|
||||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
|
||||||
</Dashboards>
|
|
||||||
</DashboardSummary>
|
|
||||||
</Project>
|
|
||||||
83
lab2/vivado/z710/vitis_prj_run.tcl
Normal file
83
lab2/vivado/z710/vitis_prj_run.tcl
Normal file
@@ -0,0 +1,83 @@
|
|||||||
|
|
||||||
|
set vivado_ws "./riscv-z710-v2020"
|
||||||
|
set vitis_ws "./hello_z710-test"
|
||||||
|
set vitis_prj_name "hello_z710"
|
||||||
|
set hardware_name "design_1_wrapper"
|
||||||
|
|
||||||
|
# set vitis workspace, ASSUMES you run this script in vivado/z710/
|
||||||
|
setws $vitis_ws
|
||||||
|
|
||||||
|
|
||||||
|
# create or activate hardware platform, then configure
|
||||||
|
|
||||||
|
if {[file exists $vitis_ws/$hardware_name/platform.spr]} {
|
||||||
|
puts "Found platform file, updating it"
|
||||||
|
platform read $vitis_ws/$hardware_name/platform.spr
|
||||||
|
platform active $hardware_name
|
||||||
|
platform config -updatehw $vivado_ws/$hardware_name.xsa
|
||||||
|
} else {
|
||||||
|
puts "Creating platform from $vivado_ws/$hardware_name.xsa, make sure you have this file"
|
||||||
|
|
||||||
|
# leave out "-out $vitis_ws" option for vitis 2020, which causes `platform list` found nothing, but still in the same place
|
||||||
|
platform create -name $hardware_name -hw $vivado_ws/$hardware_name.xsa -proc {ps7_cortexa9_0} -os {standalone}
|
||||||
|
platform write
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
platform active $hardware_name
|
||||||
|
|
||||||
|
bsp config stdout ps7_uart_1
|
||||||
|
bsp config stdin ps7_uart_1
|
||||||
|
|
||||||
|
platform write
|
||||||
|
platform generate
|
||||||
|
|
||||||
|
|
||||||
|
if {![file exists $vitis_ws/$vitis_prj_name]} {
|
||||||
|
# create app project, using current active platform
|
||||||
|
# app create -name $vitis_prj_name -proc {ps7_cortexa9_0} -os {standalone} -lang C -template {Hello World}
|
||||||
|
app create -name $vitis_prj_name -platform $hardware_name -lang C -template {Hello World}
|
||||||
|
|
||||||
|
# overwrite existing helloworld.c
|
||||||
|
file copy -force helloworld.c $vitis_ws/$vitis_prj_name/src/helloworld.c
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
# build the project
|
||||||
|
app build -name $vitis_prj_name
|
||||||
|
|
||||||
|
# connect to default hw server @ 3121 and select target as ARM core 0
|
||||||
|
# connect -host localhost -port 3121
|
||||||
|
|
||||||
|
# connect alone can start hw_server and connect to it
|
||||||
|
connect
|
||||||
|
targets -set -nocase -filter {name =~ "ARM*#0"}
|
||||||
|
|
||||||
|
# system reset
|
||||||
|
rst -system
|
||||||
|
|
||||||
|
# PS7 initialization, these steps are from Vitis IDE - Debug configuration(right click) - target setup
|
||||||
|
# $hardware_name/hw/ps7_init.tcl is the same. init and post config are performed to enable PL-PS interaction
|
||||||
|
#
|
||||||
|
# Following operations will be performed before launching the debugger.
|
||||||
|
# 1. Resets entire system. Clears the FPGA fabric (PL).
|
||||||
|
# 2. Program FPGA fabric (PL).
|
||||||
|
# 3. Runs ps7_init to initialize PS.
|
||||||
|
# 4. Runs ps7_post_config. Enables level shifters from PL to PS. (Recommended to use this option only after system reset or board power ON).
|
||||||
|
# 5. All processors in the system will be suspended, and Applications will be downloaded to the following processors as specified in the Applications tab.
|
||||||
|
# 1) ps7_cortexa9_0 (E:\Workplace\2022-fall-yatcpu-repo\lab1\vivado\z710\hello-z710-v2020\hello_z710\Debug\hello_z710.elf)
|
||||||
|
namespace eval xsdb "source $vitis_ws/$vitis_prj_name/_ide/psinit/ps7_init.tcl;ps7_init;ps7_post_config"
|
||||||
|
|
||||||
|
# burn our CPU on FPGA
|
||||||
|
fpga $vitis_ws/$hardware_name/hw/$hardware_name.bit
|
||||||
|
|
||||||
|
# download ELF to PS
|
||||||
|
dow $vitis_ws/$vitis_prj_name/Debug/$vitis_prj_name.elf
|
||||||
|
|
||||||
|
|
||||||
|
# insert breakpoint at main
|
||||||
|
# bpadd -addr &main
|
||||||
|
|
||||||
|
con
|
||||||
|
|
||||||
|
con
|
||||||
Reference in New Issue
Block a user