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vivado-vitis uart workflow added for lab2

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PurplePower
2023-12-25 20:50:54 +08:00
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lab1/vivado/z710/README.md
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@@ -48,6 +48,10 @@ xsct ./vitis_prj_run.tcl
该段描述这些脚本如何获得，若您希望了解其中原理或做出贡献，可以阅读本节。
### Lab1 auxiliary file related
lab1 中的 `clock_control.v` 进行4分频，避免生成方案 Worst Negative Slack 超标：因为仍是单周期 CPU，单时钟时间过短导致电路来不及产生结果。
### Use with Vivado 2020.1
#### Vivado 项目重建脚本