lab2还有一个报错防止改错

lab2/src/main/scala/peripheral/Timer.scala

@@ -34,5 +34,27 @@ class Timer extends Module {
   io.debug_enabled := enabled
 
   //lab2(CLINTCSR)
-  //finish the read-write for count,limit,enabled. And produce appropriate signal_interrupt
+  val address = io.bundle.address
+  io.bundle.read_data := 0.U
+  when(address === 0x4.U) {
+    io.bundle.read_data := limit
+  }.elsewhen(address === 0x8.U) {
+    io.bundle.read_data := enabled
+  }
+
+  when(io.bundle.write_enable) {
+    when(address === 0x4.U) {
+      limit := io.bundle.write_data
+    }.elsewhen(address === 0x8.U) {
+      enabled := io.bundle.write_data(0)
+    }
+  }
+
+  when(enabled && count >= limit) {
+    io.signal_interrupt := true.B
+    count := 0.U
+  }.otherwise {
+    io.signal_interrupt := false.B
+    count := count + 1.U
+  }
 }