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https://github.com/handsomezhuzhu/2025-yatcpu.git
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61 lines
1.6 KiB
Scala
61 lines
1.6 KiB
Scala
// Copyright 2021 Howard Lau
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package peripheral
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import chisel3._
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import chisel3.util._
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import riscv.Parameters
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class Timer extends Module {
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val io = IO(new Bundle {
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val bundle = new RAMBundle
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val signal_interrupt = Output(Bool())
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val debug_limit = Output(UInt(Parameters.DataWidth))
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val debug_enabled = Output(Bool())
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})
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val count = RegInit(0.U(32.W))
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val limit = RegInit(100000000.U(32.W))
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io.debug_limit := limit
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val enabled = RegInit(true.B)
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io.debug_enabled := enabled
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//lab2(CLINTCSR)
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val address = io.bundle.address
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io.bundle.read_data := 0.U
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when(address === 0x4.U) {
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io.bundle.read_data := limit
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}.elsewhen(address === 0x8.U) {
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io.bundle.read_data := enabled
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}
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when(io.bundle.write_enable) {
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when(address === 0x4.U) {
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limit := io.bundle.write_data
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}.elsewhen(address === 0x8.U) {
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enabled := io.bundle.write_data(0)
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}
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}
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when(enabled && count >= limit) {
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io.signal_interrupt := true.B
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count := 0.U
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}.otherwise {
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io.signal_interrupt := false.B
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count := count + 1.U
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}
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}
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