Fixing Z710 frequency TNS too large

- now Z7-10 vivado project no longer copy files to local folder, so vivado can auto update it in generate_bitstream.tcl
- Z7-10 clock freq is divided by 5 from 125MHz to 25MHz in clock_control.v
- adds Zynq7000 v1.3 for lab2

lab2/verilog/z710v1.3/clock_control.v

@@ -0,0 +1,33 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2023/11/29 15:52:55
+// Design Name: 
+// Module Name: clock_control
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module clock_control(
+    input clk_in,
+    input clk_enable,
+    output clk_out
+    );
+    
+    
+    // original clock
+   assign clk_out = clk_in & clk_enable;
+    
+endmodule