From ddb70fa96720c2708f0fc09394cad0a5602dcca3 Mon Sep 17 00:00:00 2001 From: PurplePower <60787289+PurplePower@users.noreply.github.com> Date: Mon, 18 Nov 2024 22:30:07 +0800 Subject: [PATCH] Fixing Z710 frequency TNS too large - now Z7-10 vivado project no longer copy files to local folder, so vivado can auto update it in generate_bitstream.tcl - Z7-10 clock freq is divided by 5 from 125MHz to 25MHz in clock_control.v - adds Zynq7000 v1.3 for lab2 --- lab1/verilog/z710/clock_control.v | 59 +- lab1/vivado/z710/generate_bitstream.tcl | 2 + lab1/vivado/z710/riscv-z710-v2020.tcl | 108 +-- lab1/vivado/z710v1.3/README.md | 87 +++ ...YNQ 7010 IO引脚分配总表_V1.1_20240604.xlsx | Bin 0 -> 22042 bytes .../resources/ZYNQ 7010开发板硬件资源.pdf | Bin 0 -> 2687524 bytes .../z710v1.3/resources/board-explain.png | Bin 0 -> 2434460 bytes .../z710v1.3/resources/运存DDR3计算.txt | 2 + lab2/src/main/scala/board/z710v1.3/Top.scala | 114 +++ lab2/src/test/scala/riscv/BoardTest.scala | 50 +- lab2/verilog/z710v1.3/clock_control.v | 33 + lab2/verilog/z710v1.3/top_test.v | 47 ++ lab2/vivado/z710v1.3/README.md | 87 +++ lab2/vivado/z710v1.3/generate_bitstream.tcl | 63 ++ lab2/vivado/z710v1.3/program_device.tcl | 24 + ...YNQ 7010 IO引脚分配总表_V1.1_20240604.xlsx | Bin 0 -> 22042 bytes .../resources/ZYNQ 7010开发板硬件资源.pdf | Bin 0 -> 2687524 bytes .../z710v1.3/resources/board-explain.png | Bin 0 -> 2434460 bytes .../z710v1.3/resources/运存DDR3计算.txt | 2 + lab2/vivado/z710v1.3/rv-z710v1.3-20.tcl | 700 ++++++++++++++++++ lab2/vivado/z710v1.3/z710v1.3.xdc | 31 + 21 files changed, 1299 insertions(+), 110 deletions(-) create mode 100644 lab1/vivado/z710v1.3/resources/ZYNQ 7010 IO引脚分配总表_V1.1_20240604.xlsx create mode 100644 lab1/vivado/z710v1.3/resources/ZYNQ 7010开发板硬件资源.pdf create mode 100644 lab1/vivado/z710v1.3/resources/board-explain.png create mode 100644 lab1/vivado/z710v1.3/resources/运存DDR3计算.txt create mode 100644 lab2/src/main/scala/board/z710v1.3/Top.scala create mode 100644 lab2/verilog/z710v1.3/clock_control.v create mode 100644 lab2/verilog/z710v1.3/top_test.v create mode 100644 lab2/vivado/z710v1.3/README.md create mode 100644 lab2/vivado/z710v1.3/generate_bitstream.tcl create mode 100644 lab2/vivado/z710v1.3/program_device.tcl create mode 100644 lab2/vivado/z710v1.3/resources/ZYNQ 7010 IO引脚分配总表_V1.1_20240604.xlsx create mode 100644 lab2/vivado/z710v1.3/resources/ZYNQ 7010开发板硬件资源.pdf create mode 100644 lab2/vivado/z710v1.3/resources/board-explain.png create mode 100644 lab2/vivado/z710v1.3/resources/运存DDR3计算.txt create mode 100644 lab2/vivado/z710v1.3/rv-z710v1.3-20.tcl create mode 100644 lab2/vivado/z710v1.3/z710v1.3.xdc diff --git a/lab1/verilog/z710/clock_control.v b/lab1/verilog/z710/clock_control.v index 30bc6e5..79c9f35 100644 --- a/lab1/verilog/z710/clock_control.v +++ b/lab1/verilog/z710/clock_control.v @@ -1,46 +1,25 @@ `timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2023/11/29 15:52:55 -// Design Name: -// Module Name: clock_control -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - +// fpga4student.com: FPGA projects, VHDL projects, Verilog projects +// Verilog project: Verilog code for clock divider on FPGA +// Top level Verilog code for clock divider on FPGA module clock_control( - input clk_in, + input clock_in, input enable_clk, - output clk_out - ); - - // if clock is divided - localparam clk_div = 2; // clock is diveded by half of divisor - reg [3:0] cnt = 4'd0; - reg out = 1'b0; - always @(posedge clk_in) begin - cnt <= cnt + 4'd1; - if (cnt >= (clk_div - 1)) begin - out <= ~out; - cnt <= 0; + output reg clock_out +); + reg[3:0] counter = 4'd0; + parameter DIVISOR = 4'd5; + // The frequency of the output clk_out + // = The frequency of the input clk_in divided by DIVISOR + // For example: Fclk_in = 50Mhz, if you want to get 1Hz signal to blink LEDs + // You will modify the DIVISOR parameter value to 28'd50.000.000 + // Then the frequency of the output clk_out = 50Mhz/50.000.000 = 1Hz + always @(posedge clock_in) + begin + counter <= counter + 4'd1; + if(counter>=(DIVISOR-1)) begin + counter <= 4'd0; end + clock_out <= ((counter code diff --git a/lab1/vivado/z710/riscv-z710-v2020.tcl b/lab1/vivado/z710/riscv-z710-v2020.tcl index dd04bb5..a68fb4e 100644 --- a/lab1/vivado/z710/riscv-z710-v2020.tcl +++ b/lab1/vivado/z710/riscv-z710-v2020.tcl @@ -3,7 +3,7 @@ # # riscv-z710-v2020.tcl: Tcl script for re-creating project 'riscv-z710-v2020' # -# Generated by Vivado on Mon Dec 25 11:27:52 +0800 2023 +# Generated by Vivado on Mon Nov 18 22:07:05 +0800 2024 # IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 # # This file contains the Vivado Tcl commands for re-creating the project to the state* @@ -23,14 +23,13 @@ # 2. The following source(s) files that were local or imported into the original project. # (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) # -# +# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/vivado/z710/riscv-z710-v2020/riscv-z710-v2020.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v" # # 3. The following remote source files that were added to the original project:- # -# "E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/Top.v" -# "E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/clock_control.v" -# "E:/Workplace/2022-fall-yatcpu-repo/lab1/vivado/z710/pre-generate-files/v2020/design_1/hdl/design_1_wrapper.v" -# "E:/Workplace/2022-fall-yatcpu-repo/lab1/vivado/z710/z710.xdc" +# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/verilog/z710/Top.v" +# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/verilog/z710/clock_control.v" +# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/vivado/z710/z710.xdc" # #***************************************************************************************** @@ -131,9 +130,14 @@ set files [list \ [file normalize "${origin_dir}/../../verilog/z710/Top.v"] \ [file normalize "${origin_dir}/../../verilog/z710/clock_control.v"] \ ] -# [file normalize "${origin_dir}/pre-generate-files/v2020/design_1/hdl/design_1_wrapper.v"] \ add_files -norecurse -fileset $obj $files +# Import local files from the original project +# set files [list \ +# [file normalize "${origin_dir}/riscv-z710-v2020/riscv-z710-v2020.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v" ]\ +# ] +# set imported_files [import_files -fileset sources_1 $files] + # Set 'sources_1' fileset file properties for remote files # None @@ -177,6 +181,7 @@ set obj [get_filesets sim_1] set obj [get_filesets sim_1] set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj set_property -name "top" -value "Top" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj set_property -name "top_file" -value "../../verilog/z710/Top.v" -objects $obj set_property -name "top_lib" -value "xil_defaultlib" -objects $obj @@ -190,10 +195,10 @@ set obj [get_filesets utils_1] # Adding sources referenced in BDs, if not already added if { [get_files Top.v] == "" } { - import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/Top.v" + import_files -quiet -fileset sources_1 ../../verilog/z710/Top.v } if { [get_files clock_control.v] == "" } { - import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/clock_control.v" + import_files -quiet -fileset sources_1 ../../verilog/z710/clock_control.v } @@ -307,7 +312,7 @@ proc cr_bd_design_1 { parentCell } { # Create ports set enable_clk [ create_bd_port -dir I -type data enable_clk ] set io_alive_led [ create_bd_port -dir O io_alive_led ] - set io_clock [ create_bd_port -dir I -type clk -freq_hz 50000000 io_clock ] + set io_clock [ create_bd_port -dir I -type clk -freq_hz 125000000 io_clock ] set io_reset [ create_bd_port -dir I -type rst io_reset ] # Create instance: Top_0, and set properties @@ -405,7 +410,7 @@ proc cr_bd_design_1 { parentCell } { CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \ CONFIG.PCW_ENET1_RESET_ENABLE {0} \ - CONFIG.PCW_ENET_RESET_ENABLE {1} \ + CONFIG.PCW_ENET_RESET_ENABLE {0} \ CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \ CONFIG.PCW_ENET_RESET_SELECT {} \ CONFIG.PCW_USB0_USB0_IO {