Fixing Z710 frequency TNS too large

- now Z7-10 vivado project no longer copy files to local folder, so vivado can auto update it in generate_bitstream.tcl
- Z7-10 clock freq is divided by 5 from 125MHz to 25MHz in clock_control.v
- adds Zynq7000 v1.3 for lab2

lab1/vivado/z710/generate_bitstream.tcl

@@ -14,6 +14,8 @@
 
 source open_project.tcl
 
+update_module_reference design_1_Top_0_0
+
 while 1 {
     if { [catch {launch_runs synth_1 -jobs 4 } ] } {
         regexp {ERROR: \[Common (\d+-\d+)]} $errorInfo -> code