mirror of
https://github.com/handsomezhuzhu/2025-yatcpu.git
synced 2026-02-20 20:10:14 +00:00
Fixing Z710 frequency TNS too large
- now Z7-10 vivado project no longer copy files to local folder, so vivado can auto update it in generate_bitstream.tcl - Z7-10 clock freq is divided by 5 from 125MHz to 25MHz in clock_control.v - adds Zynq7000 v1.3 for lab2
This commit is contained in:
PurplePower
@@ -1,46 +1,25 @@
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2023/11/29 15:52:55
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// Design Name:
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// Module Name: clock_control
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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// fpga4student.com: FPGA projects, VHDL projects, Verilog projects
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// Verilog project: Verilog code for clock divider on FPGA
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// Top level Verilog code for clock divider on FPGA
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module clock_control(
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input clk_in,
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input clock_in,
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input enable_clk,
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output clk_out
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);
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// if clock is divided
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localparam clk_div = 2; // clock is diveded by half of divisor
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reg [3:0] cnt = 4'd0;
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reg out = 1'b0;
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always @(posedge clk_in) begin
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cnt <= cnt + 4'd1;
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if (cnt >= (clk_div - 1)) begin
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out <= ~out;
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cnt <= 0;
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output reg clock_out
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);
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reg[3:0] counter = 4'd0;
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parameter DIVISOR = 4'd5;
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// The frequency of the output clk_out
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// = The frequency of the input clk_in divided by DIVISOR
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// For example: Fclk_in = 50Mhz, if you want to get 1Hz signal to blink LEDs
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// You will modify the DIVISOR parameter value to 28'd50.000.000
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// Then the frequency of the output clk_out = 50Mhz/50.000.000 = 1Hz
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always @(posedge clock_in)
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begin
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counter <= counter + 4'd1;
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if(counter>=(DIVISOR-1)) begin
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counter <= 4'd0;
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end
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clock_out <= ((counter<DIVISOR/2)?1'b1:1'b0) && enable_clk;
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end
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assign clk_out = out & enable_clk;
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// original clock
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// assign clk_out = clk_in & enable_clk;
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endmodule
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@@ -14,6 +14,8 @@
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source open_project.tcl
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update_module_reference design_1_Top_0_0
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while 1 {
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if { [catch {launch_runs synth_1 -jobs 4 } ] } {
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regexp {ERROR: \[Common (\d+-\d+)]} $errorInfo -> code
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@@ -3,7 +3,7 @@
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#
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# riscv-z710-v2020.tcl: Tcl script for re-creating project 'riscv-z710-v2020'
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#
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# Generated by Vivado on Mon Dec 25 11:27:52 +0800 2023
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# Generated by Vivado on Mon Nov 18 22:07:05 +0800 2024
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# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
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#
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# This file contains the Vivado Tcl commands for re-creating the project to the state*
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@@ -23,14 +23,13 @@
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# 2. The following source(s) files that were local or imported into the original project.
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# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
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#
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# <none>
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# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/vivado/z710/riscv-z710-v2020/riscv-z710-v2020.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v"
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#
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# 3. The following remote source files that were added to the original project:-
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#
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# "E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/Top.v"
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# "E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/clock_control.v"
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# "E:/Workplace/2022-fall-yatcpu-repo/lab1/vivado/z710/pre-generate-files/v2020/design_1/hdl/design_1_wrapper.v"
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# "E:/Workplace/2022-fall-yatcpu-repo/lab1/vivado/z710/z710.xdc"
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# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/verilog/z710/Top.v"
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# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/verilog/z710/clock_control.v"
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# "E:/Workplace/2023-fall-yatcpu-dev-test/lab1/vivado/z710/z710.xdc"
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#
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#*****************************************************************************************
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@@ -131,9 +130,14 @@ set files [list \
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[file normalize "${origin_dir}/../../verilog/z710/Top.v"] \
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[file normalize "${origin_dir}/../../verilog/z710/clock_control.v"] \
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]
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# [file normalize "${origin_dir}/pre-generate-files/v2020/design_1/hdl/design_1_wrapper.v"] \
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add_files -norecurse -fileset $obj $files
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# Import local files from the original project
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# set files [list \
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# [file normalize "${origin_dir}/riscv-z710-v2020/riscv-z710-v2020.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v" ]\
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# ]
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# set imported_files [import_files -fileset sources_1 $files]
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# Set 'sources_1' fileset file properties for remote files
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# None
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@@ -177,6 +181,7 @@ set obj [get_filesets sim_1]
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set obj [get_filesets sim_1]
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set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
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set_property -name "top" -value "Top" -objects $obj
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set_property -name "top_auto_set" -value "0" -objects $obj
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set_property -name "top_file" -value "../../verilog/z710/Top.v" -objects $obj
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set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
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@@ -190,10 +195,10 @@ set obj [get_filesets utils_1]
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# Adding sources referenced in BDs, if not already added
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if { [get_files Top.v] == "" } {
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import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/Top.v"
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import_files -quiet -fileset sources_1 ../../verilog/z710/Top.v
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}
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if { [get_files clock_control.v] == "" } {
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import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/clock_control.v"
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import_files -quiet -fileset sources_1 ../../verilog/z710/clock_control.v
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}
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@@ -307,7 +312,7 @@ proc cr_bd_design_1 { parentCell } {
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# Create ports
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set enable_clk [ create_bd_port -dir I -type data enable_clk ]
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set io_alive_led [ create_bd_port -dir O io_alive_led ]
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set io_clock [ create_bd_port -dir I -type clk -freq_hz 50000000 io_clock ]
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set io_clock [ create_bd_port -dir I -type clk -freq_hz 125000000 io_clock ]
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set io_reset [ create_bd_port -dir I -type rst io_reset ]
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# Create instance: Top_0, and set properties
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@@ -405,7 +410,7 @@ proc cr_bd_design_1 { parentCell } {
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CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
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CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \
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CONFIG.PCW_ENET1_RESET_ENABLE {0} \
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CONFIG.PCW_ENET_RESET_ENABLE {1} \
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CONFIG.PCW_ENET_RESET_ENABLE {0} \
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CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
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CONFIG.PCW_ENET_RESET_SELECT {<Select>} \
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CONFIG.PCW_EN_4K_TIMER {0} \
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@@ -467,55 +472,55 @@ proc cr_bd_design_1 { parentCell } {
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CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
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CONFIG.PCW_MIO_15_PULLUP {enabled} \
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CONFIG.PCW_MIO_15_SLEW {slow} \
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CONFIG.PCW_MIO_16_DIRECTION {out} \
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CONFIG.PCW_MIO_16_DIRECTION {inout} \
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CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_16_PULLUP {enabled} \
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CONFIG.PCW_MIO_16_SLEW {fast} \
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CONFIG.PCW_MIO_17_DIRECTION {out} \
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CONFIG.PCW_MIO_17_DIRECTION {inout} \
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CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_17_PULLUP {enabled} \
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CONFIG.PCW_MIO_17_SLEW {fast} \
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CONFIG.PCW_MIO_18_DIRECTION {out} \
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CONFIG.PCW_MIO_18_DIRECTION {inout} \
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CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_18_PULLUP {enabled} \
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CONFIG.PCW_MIO_18_SLEW {fast} \
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CONFIG.PCW_MIO_19_DIRECTION {out} \
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CONFIG.PCW_MIO_19_DIRECTION {inout} \
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CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_19_PULLUP {enabled} \
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CONFIG.PCW_MIO_19_SLEW {fast} \
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CONFIG.PCW_MIO_1_DIRECTION {out} \
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CONFIG.PCW_MIO_1_DIRECTION {inout} \
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CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
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CONFIG.PCW_MIO_1_PULLUP {enabled} \
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CONFIG.PCW_MIO_1_SLEW {slow} \
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CONFIG.PCW_MIO_20_DIRECTION {out} \
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CONFIG.PCW_MIO_20_DIRECTION {inout} \
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CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_20_PULLUP {enabled} \
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CONFIG.PCW_MIO_20_SLEW {fast} \
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CONFIG.PCW_MIO_21_DIRECTION {out} \
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CONFIG.PCW_MIO_21_DIRECTION {inout} \
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CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_21_PULLUP {enabled} \
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CONFIG.PCW_MIO_21_SLEW {fast} \
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CONFIG.PCW_MIO_22_DIRECTION {in} \
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CONFIG.PCW_MIO_22_DIRECTION {inout} \
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CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_22_PULLUP {enabled} \
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CONFIG.PCW_MIO_22_SLEW {fast} \
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CONFIG.PCW_MIO_23_DIRECTION {in} \
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CONFIG.PCW_MIO_23_DIRECTION {inout} \
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CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_23_PULLUP {enabled} \
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CONFIG.PCW_MIO_23_SLEW {fast} \
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CONFIG.PCW_MIO_24_DIRECTION {in} \
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CONFIG.PCW_MIO_24_DIRECTION {inout} \
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CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_24_PULLUP {enabled} \
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CONFIG.PCW_MIO_24_SLEW {fast} \
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CONFIG.PCW_MIO_25_DIRECTION {in} \
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CONFIG.PCW_MIO_25_DIRECTION {inout} \
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CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_25_PULLUP {enabled} \
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CONFIG.PCW_MIO_25_SLEW {fast} \
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CONFIG.PCW_MIO_26_DIRECTION {in} \
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CONFIG.PCW_MIO_26_DIRECTION {inout} \
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CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_26_PULLUP {enabled} \
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CONFIG.PCW_MIO_26_SLEW {fast} \
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CONFIG.PCW_MIO_27_DIRECTION {in} \
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CONFIG.PCW_MIO_27_DIRECTION {inout} \
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CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_27_PULLUP {enabled} \
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CONFIG.PCW_MIO_27_SLEW {fast} \
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@@ -599,7 +604,7 @@ proc cr_bd_design_1 { parentCell } {
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CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_45_PULLUP {enabled} \
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CONFIG.PCW_MIO_45_SLEW {slow} \
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CONFIG.PCW_MIO_46_DIRECTION {out} \
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CONFIG.PCW_MIO_46_DIRECTION {inout} \
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CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_46_PULLUP {enabled} \
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CONFIG.PCW_MIO_46_SLEW {slow} \
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@@ -639,7 +644,7 @@ proc cr_bd_design_1 { parentCell } {
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CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
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CONFIG.PCW_MIO_5_PULLUP {disabled} \
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CONFIG.PCW_MIO_5_SLEW {slow} \
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CONFIG.PCW_MIO_6_DIRECTION {out} \
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CONFIG.PCW_MIO_6_DIRECTION {inout} \
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CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
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CONFIG.PCW_MIO_6_PULLUP {disabled} \
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CONFIG.PCW_MIO_6_SLEW {slow} \
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@@ -798,8 +803,8 @@ proc cr_bd_design_1 { parentCell } {
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CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
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CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0} \
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CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
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CONFIG.PCW_USB0_RESET_ENABLE {1} \
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CONFIG.PCW_USB0_RESET_IO {MIO 46} \
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CONFIG.PCW_USB0_RESET_ENABLE {0} \
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CONFIG.PCW_USB0_RESET_IO {<Select>} \
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CONFIG.PCW_USB0_USB0_IO {<Select>} \
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CONFIG.PCW_USB1_RESET_ENABLE {0} \
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CONFIG.PCW_USB_RESET_ENABLE {1} \
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@@ -820,9 +825,9 @@ proc cr_bd_design_1 { parentCell } {
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# Create port connections
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connect_bd_net -net Top_0_io_led [get_bd_ports io_alive_led] [get_bd_pins Top_0/io_led]
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connect_bd_net -net Top_0_io_tx [get_bd_pins Top_0/io_tx] [get_bd_pins processing_system7_0/UART0_RX]
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connect_bd_net -net clock_control_0_clk_out [get_bd_pins Top_0/clock] [get_bd_pins clock_control_0/clk_out]
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connect_bd_net -net clock_control_0_clk_out [get_bd_pins Top_0/clock] [get_bd_pins clock_control_0/clock_out]
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connect_bd_net -net enable_clk_1 [get_bd_ports enable_clk] [get_bd_pins clock_control_0/enable_clk]
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connect_bd_net -net io_clock_1 [get_bd_ports io_clock] [get_bd_pins clock_control_0/clk_in]
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connect_bd_net -net io_clock_1 [get_bd_ports io_clock] [get_bd_pins clock_control_0/clock_in]
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connect_bd_net -net io_reset_1 [get_bd_ports io_reset] [get_bd_pins Top_0/reset]
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connect_bd_net -net xlconstant_0_dout [get_bd_pins Top_0/io_rx] [get_bd_pins xlconstant_0/dout]
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@@ -831,32 +836,32 @@ proc cr_bd_design_1 { parentCell } {
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# Perform GUI Layout
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regenerate_bd_layout -layout_string {
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"ActiveEmotionalView":"Default View",
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"Default View_ScaleFactor":"1.39048",
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"Default View_TopLeft":"-268,0",
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"Default View_ScaleFactor":"1.0",
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"Default View_TopLeft":"-329,-33",
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"ExpandedHierarchyInLayout":"",
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"guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:9.0 non-TLS
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# -string -flagsOSRD
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preplace port DDR -pg 1 -lvl 3 -x 560 -y 60 -defaultsOSRD
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preplace port FIXED_IO -pg 1 -lvl 3 -x 560 -y 80 -defaultsOSRD
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preplace port io_alive_led -pg 1 -lvl 3 -x 560 -y 310 -defaultsOSRD
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preplace port io_reset -pg 1 -lvl 0 -x 0 -y 300 -defaultsOSRD
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preplace port io_clock -pg 1 -lvl 0 -x 0 -y 220 -defaultsOSRD
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preplace port enable_clk -pg 1 -lvl 0 -x 0 -y 240 -defaultsOSRD
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preplace inst Top_0 -pg 1 -lvl 2 -x 390 -y 300 -defaultsOSRD
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preplace inst clock_control_0 -pg 1 -lvl 1 -x 130 -y 230 -defaultsOSRD
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preplace port DDR -pg 1 -lvl 3 -x 570 -y 60 -defaultsOSRD
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preplace port FIXED_IO -pg 1 -lvl 3 -x 570 -y 80 -defaultsOSRD
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preplace port enable_clk -pg 1 -lvl 0 -x -10 -y 240 -defaultsOSRD
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preplace port io_alive_led -pg 1 -lvl 3 -x 570 -y 310 -defaultsOSRD
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preplace port io_clock -pg 1 -lvl 0 -x -10 -y 220 -defaultsOSRD
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preplace port io_reset -pg 1 -lvl 0 -x -10 -y 300 -defaultsOSRD
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preplace inst processing_system7_0 -pg 1 -lvl 2 -x 400 -y 120 -defaultsOSRD
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preplace inst xlconstant_0 -pg 1 -lvl 1 -x 130 -y 360 -defaultsOSRD
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preplace inst processing_system7_0 -pg 1 -lvl 2 -x 390 -y 120 -defaultsOSRD
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preplace netloc xlconstant_0_dout 1 1 1 240J 320n
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preplace netloc clock_control_0_clk_out 1 1 1 240 230n
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preplace netloc Top_0_io_tx 1 2 1 540 140n
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preplace inst Top_0 -pg 1 -lvl 2 -x 400 -y 300 -defaultsOSRD
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preplace inst clock_control_0 -pg 1 -lvl 1 -x 130 -y 230 -defaultsOSRD
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preplace netloc Top_0_io_led 1 2 1 NJ 310
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preplace netloc io_reset_1 1 0 2 NJ 300 NJ
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preplace netloc io_clock_1 1 0 1 NJ 220
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preplace netloc Top_0_io_tx 1 2 1 550 130n
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preplace netloc clock_control_0_clk_out 1 1 1 250 230n
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preplace netloc enable_clk_1 1 0 1 NJ 240
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preplace netloc processing_system7_0_DDR 1 2 1 NJ 60
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preplace netloc processing_system7_0_FIXED_IO 1 2 1 NJ 80
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levelinfo -pg 1 0 130 390 560
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pagesize -pg 1 -db -bbox -sgen -120 0 690 420
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preplace netloc io_clock_1 1 0 1 NJ 220
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preplace netloc io_reset_1 1 0 2 NJ 300 NJ
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preplace netloc xlconstant_0_dout 1 1 1 250J 320n
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preplace netloc processing_system7_0_FIXED_IO 1 2 1 550J 80n
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preplace netloc processing_system7_0_DDR 1 2 1 550J 60n
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levelinfo -pg 1 -10 130 400 570
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||||
pagesize -pg 1 -db -bbox -sgen -130 0 700 420
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"
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}
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||||
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@@ -872,11 +877,10 @@ cr_bd_design_1 ""
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||||
set_property REGISTERED_WITH_MANAGER "1" [get_files design_1.bd ]
|
||||
set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files design_1.bd ]
|
||||
|
||||
# call make_wrapper to create wrapper files
|
||||
# make wrapper for design_1.db
|
||||
set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse design_1.bd] -top]
|
||||
add_files -norecurse -fileset sources_1 $wrapper_path
|
||||
|
||||
|
||||
# Create 'synth_1' run (if not found)
|
||||
if {[string equal [get_runs -quiet synth_1] ""]} {
|
||||
create_run -name synth_1 -part xc7z010clg400-1 -flow {Vivado Synthesis 2020} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
|
||||
|
||||
@@ -0,0 +1,87 @@
|
||||
# 如何使用脚本烧录 CPU 至 Zynq7010 FPGA V1.3_24/02 开发板并从 UART 读取输出
|
||||
|
||||
## 0. 预先准备
|
||||
|
||||
在执行下述步骤前，请确保完成：
|
||||
|
||||
1. 通过 CPUTest 确保实现无误.
|
||||
2. 在 `src\main\scala\z710v1.3\Top.scala` 运行 `VerilogGenerator` 并生成 `verilog\z710v1.3\Top.v` 。
|
||||
3. 确认您的板子确实为如下板子，**并调整好下图中 UART 选择的跳线（序号①处）**、连接好右侧的线。
|
||||
|
||||
<!--  -->
|
||||
<img src="resources/board-explain.png" alt="Alt Text" style="width:70%; height:auto;">
|
||||
|
||||
|
||||
|
||||
接下来将使用 Vivado 2020 或 2022 版本，更高版本应当也适用。您将在命令行调用这些工具，如果您已经将其所在目录添加到系统变量 PATH 中，则可直接在命令行中输入 `vivado` 进行调用，如目录 `E:\Xilinx\Vivado\2020.1\bin\vivado` 。
|
||||
若还没有添加，可以使用 E:\Xilinx\Vivado\2020.1\bin\vivado 来代替。
|
||||
|
||||
若您使用 2020.1 或较久版本的 Xilinx 工具，在 Windows Powershell 中执行将在额外弹出的窗口中运行 `vivado` 和 `xsct`。您可以在命令前添加 `cmd /c` 以指定其在 cmd 中运行并保留输出至本窗口。
|
||||
|
||||
**以下操作均默认在 `vivado/z710v1.3` 目录下打开终端并执行，您可以使用 cd 命令切换目录。**
|
||||
|
||||
|
||||
## 1. 生成 Vivado 项目
|
||||
|
||||
执行指令
|
||||
|
||||
```pwsh
|
||||
vivado -mode batch -source ./rv-z710v1.3-20.tcl
|
||||
```
|
||||
|
||||
这将生成 Vivado 项目，成功后应能看见 `rv-z710v1.3-20\rv-z710v1.3-20.xpr` 文件，注意中途输出有无报错。
|
||||
|
||||
## 2. 生成比特流文件
|
||||
|
||||
执行指令
|
||||
|
||||
```pwsh
|
||||
vivado -mode batch -source ./generate_bitstream.tcl
|
||||
```
|
||||
|
||||
这可能耗费较长时间，成功后，您应看见 `vivado\z710v1.3\rv-z710v1.3-20\rv-z710v1.3-20.runs\impl_1\design_1_wrapper.bit` 文件，或成功的输出信息（可能略有不同）：
|
||||
|
||||
```text
|
||||
...
|
||||
Creating bitmap...
|
||||
Creating bitstream...
|
||||
Writing bitstream ./design_1_wrapper.bit...
|
||||
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
|
||||
INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
128 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
write_bitstream completed successfully
|
||||
write_bitstream: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2220.910 ; gain = 419.598
|
||||
INFO: [Common 17-206] Exiting Vivado at Mon Nov 18 17:22:21 2024...
|
||||
[Mon Nov 18 17:22:26 2024] impl_1 finished
|
||||
wait_on_run: Time (s): cpu = 00:00:00 ; elapsed = 00:01:05 . Memory (MB): peak = 1074.246 ; gain = 0.000
|
||||
INFO: [Common 17-206] Exiting Vivado at Mon Nov 18 17:22:26 2024...
|
||||
```
|
||||
|
||||
## 3. 烧录至开发板
|
||||
|
||||
确认您的开发板已调整跳线为使用 UART3 接口，见 [预先准备](#0-预先准备)。
|
||||
|
||||
将您的开发板连接至电脑，包括连接 USB-UART 的 type-C 口线缆 和 JTAG 烧录接口共两个口。若成功连接，您可在设备管理器 - 端口（COM 和 LPT）中看到 `USB Serial Port (COMx)` 端口，其中 `x` 为端口号，后面打开串口时就使用这个 COM 口。
|
||||
|
||||
然后执行指令
|
||||
|
||||
```pwsh
|
||||
vivado -mode batch -source ./program_device.tcl
|
||||
```
|
||||
|
||||
若烧录成功，您应看见开发板中央的核心小板亮起绿灯，见 [预先准备](#0-预先准备) 图中的序号④。随后打开 PL_SW1 以开启时钟信号。
|
||||
|
||||
使用软件打开串口，您可以使用 MobaXTerm、XCom 或 Vitis 等来打开串口，设置 baud rate 为 115200，数据位 8、停止位 1、无校验位，即可收到 CPU 的输出 UART 信息，切换 PL_SW2 以发送 reset 信号重置 CPU 打印。
|
||||
|
||||
|
||||
|
||||
## For Maintainers
|
||||
|
||||
Zybo Z710 的时钟信号大抵不是 125MHz 而是 100MHz，因而 UART 模块使用的 frequency 参数要细调。
|
||||
本板子 Zynq7010 Soc 引了 PL 到 UART3，因此可以直连而不必通过 ARM 核心转发 UART 信号。但有以下需要注意的：
|
||||
|
||||
- reset 信号在 Vivado 2020 中不要连接至 button 或使用 Utility Vector Logic 做 NOT 门，否则会导致乱码输出，原因未知，好像可以将 TX 输出连接到一个 ILA debug 模块使输出正常。在 Vivado 2022 中使用则无问题。
|
||||
- `say_goodbye.c` 中打印间隔调大，因为时钟信号只有 50MHz
|
||||
- 其他引线等资源参考 resources 下的内容
|
||||
- 其他可参考 Z710 的 README.md
|
||||
|
||||
Binary file not shown.
BIN
lab1/vivado/z710v1.3/resources/ZYNQ 7010开发板硬件资源.pdf
Normal file
BIN
lab1/vivado/z710v1.3/resources/ZYNQ 7010开发板硬件资源.pdf
Normal file
Binary file not shown.
BIN
lab1/vivado/z710v1.3/resources/board-explain.png
Normal file
BIN
lab1/vivado/z710v1.3/resources/board-explain.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 2.3 MiB |
2
lab1/vivado/z710v1.3/resources/运存DDR3计算.txt
Normal file
2
lab1/vivado/z710v1.3/resources/运存DDR3计算.txt
Normal file
@@ -0,0 +1,2 @@
|
||||
1. 看有几块运存，本核心板有两块DDR3
|
||||
2. DDR的数据手册, DDR3的芯片是 NT5CC256M16EP-EK，一块是4Gb的，两块就是8Gb，即是整个核心板的DDR3为1GB
|
||||
Reference in New Issue
Block a user