finished lab1

lab2/verilog/z710/pass_through.v

@@ -0,0 +1,28 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2023/11/29 16:38:00
+// Design Name: 
+// Module Name: pass_through
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module pass_through(
+    input in,
+    output out
+    );
+    assign out = in;
+endmodule