mirror of
https://github.com/handsomezhuzhu/2025-yatcpu.git
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finished lab1
This commit is contained in:
TOKISAKIX\21168
BIN
lab1/vivado/z710/riscv-z710/design_1_wrapper.xsa
Normal file
BIN
lab1/vivado/z710/riscv-z710/design_1_wrapper.xsa
Normal file
Binary file not shown.
@@ -0,0 +1,459 @@
|
||||
{
|
||||
"design": {
|
||||
"design_info": {
|
||||
"boundary_crc": "0xD2682A7282870375",
|
||||
"device": "xc7z010clg400-1",
|
||||
"name": "design_1",
|
||||
"rev_ctrl_bd_flag": "RevCtrlBdOff",
|
||||
"synth_flow_mode": "Hierarchical",
|
||||
"tool_version": "2020.1",
|
||||
"validated": "true"
|
||||
},
|
||||
"design_tree": {
|
||||
"processing_system7_0": "",
|
||||
"clock_control_0": "",
|
||||
"xlconstant_0": "",
|
||||
"Top_0": ""
|
||||
},
|
||||
"interface_ports": {
|
||||
"DDR": {
|
||||
"mode": "Master",
|
||||
"vlnv": "xilinx.com:interface:ddrx_rtl:1.0",
|
||||
"parameters": {
|
||||
"CAN_DEBUG": {
|
||||
"value": "false",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TIMEPERIOD_PS": {
|
||||
"value": "1250",
|
||||
"value_src": "default"
|
||||
},
|
||||
"MEMORY_TYPE": {
|
||||
"value": "COMPONENTS",
|
||||
"value_src": "default"
|
||||
},
|
||||
"DATA_WIDTH": {
|
||||
"value": "8",
|
||||
"value_src": "default"
|
||||
},
|
||||
"CS_ENABLED": {
|
||||
"value": "true",
|
||||
"value_src": "default"
|
||||
},
|
||||
"DATA_MASK_ENABLED": {
|
||||
"value": "true",
|
||||
"value_src": "default"
|
||||
},
|
||||
"SLOT": {
|
||||
"value": "Single",
|
||||
"value_src": "default"
|
||||
},
|
||||
"MEM_ADDR_MAP": {
|
||||
"value": "ROW_COLUMN_BANK",
|
||||
"value_src": "default"
|
||||
},
|
||||
"BURST_LENGTH": {
|
||||
"value": "8",
|
||||
"value_src": "default"
|
||||
},
|
||||
"AXI_ARBITRATION_SCHEME": {
|
||||
"value": "TDM",
|
||||
"value_src": "default"
|
||||
},
|
||||
"CAS_LATENCY": {
|
||||
"value": "11",
|
||||
"value_src": "default"
|
||||
},
|
||||
"CAS_WRITE_LATENCY": {
|
||||
"value": "11",
|
||||
"value_src": "default"
|
||||
}
|
||||
}
|
||||
},
|
||||
"FIXED_IO": {
|
||||
"mode": "Master",
|
||||
"vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0",
|
||||
"parameters": {
|
||||
"CAN_DEBUG": {
|
||||
"value": "false",
|
||||
"value_src": "default"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"io_clock": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"CLK_DOMAIN": {
|
||||
"value": "design_1_clock",
|
||||
"value_src": "default"
|
||||
},
|
||||
"FREQ_HZ": {
|
||||
"value": "100000000"
|
||||
},
|
||||
"FREQ_TOLERANCE_HZ": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"INSERT_VIP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"PHASE": {
|
||||
"value": "0.000",
|
||||
"value_src": "default"
|
||||
}
|
||||
}
|
||||
},
|
||||
"io_alive_led": {
|
||||
"direction": "O"
|
||||
},
|
||||
"io_reset": {
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"POLARITY": {
|
||||
"value": "",
|
||||
"value_src": "weak"
|
||||
}
|
||||
}
|
||||
},
|
||||
"enable_clk": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"CLK_DOMAIN": {
|
||||
"value": "design_1_enable_clk_0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"FREQ_HZ": {
|
||||
"value": "100000000",
|
||||
"value_src": "default"
|
||||
},
|
||||
"FREQ_TOLERANCE_HZ": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"INSERT_VIP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"PHASE": {
|
||||
"value": "0.000",
|
||||
"value_src": "default"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"components": {
|
||||
"processing_system7_0": {
|
||||
"vlnv": "xilinx.com:ip:processing_system7:5.5",
|
||||
"xci_name": "design_1_processing_system7_0_0",
|
||||
"parameters": {
|
||||
"PCW_ACT_APU_PERIPHERAL_FREQMHZ": {
|
||||
"value": "666.666687"
|
||||
},
|
||||
"PCW_ACT_CAN_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_DCI_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.158730"
|
||||
},
|
||||
"PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_ENET1_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": {
|
||||
"value": "50.000000"
|
||||
},
|
||||
"PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": {
|
||||
"value": "200.000000"
|
||||
},
|
||||
"PCW_ACT_QSPI_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_SDIO_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_SMC_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_SPI_PERIPHERAL_FREQMHZ": {
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": {
|
||||
"value": "200.000000"
|
||||
},
|
||||
"PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": {
|
||||
"value": "111.111115"
|
||||
},
|
||||
"PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": {
|
||||
"value": "111.111115"
|
||||
},
|
||||
"PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": {
|
||||
"value": "111.111115"
|
||||
},
|
||||
"PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": {
|
||||
"value": "111.111115"
|
||||
},
|
||||
"PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": {
|
||||
"value": "111.111115"
|
||||
},
|
||||
"PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": {
|
||||
"value": "111.111115"
|
||||
},
|
||||
"PCW_ACT_UART_PERIPHERAL_FREQMHZ": {
|
||||
"value": "100.000000"
|
||||
},
|
||||
"PCW_ACT_WDT_PERIPHERAL_FREQMHZ": {
|
||||
"value": "111.111115"
|
||||
},
|
||||
"PCW_CLK0_FREQ": {
|
||||
"value": "50000000"
|
||||
},
|
||||
"PCW_CLK1_FREQ": {
|
||||
"value": "10000000"
|
||||
},
|
||||
"PCW_CLK2_FREQ": {
|
||||
"value": "10000000"
|
||||
},
|
||||
"PCW_CLK3_FREQ": {
|
||||
"value": "10000000"
|
||||
},
|
||||
"PCW_DDR_RAM_HIGHADDR": {
|
||||
"value": "0x1FFFFFFF"
|
||||
},
|
||||
"PCW_EN_EMIO_UART0": {
|
||||
"value": "1"
|
||||
},
|
||||
"PCW_EN_UART0": {
|
||||
"value": "1"
|
||||
},
|
||||
"PCW_EN_UART1": {
|
||||
"value": "1"
|
||||
},
|
||||
"PCW_FPGA_FCLK0_ENABLE": {
|
||||
"value": "1"
|
||||
},
|
||||
"PCW_MIO_48_IOTYPE": {
|
||||
"value": "LVCMOS 3.3V"
|
||||
},
|
||||
"PCW_MIO_48_PULLUP": {
|
||||
"value": "enabled"
|
||||
},
|
||||
"PCW_MIO_48_SLEW": {
|
||||
"value": "slow"
|
||||
},
|
||||
"PCW_MIO_49_IOTYPE": {
|
||||
"value": "LVCMOS 3.3V"
|
||||
},
|
||||
"PCW_MIO_49_PULLUP": {
|
||||
"value": "enabled"
|
||||
},
|
||||
"PCW_MIO_49_SLEW": {
|
||||
"value": "slow"
|
||||
},
|
||||
"PCW_MIO_TREE_PERIPHERALS": {
|
||||
"value": "unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 1#UART 1#unassigned#unassigned#unassigned#unassigned"
|
||||
},
|
||||
"PCW_MIO_TREE_SIGNALS": {
|
||||
"value": "unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#tx#rx#unassigned#unassigned#unassigned#unassigned"
|
||||
},
|
||||
"PCW_UART0_GRP_FULL_ENABLE": {
|
||||
"value": "0"
|
||||
},
|
||||
"PCW_UART0_PERIPHERAL_ENABLE": {
|
||||
"value": "1"
|
||||
},
|
||||
"PCW_UART0_UART0_IO": {
|
||||
"value": "EMIO"
|
||||
},
|
||||
"PCW_UART1_GRP_FULL_ENABLE": {
|
||||
"value": "0"
|
||||
},
|
||||
"PCW_UART1_PERIPHERAL_ENABLE": {
|
||||
"value": "1"
|
||||
},
|
||||
"PCW_UART1_UART1_IO": {
|
||||
"value": "MIO 48 .. 49"
|
||||
},
|
||||
"PCW_UART_PERIPHERAL_FREQMHZ": {
|
||||
"value": "100"
|
||||
},
|
||||
"PCW_UART_PERIPHERAL_VALID": {
|
||||
"value": "1"
|
||||
},
|
||||
"PCW_UIPARAM_ACT_DDR_FREQ_MHZ": {
|
||||
"value": "533.333374"
|
||||
},
|
||||
"PCW_USE_M_AXI_GP0": {
|
||||
"value": "0"
|
||||
}
|
||||
}
|
||||
},
|
||||
"clock_control_0": {
|
||||
"vlnv": "xilinx.com:module_ref:clock_control:1.0",
|
||||
"xci_name": "design_1_clock_control_0_0",
|
||||
"reference_info": {
|
||||
"ref_type": "hdl",
|
||||
"ref_name": "clock_control",
|
||||
"boundary_crc": "0x0"
|
||||
},
|
||||
"ports": {
|
||||
"clk_in": {
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"CLK_DOMAIN": {
|
||||
"value": "design_1_clock",
|
||||
"value_src": "default_prop"
|
||||
},
|
||||
"FREQ_HZ": {
|
||||
"value": "100000000",
|
||||
"value_src": "user_prop"
|
||||
},
|
||||
"PHASE": {
|
||||
"value": "0.000",
|
||||
"value_src": "default_prop"
|
||||
}
|
||||
}
|
||||
},
|
||||
"enable_clk": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"CLK_DOMAIN": {
|
||||
"value": "design_1_enable_clk_0",
|
||||
"value_src": "default_prop"
|
||||
}
|
||||
}
|
||||
},
|
||||
"clk_out": {
|
||||
"direction": "O",
|
||||
"parameters": {
|
||||
"CLK_DOMAIN": {
|
||||
"value": "",
|
||||
"value_src": "weak"
|
||||
},
|
||||
"FREQ_HZ": {
|
||||
"value": "",
|
||||
"value_src": "weak"
|
||||
},
|
||||
"PHASE": {
|
||||
"value": "",
|
||||
"value_src": "weak"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"xlconstant_0": {
|
||||
"vlnv": "xilinx.com:ip:xlconstant:1.1",
|
||||
"xci_name": "design_1_xlconstant_0_0"
|
||||
},
|
||||
"Top_0": {
|
||||
"vlnv": "xilinx.com:module_ref:Top:1.0",
|
||||
"xci_name": "design_1_Top_0_0",
|
||||
"reference_info": {
|
||||
"ref_type": "hdl",
|
||||
"ref_name": "Top",
|
||||
"boundary_crc": "0x0"
|
||||
},
|
||||
"ports": {
|
||||
"clock": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "reset",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
},
|
||||
"reset": {
|
||||
"type": "rst",
|
||||
"direction": "I"
|
||||
},
|
||||
"io_tx": {
|
||||
"direction": "O"
|
||||
},
|
||||
"io_rx": {
|
||||
"direction": "I"
|
||||
},
|
||||
"io_led": {
|
||||
"direction": "O"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"processing_system7_0_FIXED_IO": {
|
||||
"interface_ports": [
|
||||
"FIXED_IO",
|
||||
"processing_system7_0/FIXED_IO"
|
||||
]
|
||||
},
|
||||
"processing_system7_0_DDR": {
|
||||
"interface_ports": [
|
||||
"DDR",
|
||||
"processing_system7_0/DDR"
|
||||
]
|
||||
}
|
||||
},
|
||||
"nets": {
|
||||
"Top_0_io_tx": {
|
||||
"ports": [
|
||||
"Top_0/io_tx",
|
||||
"processing_system7_0/UART0_RX"
|
||||
]
|
||||
},
|
||||
"Top_0_io_led": {
|
||||
"ports": [
|
||||
"Top_0/io_led",
|
||||
"io_alive_led"
|
||||
]
|
||||
},
|
||||
"io_reset_1": {
|
||||
"ports": [
|
||||
"io_reset",
|
||||
"Top_0/reset"
|
||||
]
|
||||
},
|
||||
"io_clock_1": {
|
||||
"ports": [
|
||||
"io_clock",
|
||||
"clock_control_0/clk_in"
|
||||
]
|
||||
},
|
||||
"enable_clk_0_1": {
|
||||
"ports": [
|
||||
"enable_clk",
|
||||
"clock_control_0/enable_clk"
|
||||
]
|
||||
},
|
||||
"clock_control_0_clk_out": {
|
||||
"ports": [
|
||||
"clock_control_0/clk_out",
|
||||
"Top_0/clock"
|
||||
]
|
||||
},
|
||||
"xlconstant_0_dout": {
|
||||
"ports": [
|
||||
"xlconstant_0/dout",
|
||||
"Top_0/io_rx"
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,116 @@
|
||||
//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
|
||||
//Date : Tue Dec 12 00:14:50 2023
|
||||
//Host : Tokisakix running 64-bit major release (build 9200)
|
||||
//Command : generate_target design_1_wrapper.bd
|
||||
//Design : design_1_wrapper
|
||||
//Purpose : IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module design_1_wrapper
|
||||
(DDR_addr,
|
||||
DDR_ba,
|
||||
DDR_cas_n,
|
||||
DDR_ck_n,
|
||||
DDR_ck_p,
|
||||
DDR_cke,
|
||||
DDR_cs_n,
|
||||
DDR_dm,
|
||||
DDR_dq,
|
||||
DDR_dqs_n,
|
||||
DDR_dqs_p,
|
||||
DDR_odt,
|
||||
DDR_ras_n,
|
||||
DDR_reset_n,
|
||||
DDR_we_n,
|
||||
FIXED_IO_ddr_vrn,
|
||||
FIXED_IO_ddr_vrp,
|
||||
FIXED_IO_mio,
|
||||
FIXED_IO_ps_clk,
|
||||
FIXED_IO_ps_porb,
|
||||
FIXED_IO_ps_srstb,
|
||||
enable_clk,
|
||||
io_alive_led,
|
||||
io_clock,
|
||||
io_reset);
|
||||
inout [14:0]DDR_addr;
|
||||
inout [2:0]DDR_ba;
|
||||
inout DDR_cas_n;
|
||||
inout DDR_ck_n;
|
||||
inout DDR_ck_p;
|
||||
inout DDR_cke;
|
||||
inout DDR_cs_n;
|
||||
inout [3:0]DDR_dm;
|
||||
inout [31:0]DDR_dq;
|
||||
inout [3:0]DDR_dqs_n;
|
||||
inout [3:0]DDR_dqs_p;
|
||||
inout DDR_odt;
|
||||
inout DDR_ras_n;
|
||||
inout DDR_reset_n;
|
||||
inout DDR_we_n;
|
||||
inout FIXED_IO_ddr_vrn;
|
||||
inout FIXED_IO_ddr_vrp;
|
||||
inout [53:0]FIXED_IO_mio;
|
||||
inout FIXED_IO_ps_clk;
|
||||
inout FIXED_IO_ps_porb;
|
||||
inout FIXED_IO_ps_srstb;
|
||||
input enable_clk;
|
||||
output io_alive_led;
|
||||
input io_clock;
|
||||
input io_reset;
|
||||
|
||||
wire [14:0]DDR_addr;
|
||||
wire [2:0]DDR_ba;
|
||||
wire DDR_cas_n;
|
||||
wire DDR_ck_n;
|
||||
wire DDR_ck_p;
|
||||
wire DDR_cke;
|
||||
wire DDR_cs_n;
|
||||
wire [3:0]DDR_dm;
|
||||
wire [31:0]DDR_dq;
|
||||
wire [3:0]DDR_dqs_n;
|
||||
wire [3:0]DDR_dqs_p;
|
||||
wire DDR_odt;
|
||||
wire DDR_ras_n;
|
||||
wire DDR_reset_n;
|
||||
wire DDR_we_n;
|
||||
wire FIXED_IO_ddr_vrn;
|
||||
wire FIXED_IO_ddr_vrp;
|
||||
wire [53:0]FIXED_IO_mio;
|
||||
wire FIXED_IO_ps_clk;
|
||||
wire FIXED_IO_ps_porb;
|
||||
wire FIXED_IO_ps_srstb;
|
||||
wire enable_clk;
|
||||
wire io_alive_led;
|
||||
wire io_clock;
|
||||
wire io_reset;
|
||||
|
||||
design_1 design_1_i
|
||||
(.DDR_addr(DDR_addr),
|
||||
.DDR_ba(DDR_ba),
|
||||
.DDR_cas_n(DDR_cas_n),
|
||||
.DDR_ck_n(DDR_ck_n),
|
||||
.DDR_ck_p(DDR_ck_p),
|
||||
.DDR_cke(DDR_cke),
|
||||
.DDR_cs_n(DDR_cs_n),
|
||||
.DDR_dm(DDR_dm),
|
||||
.DDR_dq(DDR_dq),
|
||||
.DDR_dqs_n(DDR_dqs_n),
|
||||
.DDR_dqs_p(DDR_dqs_p),
|
||||
.DDR_odt(DDR_odt),
|
||||
.DDR_ras_n(DDR_ras_n),
|
||||
.DDR_reset_n(DDR_reset_n),
|
||||
.DDR_we_n(DDR_we_n),
|
||||
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
|
||||
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
|
||||
.FIXED_IO_mio(FIXED_IO_mio),
|
||||
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
|
||||
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
|
||||
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
|
||||
.enable_clk(enable_clk),
|
||||
.io_alive_led(io_alive_led),
|
||||
.io_clock(io_clock),
|
||||
.io_reset(io_reset));
|
||||
endmodule
|
||||
376
lab1/vivado/z710/riscv-z710/riscv-z710.xpr
Normal file
376
lab1/vivado/z710/riscv-z710/riscv-z710.xpr
Normal file
@@ -0,0 +1,376 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2020.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="49" Path="C:/Users/21168/Desktop/2023-fall-yatcpu-repo/lab2/vivado/z710/riscv-z710/riscv-z710.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="668831b5ccb743abb1dad41da490586a"/>
|
||||
<Option Name="Part" Val="xc7z010clg400-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirIES" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PSRCDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../../../../lab4/verilog/z710/clock_control.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../verilog/z710/Top.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci">
|
||||
<Proxy FileSetName="design_1_processing_system7_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_clock_control_0_0/design_1_clock_control_0_0.xci">
|
||||
<Proxy FileSetName="design_1_clock_control_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_Top_0_0/design_1_Top_0_0.xci">
|
||||
<Proxy FileSetName="design_1_Top_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/bd/design_1/hdl/design_1_wrapper.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../../lab4/verilog/z710/Top_reset.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../../lab4/verilog/z710/pass_through.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../../lab4/verilog/z710/uart_control.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="design_1_wrapper"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/../z710.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../../../../lab4/verilog/z710/test.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../../lab4/verilog/z710/top_test.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="design_1_wrapper"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="design_1_processing_system7_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_processing_system7_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="design_1_processing_system7_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="design_1_clock_control_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_clock_control_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="design_1_clock_control_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="design_1_Top_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_Top_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="design_1_Top_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ActiveHDL">
|
||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="11">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_processing_system7_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_processing_system7_0_0" Part="xc7z010clg400-1" ConstrsSet="design_1_processing_system7_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_processing_system7_0_0_synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_clock_control_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_clock_control_0_0" Part="xc7z010clg400-1" ConstrsSet="design_1_clock_control_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_clock_control_0_0_synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_Top_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_Top_0_0" Part="xc7z010clg400-1" ConstrsSet="design_1_Top_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_Top_0_0_synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_processing_system7_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_processing_system7_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_processing_system7_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_clock_control_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_clock_control_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_clock_control_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_Top_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="design_1_Top_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_Top_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
Reference in New Issue
Block a user