finished lab1

lab1/verilog/z710/Top_reset.v

@@ -0,0 +1,32 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2023/12/01 16:32:40
+// Design Name: 
+// Module Name: Top_reset
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Top_reset(
+    input reset
+    );
+    initial begin
+        reset = 1;
+        #25 reset = 0;
+    end
+    
+    
+endmodule