finished lab1

lab1/verilog/z710/Top_reset.v

@@ -0,0 +1,32 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2023/12/01 16:32:40
+// Design Name: 
+// Module Name: Top_reset
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Top_reset(
+    input reset
+    );
+    initial begin
+        reset = 1;
+        #25 reset = 0;
+    end
+    
+    
+endmodule

lab1/verilog/z710/clock_control.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2023/11/29 15:52:55
+// Design Name: 
+// Module Name: clock_control
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module clock_control(
+    input clk_in,
+    input enable_clk,
+    output clk_out
+    );
+    
+    // if clock is divided
+    localparam clk_div = 2; // clock is diveded by half of divisor
+    reg [3:0] cnt = 4'd0;
+    reg out = 1'b0;
+    always @(posedge clk_in) begin 
+        cnt <= cnt + 4'd1;
+        if (cnt >= (clk_div - 1)) begin
+            out <= ~out;
+            cnt <= 0;
+        end
+    end
+    assign clk_out = out & enable_clk;
+    
+    
+    // original clock
+//    assign clk_out = clk_in & enable_clk;
+    
+endmodule

lab1/verilog/z710/pass_through.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2023/11/29 16:38:00
+// Design Name: 
+// Module Name: pass_through
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module pass_through(
+    input in,
+    output out
+    );
+    assign out = in;
+endmodule

lab1/verilog/z710/top_test.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2023/12/01 15:46:54
+// Design Name: 
+// Module Name: top_test
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module top_test(
+
+    );
+    
+    reg clock;
+    reg reset;
+    reg constant_zero = 1'b0;
+    
+    wire io_led, io_tx;
+    
+    localparam CLK_PERIOD = 10;
+    initial begin
+        clock = 1'b0;
+        forever #( CLK_PERIOD / 2 ) clock = ~clock;
+    end
+    
+    
+    initial begin
+        reset = 1;  // need a down edge to init all components
+        #(CLK_PERIOD)  reset = 0;  // NOTE!!: must happen together with clock down edge!
+    end
+    
+    Top mytop(clock, reset, io_tx, constant_zero, io_led );
+    
+endmodule

lab1/verilog/z710/uart_control.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2023/11/30 00:51:08
+// Design Name: 
+// Module Name: uart_control
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module uart_control(
+    input enable_uart,
+    input tx_in,
+    output tx_out
+    );
+    assign tx_out = (enable_uart) ? tx_in : 1'h1;
+
+endmodule