zzh/2025-yatcpu
1
0
Fork 0
mirror of https://github.com/handsomezhuzhu/2025-yatcpu.git synced 2026-02-20 20:10:14 +00:00
Code Issues Packages Projects Releases Wiki Activity

Fixed vivado script import path error

Browse Source
This commit is contained in:
PurplePower
2023-12-27 14:01:29 +08:00
parent b7871a2c9b
commit d79780a480
4 changed files with 8 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
lab1/vivado/z710/riscv-z710-v2020.tcl
View File

@@ -190,10 +190,10 @@ set obj [get_filesets utils_1]
# Adding sources referenced in BDs, if not already added # Adding sources referenced in BDs, if not already added
if { [get_files Top.v] == "" } { if { [get_files Top.v] == "" } {
import_files -quiet -fileset sources_1 E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/Top.v import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/Top.v"
} }
if { [get_files clock_control.v] == "" } { if { [get_files clock_control.v] == "" } {
import_files -quiet -fileset sources_1 E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/clock_control.v import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/clock_control.v"
} }

4
lab2/vivado/z710/riscv-z710-v2020.tcl
View File

@@ -190,10 +190,10 @@ set obj [get_filesets utils_1]
# Adding sources referenced in BDs, if not already added # Adding sources referenced in BDs, if not already added
if { [get_files Top.v] == "" } { if { [get_files Top.v] == "" } {
import_files -quiet -fileset sources_1 E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/Top.v import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/Top.v"
} }
if { [get_files clock_control.v] == "" } { if { [get_files clock_control.v] == "" } {
import_files -quiet -fileset sources_1 E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/clock_control.v import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/clock_control.v"
} }

4
lab3/vivado/z710/riscv-z710-v2020.tcl
View File

@@ -190,10 +190,10 @@ set obj [get_filesets utils_1]
# Adding sources referenced in BDs, if not already added # Adding sources referenced in BDs, if not already added
if { [get_files Top.v] == "" } { if { [get_files Top.v] == "" } {
import_files -quiet -fileset sources_1 E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/Top.v import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/Top.v"
} }
if { [get_files clock_control.v] == "" } { if { [get_files clock_control.v] == "" } {
import_files -quiet -fileset sources_1 E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/clock_control.v import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/clock_control.v"
} }

4
lab4/vivado/z710/riscv-z710-v2020.tcl
View File

@@ -190,10 +190,10 @@ set obj [get_filesets utils_1]
# Adding sources referenced in BDs, if not already added # Adding sources referenced in BDs, if not already added
if { [get_files Top.v] == "" } { if { [get_files Top.v] == "" } {
import_files -quiet -fileset sources_1 E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/Top.v import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/Top.v"
} }
if { [get_files clock_control.v] == "" } { if { [get_files clock_control.v] == "" } {
import_files -quiet -fileset sources_1 E:/Workplace/2022-fall-yatcpu-repo/lab1/verilog/z710/clock_control.v import_files -quiet -fileset sources_1 "${origin_dir}/../../verilog/z710/clock_control.v"
} }